GB2229890A

GB2229890A - Teletext broadcasting signal generating and receiving apparatus

Info

Publication number: GB2229890A
Application number: GB9004691A
Authority: GB
Inventors: Yoshikazu Tomida; Osamu Yamada; Toru Kuroda
Original assignee: Nippon Hoso Kyokai NHK; Sanyo Electric Co Ltd; Japan Broadcasting Corp
Current assignee: Sanyo Electric Co Ltd; Japan Broadcasting Corp
Priority date: 1989-03-03
Filing date: 1990-03-02
Publication date: 1990-10-03
Anticipated expiration: 2010-03-02
Also published as: JP2720189B2; JPH02231892A; HK69594A; GB2229890B; CN1045323A; GB9004691D0; CN1027668C

Abstract

In a teletext broadcasting signal generating apparatus, a PLL circuit 15 generates a clock signal having a bit rate equal to a relatively single fraction e.g. 15/11, of the frequency of the color subcarrier signal, and having identical phase with identical timing in a corresponding horizontal scanning period after a predetermined number of field periods eg after eight fields. An 8F signal having a period of eight fields is generated from an 8F signal generating circuit 29 in response to a synchronizing signal. A timing signal representing a timing of a leading edge of a framing code in a predetermined horizontal scanning period of each field is generated from a multiplexes position timing generating circuit 19 in response to leading edges of the framing code and character data are defined according to the timing in the predetermined horizontal scanning period of each field. The fraction may be 14/11, 16/11 or 8/5 instead of 15/11, the predetermined number of field periods being 4, 2 or 10 respectively instead of 8. <IMAGE>

Description

TITLE OF THE INVENTION Text Broadcasting Signal Generating Apparatus and Text Broadcasting Signal Receiving Apparatus BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to text broadcasting system generating apparatus and text broadcasting signal receiving apparatus. Particularly, it relates to a text broadcasting signal generating apparatus which generates a clock signal necessary for sampling data in synchronization with a frequency of a color subcarrier signal and multiplexes a framing code and character data in a horizontal period in a vertical blanking period, thereby generating a text broadcasting signal, and to a text broadcasting signal receiving apparatus which receives the text broadcasting signal thus generated.

Description of the Background Art Text broadcasting is a new broadcasting system in which character/graphic information is transmitted as a digital signal in a multiplexed manner in a vertical blanking period of a television video signal and a receiving station converts it to a television signal to be displayed. The text broadcasting has an advantage that programs such as news or weather broadcast programs can be transmitted repeatedly with the latest information.

Fig. 46 is a diagram showing a hierarchical structure of a text broadcasting signal in the generally known NTSC system. Referring to Fig. 46, a character signal is transmitted in a manner multiplexed with 10th H to 21st H (H being one horizontal scanning period) in a first field in a vertical blanking period and 273rd H to 284th H in a second field. Hereinafter, the 10th H, 21st H, 273rd H, 284th H etc. are simply referred to as 10H, 21H, 273H, 284H, etc. The character signal includes a synchronizing part and a data packet. The synchronizing part includes a clock run-in (CR) and a framing code (FC) and the data packet includes a data block and a check code. The clock run-in is provided for bit synchronization; and it is a 16-bit signal repeating "1" and "0".The framing code is provided for byte synchronization; it is an 8-bit signal of '11100101 having a l-bit error correcting function.

According to the NTSC system, relations as indicated below exist in a vertical frequency (fv:59.94Hz), a horizontal frequency (f:l5 734kHz) and a color subcarrier frequency (fsc:3.57945MHz).

fV=2/525-fH fSC=455/2*fH More specifically, according to the NTSC system, the color subcarrier frequency f and the horizontal frequency fH are in the relation proportional to a fraction having the integer 2 as a denominator and the integer 455 as a numerator. A frequency fCK of sampling clocks of the character signal is selected as follows.

CK 8/5-fsc=5-727272MHz Assuming that 1f CK is 1 bit, 1H (one horizontal scanning period) has 364 bits. As described above, the frequency fCK of sampling clocks is an integral multiple of H and accordingly if the character signal is applied with a unit of 1H of the video signal, it can be multiplexed always in the same timing position for each H.

If the character signals are multiplexed in the same position of each horizontal period in a vertical blanking period, a position having a framing code of the character signal exists for 364 clocks if fCK is regarded as a unit, and error correction can be carried out by utilizing not only the l-bit error correcting function of the framing code itself but also its periodicity. For example, if character signals are multiplexed in 14H, 15H, 16H in a vertical blanking period, a framing code is detected from the character signal multiplexed at first in 14H.

Sampling clocks are counted by a counter based on that framing code and when the count value attains 364, a pulse is outputted and the next framing code should exist in this position as prescribed.

If the circuit is constructed so that a framing code exists even if it is damaged by impulse noise or the like, its error correction effect is considerably improved.

Thus, according to the text broadcasting system generally adopted in Japan, there are two main features that a sampling clock signal is reproduced from a color subcarrier signal and that the error correction effect of a framing code is enhanced by utilizing the periodicity of the framing code.

On the other hand, teletext is proposed in Great Britain as one of PAL text broadcasting systems.

According to the PAL system, relations of a vertical frequency (fv:50Hz), a horizontal frequency (fH:15.625kHz), and a color subcarrier frequency (fSc:4.43361875MHz) are as follows.

fV:=2/625ofH V.

sC=284114 . fH +25 H# In the above indicated teletext, the sampling clock frequency is selected to be 6.9375MHz. This sampling clock frequency fCK is not an integral multiple of the color subcarrier frequency fSC. Consequently, according to the teletext, a sampling clock signal is reproduced in synchronization with a clock run-in. However, a clock run-in is outputted only for one field. Since it is outputted only for 1/50sec, the reliability of the reproduced sampling clock is deteriorated.

As described above, the teletext in the PAL system has the disadvantage that the reliability of sampling clock is deteriorated compared with the Japanese NTSC system. However, if the Japanese NTSC system is to be applied to the PAL system to overcome this disadvantage, a suitable sampling frequency, namely, bit rate can not be selected from the relations of the vertical frequency fvt the horizontal frequency f and the color subcarrier frequency fSC. If a very complicated phase-locked loop (PLL) is adopted, it may be possible to select a bit rate equal to an integral multiple of a horizontal frequency but it is difficult to realize such a circuit.

Therefore, it may be considered to select a sampling clock frequency fCK to be in a relation of a fraction having a denominator of a relatively simple integer and a numerator of a relative simple integer. For example, the sampling clock frequency fCK is selected to be in the following relation.

fcK=l4//ll fSC =5.6427875MHz In this case, lH=361.1384 bits and there is a decimal part of 0.1384.

Fig. 47 is a waveform diagram of character signals multiplexed in 7H (320H), 8H (321H), 8H (322H), ..., 22H (335H) in the case of lH=361.1384 bits. As is evident from Fig. 47, since there is a fraction of 0.1384 bit in each H period, the phase of a leading edge of a character signal advances for 0.1384 bit in each of the 7H, 8H, 9H, ..., 22H periods. Consequently, the leading edges of the character signals in the respective horizontal scanning periods in the vertical blanking period of the next field are further advanced and in some field, the character signal is advanced as far as a color burst or horizontal synchronizing signal position, exerting unfavorable effect on normal broadcasting.

In addition, since the color subcarrier frequency f in the above mentioned teletext is not an integral multiple of the horizontal frequency fH, a framing code is reproduced only by utilizing the l-bit error correcting function of itself and as is different from the system generally adopted in Japan, the error correction effect can not be enhanced by utilizing the periodicity of the framing code.

SUMMARY OF THE INVENTION Therefore, a principal object of the present invention is to provide a text broadcasting signal generating apparatus capable of reproducing a sampling clock from a signal having a component of a color subcarrier frequency and generating a text broadcasting signal with a position of a character signal not exerting any unfavorable effect on color burst or a horizontal synchronizing signal for each horizontal period of a vertical blanking period of each field.

Another object of the present invention is to provide a text broadcasting signal generating apparatus capable of generating a text broadcasting signal with an enhanced error correction effect of a framing code by making it possible to predict detection timing of the framing code.

A further object of the present invention is to provide a text broadcasting signal receiving apparatus capable of reproducing a sampling clock from a color subcarrier signal and demodulating in a good condition a character signal with phases different for respective horizontal scanning periods of each field.

A further object of the present invention is to provide a text broadcasting signal receiving apparatus with an enhanced error correction effect using a framing code having periodicity.

Briefly stated, according to the present invention, a clock signal is generated in synchronization with a color subcarrier signal, the clock signal having a bit rate of a relation of a fraction consisting of a denominator of a relatively simple first integer and a numerator of a second integer different from the first integer with respect to a frequency of the color subcarrier signal, and having periodicity attaining the same phase at the same timing in a corresponding horizontal scanning period for a predetermined number of fields. In response to a synchronizing signal, a periodicity signal having a periodicity of a predetermined number of fields is generated.In response to the generated clock signal and periodicity signal, a timing signal indicating leading timing of a framing code in a predetermined horizontal scanning period of each field is generated, and in response to the timing signal, a signal is provided in a multiplexed manner where leading edges of the framing code and the character data are defined according to the leading timing in a predetermined horizontal scanning period of each field.

According to a preferred embodiment, a second clock signal of a frequency twice that of the above mentioned clock signal is generated and this second clock signal is twice frequency-divided, so that the clock signal is provided. The first and second clock signals have a delay therebetween by an amount within one period of the clock signal and phases of the periodicity signal and the delayed clock signal are compared and detected, so that an amount of a difference of the phases is detected by the delayed second clock signal. In response to the detection output, the delay amount is changed so that a phase of the periodicity signal is within a prescribed range with respect to the phase of the clock signal.

According to another aspect of the invention, a text broadcasting signal receiving apparatus for receiving a text broadcasting signal is provided and this apparatus receives a television broadcasting signal containing a framing code and character data in a multiplexed form, so that a synchronizing signal is separated from the received television broadcasting signal. A clock signal is generated which synchronizes with a color subcarrier signal and has a bit rate of a relation of a fraction consisting of a denominator of a relatively simple first integer and a numerator of a second integer different from the first integer with respect to a frequency of the color subcarrier signal, and has a periodicity attaining the same phase at the same timing in a corresponding horizontal scanning period for a predetermined number of fields.In response to the separated synchronizing signal, a periodicity signal having a period of a predetermined number of fields is generated. A framing code is detected from a text broadcasting signal multiplexed in the received television signal, and in response to the first framing code detection signal and periodicity signal of the first field out of the detected predetermined number of fields, a framing code detection signal is formed at timing in a predetermined horizontal scanning period of each field. In response to the framing code detection signal thus formed and the clock signal, character data of the text broadcasting signal is demodulated.

According to a preferred embodiment of the invention, the first and second fields are detected in response to the synchronizing signal and the detection signal of the detected first field is counted, whereby a periodicity signal of a predetermined number of fields is outputted.

According to a further preferred embodiment, a vertical synchronizing signal is separated from the synchronizing signal and synchronous/asynchronous states between the periodicity signal and the separated synchronizing signal are detected. In response to the detection of a deviation in synchronization of the periodicity signal with respect to the vertical synchronizing signal, the deviation in synchronization is corrected.

According to a further preferred embodiment, in response to detection of the first framing code, the clock signal is counted and a timing signal for predicting a detection position of a framing code coming after the subsequent predetermined number of fields is generated.

match/mismatch of phases of the detected first framing code detection signal and the predicting timing signal are determined and in response to the-determination result, timing of detection of the framing code is defined in a predetermined horizontal scanning period of each field.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a relative positional relation of character-multiplexed signals of respective H's in one field with FCK=14/11xfSC.

Fig. 2 is a diagram showing a relative positional relation of a text broadcasting signal in respective fields.

Fig. 3 is a diagram showing a relative positional relation of character-multiplexed signals of respective H's in one field with fcK=15/llxfsc.

Fig. 4 is a diagram showing a relative positional relation of character-multiplexed signals in respective fields with the above mentioned condition.

Fig. 5 is a diagram showing a relative positional relation of character-multiplexed signals of respective H's in one field with fCK=16/11xfSC.

Fig. 6 is a diagram showing a relative positional relation of character-multiplexed signals in respective fields with the above mentioned condition.

Fig. 7 is a diagram showing a relative positional relation of character-multiplexed signals of respective H's in one field with fCK = 8/5xfSC.

Fig. 8 is a diagram showing a relative positional relation of character-multiplexed signals in respective fields with the above mentioned condition.

Fig. 9 is a diagram showing an entire construction of a multiplexed text broadcasting system according to an embodiment of the present invention.

Fig. 1.0 is a block diagram of a character signal multiplexing apparatus with fcK=14/llxfsc.

Fig. 11 is a block diagram of a character signal multiplexing apparatus with fcK=15/llxfsc.

Fig. 12 is a block diagram of a character signal multiplying apparatus with fcK=16/llxfsc.

Fig. 13 is a block diagram showing an example of a character signal multiplexing apparatus with Fig. 14 is a block diagram showing another example of a character signal multiplexing apparatus with fCK=14/11xfSC.

Fig. 15 is a block diagram showing another example of a character signal multiplexing apparatus with fcK=8/5xfsc .

Fig. 16 is a block diagram showing a PLL circuit for generating the signal 2fCK shown in Figs. 10 to 12.

Fig. 17 is a block diagram of a PLL circuit for generating the signal fCK shown in Fig. 14.

Fig. 18 is a block diagram of a PLL circuit for generating the signal 2fCK shown in Fig. 13.

Fig. 19 is a block diagram of a PLL circuit for generating the signal fCK shown in Fig. 15.

Fig. 20 is a waveform diagram showing relations between a vertical synchronizing signal and 4-field, 8-field, 2-field and 10-field period signals.

Fig. 21 is a specified block diagram showing the fCK automatic phase adjusting circuit shown in Fig. 10.

Fig. 22 is a waveform diagram of the fCK automatic phase adjusting circuit shown in Fig. 21.

Fig. 23 is a block diagram of the address generating circuit shown in Fig. 10.

Fig. 24 is a block diagram of the address generating circuit shown in Fig. 12.

Figs. 25, 26 and 27 are waveform diagrams of the address generating circuit shown in Fig. 23.

Fig. 28 is a waveform diagram with f =16/llxf in CK ' SC the address generating circuit shown in Fig. 24.

Fig. 29 is a waveform diagram with fcK=8/5xfSc in the address generating circuit shown in Fig. 24.

Fig. 30 is a block diagram showing an entire construction of a multiplexed text broadcasting receiving apparatus.

Fig. 31 is a block diagram of the character signal processing circuit shown in Fig. 30.

Fig. 32 is a block diagram showing a kf signal generating circuit and a protection circuit.

Figs. 33, 34 and 35 are waveform diagrams of the kf signal generating circuit.

Figs. 36 is a block diagram showing a framing code detection protecting circuit.

Figs. 37, 38, 39, 40, 41, 42, 43, 44 and 45 are waveform diagrams of the framing code detection protecting circuit.

Fig. 46 is a diagram showing a hierarchical structure of a text broadcasting signal in the NTSC system adopted in Japan.

Fig. 47 is a waveform diagram of character signals multiplexed in a video signal in each H with 1H=361.1384 bits.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with regard to four cases where a bit rate of a frequency fCK of a sampling clock signal is set to fCK=14/11xfSC, 15/11xfSC, 16/llxfSc, and 8/5xfSc.

Fig. 1 is a waveform diagram showing a relative positional relation of character-multiplexed signals in respective H's in one field with the condition of fcK=14/llxfsc and Fig. 2 is a waveform diagram showing a relative positional relation of character-multiplexed signals in respective fields with the above mentioned condition.

As described previously in connection with Fig. 47, if the condition of fcK=14/llxfsc is selected, fcK=361.1384xfH=(361+0.1384)xfH=112855.75xfv. Since the frequency fSC of the color subcarrier signal is fSc=4.43361875MHz, the sampling clock frequency is fcK=5.6427875MHz. From the above described relations, if a character signal is multiplexed for 361 bits for 1H, the character signal of 8H (321H) has a phase of its leading edge advanced by 0.1384 bit with respect to the character signal of 7H (320H) and the character signal of 22H (335H) has a phase advanced by 2.076 bits.

A relative positional relation of character signals in respective fields is as shown in Fig. 2. More specifically, the leading edge of the character signal of 320H of the second field after 313 H's with respect to the phase of the character signal of 7H of the first field is the 113037th bit and thus the phase is advanced by 0.3192 bit. The leading edge of the character signal in 7H of the third field is the 225712.5th bit and the phase is further advanced with respect to the character signal in 320H of the second field. As described afterwards, according to the present invention, the sampling clock signal is switched to an inverse phase with respect to the frequency fSC of the color subcarrier signal for two fields, whereby the above mentioned phase matches with that of the character signal in 7H of the first field.

Fig. 3 is a waveform diagram showing a relative positional relation of character-multiplexed signals in respective H's in one field with fcK=15/llxfsc, and Fig. 4 is a waveform diagram showing a relative positional relation of character-multiplexed signals in respective fields with the above mentioned condition.

Referring to Fig. 3, if fcK=15/llxfsc is selected, f =386.934xf =(387-0.066) x fH=120916.975xfv. Since fsc=4.43361875MHz, the sampling clock frequency is fCk=6.04584375MHz. From this relation, if the signals are multiplexed for 387 bits for 1H, the phase of the character signal in 8H (321H) is delayed by 0.066 bit and the phase in 9H (322H) is delayed by 0.132 bit, and the phase in 22H (335H) is delayed by 0.99 bit.

In each field, multiplexed positions coincide for eight fields based on the relation of fCK=967335 x as shown in Fig. 4.

Fig. 5 is a waveform diagram showing a relative positional relation of multiplexed character signals in respective H's in one field with fCK=16/11xfSC, and Fig. 6 is a waveform diagram showing a relative positional relation of multiplexed character signals in respective fields with the above mentioned condition.

Referring to Fig. 5, if f=l6/llxf SC is selected, a relation of fCK=412.7296 x fH= (413-0.2704) x fH=128978 x fV is obtained and since fSc=4.43361875MHz, fcK=6.4489MHz.

From these relations, if the signals are multiplexed for 413 bits for 1H, the phase of the character signal in 8H (321H) is delayed by 0.2704 bit with respect to that of the character signal in 7H (320H) and the phase in 22H (335H) is delayed by 4.056 bits.

A relative positional relation of multiplexed character signals in respective fields is as shown in Fig.

6. With fcK=128978xfv, an interval of 313 H's is provided from the first field to the second field and an interval of 312 H's is provided from. the second field to the first field. Accordingly, multiplexed positions coincide for two fields.

Fig. 7 is a diagram showing a relative positional relation of multiplexed character signals in respective H's in one field with fCK=8/5xfSC, and Fig. 8 is a diagram showing a relative positional relation of multiplexed character signals in respective fields with the above mentioned condition.

According to the PAL system, relations of the vertical frequency, horizontal frequency and color subcarrier frequency are as follows.

V=2'60H fCS=( 284-1/4) . fH+25 where fV is the vertical frequency (50Hz), fH is the horizontal frequency (15.625kHz) and fSC is the color subcarrier frequency (4.43361875MHz).

According to WST (World System Teletext) which is a text broadcasting system adopted in Great Britain etc., the sampling clock fCK of a character signal is selected to be fCK=6.9375MHz. If fCK is regarded as a unit, 1H=444 and information of 360 bits in practice is multiplexed for 1H.

In this case, the sampling clock of a character signal is selected in the below described frequency relation.

fCK'8/5 x f5(7.O979MHz) Regarding fCK as a unit, 1H=454.00256, and accordingly information can be multiplexed in each vertical blanking period as shown in Fig. 7. Needless to say, since the total number of bits is larger than 444, information similar to that in WST can be directly multiplexed.

Since 1V=625H, lV=283751.6 10V=2837516 Consequently, as shown in Fig. 8, character signals can be multiplexed with 10V as a period.

Fig. 9 is a schematic block diagram showing a construction of a multiplexed text broadcasting system according to an embodiment of the present invention.

Referring to Fig. 9, video signals outputted from a camera 1 and a VTR 2 are switched by a switcher 3 and a sound signal outputted from the switcher 3 is supplied to an RF modulator 4, where it is modulated, so that the output is supplied to a mixer 5. On the other hand, the video signal outputted from the switcher 3 is supplied to a character signal multiplexing apparatus 6, where a character signal is multiplexed to the video signal, and the output therefrom is supplied to an RF modulator 7.

The RF modulator 7 modulates the video signal multiplexed with the character signal and supplies the output of the modulation to the mixer 5. The mixer 5 mixes a sound signal and the video signal multiplexed with the character signal and transmits the output in the air through an antenna 8.

Fig, 10 is a schematic block diagram of a character signal multiplexing apparatus with fCK = 14/llxfsc.

Referring to Fig. 10, a video signal is supplied to a bandpass filter (BPF) 11, a sync separation circuit 12 and a character signal multiplexing circuit 27. The bandpass filter Il is provided to separate a color signal component contained in the video signal and the color signal component thus separated is applied to a voltage quartz crystal oscillator circuit (VCXO 14). The sync separation circuit 12 separates a composite synchronizing signal from the video signal and supplies it to a burst gate pulse generating circuit 14 and a 4F signal generating circuit 16.

The burst gate pulse generating circuit 13 is provided to generate a pulse signal corresponding to a color burst portion, and the burst gate pulse signal is supplied to the VCXO 14. The VCXO 14 generates a signal fCS having the same frequency as the frequency of the color subcarrier signal, fsc=4.43361875MHz in response to the color signal component and the burst gate pulse signal, and supplies it to a PLL circuit 15. The PLL circuit 15 generates a signal 2fCk having a frequency of 2fCK synchronizing with the signal fSC and supplies it to an fCK automatic phase adjusting circuit 17.

The 4F generating circuit 16 discriminates between the first and second fields in response to a composite synchronizing signal and detects the first filed. In response to the detection, it generates a 4-field period signal 4F and supplies it to the fCK automatic phase adjusting circuit 17 and to a multiplexed position timing generating circuit 19 contained in an address generating circuit 18. The fCK automatic phase adjusting circuit 17 adjusts phases of the 4-field period signal 4F and the signal 2fCK and generates a signal fCK of a frequency fCK, thereby supplying it to the multiplexed position timing generating circuit 19.

The multiplexed position timing generating circuit 19 generates a timing signal indicating a leading position for multiplexing character signals of 7H of the first field, 320H of the second field, 7H of the third field1 320H of the third field, and 320H of the fourth field, in response to the 4-field period signal 4F and the signal and supplies it to a 361-base counter 20. The counter 20 is cleared by a timing signal indicating a multiplexed position and counts the signal fuck, whereby an address signal is supplied to a RAM 21.

A character data storing device 22 is provided to store character data to be transmitted and it is constructed for example by a personal computer or an external storing device. A RAM interface circuit 23 is provided to read the character data stored in the character data storing device 22 and to write it in the RAM 21. A RAM data reading circuit 24 reads the character data written in the RAM 21 and applies parallel/serial conversion thereto, so that a signal is outputted at a TLL level of logics 0, 1. This signal is supplied to an amplifier 25. The amplifier 25 is provided to convert output impedance of the signal to 75Q and the output of the amplifier 25 is supplied to a low-pass filter (LPF) 26, where the waveform is shaped as a sine wave.The character signal outputted from the low-pass filter 26 is supplied to the character signal multiplexing circuit 27, where the character signal is multiplexed to the video signal. The video signal with the multiplexed character signal is amplified by the amplifier 28 and the output of the amplification is provided as a character-multiplexed signal.

Fig. 11 is a schematic block diagram of a character signal multiplexing apparatus with fCK=15/llXfSC. The character signal multiplexing apparatus shown in Fig. 11 includes an 8F signal generating circuit 29 in place of the 4F signal generating circuit 16 shown in Fig. 10, and a 387-base counter 30 in place of the 361-base counter 20.

The other structure is the same as in Fig. 8. The 8F signal generating circuit 29 is provided to generate an 8-field period signal 8F in response to detection of the first field of the composite synchronizing signal.

The multiplexed position timing generating circuit 19 generates a timing signal for multiplexing character signals of 7H of the first field, 320H of the second filed, 7H of the third field, 320H of the fourth field, 7H of the fifth field, 320H of the sixth field, 7H of the seventh field, 320H of the eight field, and 7H of the ninth field, in response to the 8-field period signal 8F and the signal fCKt as shown in Fig. 4, and supplies the timing signal to the 387-base counter 30. The 387-base counter 30 is cleared by a timing signal indicating a multiplexed position of a character signal of each field outputted from the multiplexed position timing generating circuit 19 and counts the signal fCK, whereby an address signal is supplied to the RAM 21. The other operation is the-same as described above in connection with Fig. 8.

Fig. 12 is a schematic block diagram of a character signal multiplexing apparatus with fcK=16/llxfsc. This character signal multiplexing apparatus shown in Fig. 12 includes a 2F signal generating circuit 31 in place of the 4F signal generating circuit 16 shown in Fig. 10, and a 413-base counter 32 in place of the 361-base counter 20 of the address generating circuit 18. This apparatus generates a character-multiplexed signal in each field shown in Figs. 5 and 6. The 2F signal generating circuit 31 generates a 2-field period signal 2F in response to detection of the first field of the synchronizing signal and supplies it to the fCK automatic phase adjusting circuit 17 and the multiplexed position timing generating circuit 19.The multiplexed position timing generating circuit 19 generates a timing signal f or multiplexing character signals of 7H of the first field and 320H of the second field as shown in Fig. 6, in response to the 2-field period signal 2F. The 413-base counter 32 is cleared by the timing signal and it counts the signal fCK and supplies an address signal to the RAM 21. The other operation is the same as described previously in connection with Fig. 10.

Fig. 13 is a schematic block diagram of a character signal multiplexing apparatus with fcK=8/5xfsc. The character signal multiplexing apparatus shown in Fig. 13 includes a 10F signal generating circuit 36 in place of the 4F signal generating circuit 16 shown in Fig. 10, and a 454-base counter 37 in place of the 361-base counter 20 of the address generating circuit 18. This apparatus generates a character-multiplexed signal in each field shown in Figs. 7 and 8. The 1OF signal generating circuit 36 generates a 10-field period signal 10F in response to the first field of the synchronizing signal and supplies it to the fCK automatic phase adjusting circuit 17 and the multiplexed position timing generating circuit 19.The multiplexed position timing generating circuit 19 generates a timing signal for multiplexing character signals in 7H of the first field and 320H of the second field, as described above with reference to Fig. 8, in response to the 10-field period signal 10F. The 454-base counter 37 is cleared by the timing signal and it counts the signal fCK and supplies an address signal to the RAM 21. The other operation is the same as described previously in connection with Fig. 10.

Fig. 14 is a schematic block diagram showing another example of a character signal multiplexing apparatus with fcK=14/llxfsc. The apparatus shown in Fig. 14 includes a ROM 33 in place of the RAM 21, character data storing device 22 and RAM interface circuit 23 shown in Fig; 10, and includes a ROM data reading circuit 34 in place of the RAM data reading circuit 24. In addition, the fCK automatic phase adjusting circuit 17 is not provided and a PLL circuit 35 for generating the signal fCK is provided in place of the PLL circuit 15 for generating the signal 2fCK. The other construction is the same as shown in Fig.

10.

The PLL circuit 35 is provided to generate the signal fCK in response to the signal fSC generated from the VCXO 14 and to supply it to the multiplexed position timing generating circuit 19. More specifically, in the example shown in Fig. 14, adjustment for setting the 4-field period signal 4F to the phase of the signal fCK as shown in Fig. 10 is not carried out. Character data to be displayed is stored in the ROM 33 and when the address signal is supplied from the 361-base counter 20 to the ROM 33, corresponding character data is read out. The ROM data reading circuit 34 performs parallel/serial conversion of the character data read from the ROM 33 and provides the output of the conversion to the amplifier 25.

The other operation is the same as described previously with reference to Fig. 10.

Fig. 15 is a schematic block diagram showing another example of a character signal multiplexing apparatus with The The The apparatus shown in Fig. 15 has the below described structure in the same manner as in Fig. 14. A ROM 33 is provided in place of the RAM 21, character data storing device 22 and RAM interface circuit 23 shown in Fig. 13. A ROM data reading circuit 34 is provided in place of the RAM data reading circuit 24. The fCK automatic phase adjusting circuit 17 is not provided, and a PLL circuit 39 for generating the signal fCK is provided in place of the PLL circuit 38 for generating the signal 2fCK The other structure is the same as in Fig. 13.

The PLL circuit 39 is provided to generate the signal fCK in response to the signal fSC generated from the VCXO 14 and to supply it to the multiplexed position timing generating circuit 19. Thus, in the example shown in Fig.

15, adjustment for setting the 10-field period signal 10F to the phase of the signal fCK as shown in Fig. 13 is not carried out. Character data to be displayed is stored in the ROM 33 and when the address signal is supplied from the 454-base counter 37 to the ROM 33, corresponding character data is read out. The ROM data reading circuit 34 performs parallel/serial conversion of the character data read from ROM 33 and provides the output of the conversion to the amplifier 25. The other operation is the same as described previously with reference to Fig.

13.

Fig. 16 is a specified block diagram of a PLL circuit for generation of 2fCK included in the character signal multiplexing apparatus shown in Fig. 12. Referring to Fig. 16, an 11-frequency division circuit 151 receives the signal fSC The ll-frequency division circuit 151 frequency-divides 11 times the signal fSC of 4.361875MHz and provides an output signal a of 403.05625kHz to a phase comparator 153. The phase comparator 153 is provided to compare the output signal a of the ll-frequency division circuit 151 with the phase of an output signal b of a k-frequency division circuit 152.The k-frequency division circuit 152 frequency-divides k times an output of a voltage control oscillator (VCO) 155 and a frequency dividing ratio is defined as k=28 with fcK=14/llxfsc, k=30 with fcK=15/llxfSc, and k=32 with fcK=16/llxfSc.

The phase comparator 153 outputs a pulse signal corresponding to a phase difference between the output signal a of the ll-frequency division circuit 151 and the output signal b of the k-frequency division circuit 152 and supplies it to a low-pass filter (LPF) 154. The low-pass filter 154 supplies DC voltage to the VCO 155 in response to the pulse signal outputted from the phase comparator 153. The VCO 155 outputs the signal 2fCK in response to the inputted DC voltage.

2fcg=11.285575MHz with fcK=14/llxfSc; 2fcK=12.0916875MHz with fCk=15/llxfSc; and 2fCK=12.8978MHz with fcK=16/llxfsc.

Fig. 17 is a schematic block diagram showing the PLL circuit for fCK generation shown in Fig. 13. Referring to Fig. 17, th PLL circuit 35 comprises an 11-frequency division circuit 151, a k-frequency division circuit 152, a phase comparator 153, a low-pass filter 154, and a VCO 155, in the same manner as in the PLL circuit 15 for 2fCK generation shown in Fig. 16. The frequency dividing ratio of the k-frequency division circuit 152 is set to a half of that of the example shown in Fig. 16. More specifically, the frequency dividing ratio of the k-frequency division circuit 152 is selected to be k=14 with fCK=14/11xfSC and the frequency fCR of the signal fCK is 5.642785MHz.The frequency dividing ratio is selected to be k=15 with fCK=15/11xfSC and the frequency fCK of the signal fCK is 6.04584375MHz. k=16 is selected with fCK=16/11xfSC and the frequency fCK of the signal fCK is 6.4489MHz.

Fig. 19 is a schematic block diagram of the PLL circuit for fCK generation shown in Fig. 15. The PLL circuit 39 shown in Fig. 19 includes a 5-frequency division circuit 156 in place of the ll-frequency division circuit 151 of the PLL circuit 35 shown in Fig. 17, and an 8-frequency division circuit 158 in place of the k-frequency division circuit 152. The 5-frequency division circuit 156 frequency-divides the signal fCK five times, and the 8-frequency division circuit 158 frequency-divides the output of the VCO 115 eight times, in the same manner as in Fig. 18. The phase comparator 153 compares the output of the frequency division of the 5-frequency division circuit 156 and the output of the frequency division of the 8-frequency division circuit 158 and supplies the output of the comparison to the low-pass filter 154. The other operation is the same as in Fig.

17.

Fig. 20 is a diagram showing relations of a vertical synchronizing signal, a 4-field period signal 4F, an 8-field period signal 8F, a 2-field period signal 2F, and a 10-field period signal 10F. Referring to Fig. 20, the 2F signal generating circuit 31 described above with reference to Fig. 12 detects the vertical synchronizing signal of each field and outputs the 2-field period signal 2F by frequency-dividing twice the output of the detection. The 4F signal generating circuit 16 shown in Fig. 10 frequency-divides the 2-field period signal further twice and outputs the 4-field period signal 4F. The 8F signal generating circuit 29 shown in Fig. 11 frequency-divides the 4-field period signal 4F further twice and outputs the 8-field period signal 8F.The 10F signal generating circuit 36 shown in Fig. 13 frequency-divides five times the 2-field period signal and generates the 10-field period signal.

Fig. 21 is a specified block diagram of the fCK automatic phase adjusting circuit shown in Figs. 10 to 12.

It is necessary to provide a sufficient margin for a rise of the 4-field cycle signal 4F with respect to a rise of the signal CK However, since the 4-field period signal 4F is formed by a signal obtained by separation from the video signal by the sync separation circuit 12 shown in Fig. 10, the signal 4F is affected by the received field strength, the transmitted state of electric wave etc. and its state fluctuates. In addition, its rise sometimes occurs at almost the same timing as that of the rise of the signal CR Therefore, the fCK automatic phase adjusting circuit 27 is provided to carry out phase adjustment so that the rise of the 4-field period signal 4F can have a sufficient margin with respect to the rise of the signal fCK Referring to Fig. 21, the construction of the fCK automatic phase adjusting circuit 27 will be described.

The signal 2fCK is supplied from the PLL circuit 15 shown in Fig. 10 to an inverter 180 and a delay line 184. The inverter 180 inverts the signal 2fCK and supplies theoutput of the inversion to a 2-frequency division circuit 181 including a D-flip-flop. The 2-f requency division circuit 181 supplies a clock signal obtained by 2-frequency-division of the signal 2fuck to the delay line 182. The delay line 182 is provided to output the signal fCK of different phases by delaying the clock signal successively by a predetermined delay amount, and the respective delayed outputs are supplied to a data selector 183.

The data selector 183 selects any of the delayed outputs from the delay line 182 based on an output of a 2-bit counter 179 to be described afterwards. The ~delay line 184 is provided to output the signal 2fCK of different phases by delaying the signal 2fCK by a prescribed amount, and the respective delayed outputs are supplied to a data selector 185. The data selector 185 selects any of the delayed outputs from the delay line 184 based on an output of the 2-bit counter 179.

The 4-field period signal 4F is supplied from the 4F signal generating circuit 16 shown in Fig. 10 to monostable multivibrators 172, 173. In the example shown in Fig. 11, the 8-field period signal 8F is inputted, while in the example shown in Fig. 12, the 2-field period signal 2F is inputted. The inverter 171 inverts the 4-field period signal 4F and supplies the output of the inversion to a D input terminal of the D-flip-flop 174.

The D-flip-flop 174 is provided to compare the 4-field period signal 4F and the signal f CR The delayed signal fCK is inputted from the above mentioned data selector 183 to a clock input terminal of the D-flip-flop 174. An output Q of the D-flip-flop 174 and an output of the inverter 171 are supplied to an AND gate 175.

The AND gate 175 outputs a pulse signal corresponding to a period from a fall of the 4-field period signal 4F to logical low ("L") level to a rise of the signal fCK to logical high ("H") level, namely, a phase difference between the 4-field period signal 4F and the signal fCKt and supplies the pulse signal to an enable terminal of a l-bit counter 176. The counter 176 is provided to detect a magnitude of the above mentioned phase difference in response to an output signal c of the AND gate 175. For this purpose, the delayed signal 2fCK is supplied from the above mentioned data selector 185 to the clock input terminal of the counter 176. A clear pulse is supplied from the monostable multivibrator 172 to a clear input terminal of the counter 176.The monostable multivibrator 172 is provided to generate a clear pulse after a prescribed time from the fall of the 4-field period signal 4F to "L" level.

The output of the counter 176 is inverted by an inverter 177 and the output of the inversion is supplied to one input terminal of the AND gate 178. The other input terminal of the AND gate 178 receives a count pulse from the monostable multivibrator 173. The monostable multivibrator 173 is provided to output a count pulse before the output of the clear pulse after the fall of the 4-field period signal 4F to "L" level. The output of the AND gate 178 is supplied to a clock input terminal of a 2-bit counter 179. The 2-bit counter 179 outputs a signal for selecting the delayed outputs of the delay lines 182, 184 so that the phase difference of the respective field period signals and the signal fCK may be within a prescribed range.For this purpose, an output QA and an output QB of the 2-bit counter 179 are supplied to the data selectors 183 and 185, respectively.

Fig. 22 is a waveform diagram for explaining operation of the fCK automatic phase adjusting circuit shown in Fig. 21.

Referring to Fig. 22, the operation of the fCK automatic phase adjusting circuit shown in Fig. 21 will be described. As shown in (A) of Fig. 22, when the 4-field period signal 4F falls to "L" level, the output of the inverter 171 rises to "H" level and the D-flip-flop 174 sets the output Q to "L" level at the rise of an fCK signal b. The AND gate 175 supplies, as an enable signal, a signal c having "H" level only in a period from the fall of the 4-field period signal 4F to "L" level to the rise of the clock signal b, to the counter 176.

The counter 176 has the QA output d set to "H" level with timing of rise of the enable signal to "H" level and rise of the 2fCK signal a. The output d of the counter 176 is inverted by the inverter 177 and the output falls to "L" level. As a result, the AND gate 178 is closed and the count pulse outputted from the monostable multivibrator 173 is not supplied to the 2-bit counter 179. Consequently, the respective outputs QAT QB of the 2-bit counter 179 fall to "L" level and thus the data selectors 183, 185 select the signals having the least delay amount from the delay lines 182, 184.

When the output signal c of the AND gate 175 and the fCK signal b are in a relation as shown in (E) of Fig. 22, the 2fCK signal a rises only once in a period of "H" level of the signal c and accordingly, the counter 176 counts the 2FCK signal only once. In this case also, the pulse signal e rising to "H" level is not supplied from the AND gate 178 to the 2-bit counter 179.

As shown in (F) of Fig. 22, if the 2fCK signal rises twice in the period of the gate signal c outputted from the AND gate 175, the counter 176 counts the 2fCK signal twice and as a result the AND gate 178 is opened, so that the pulse signal e is supplied to the 2-bit counter 179.

The output QA of the 2-bit counter 179 rises to "H" level and the data selectors 183, 185 output the subsequent delayed fCK signal and 2fCK signal of the delay lines 182, 184. Further, when timing as shown in (G) of Fig. 22 is set, the 2fCK signal a never rises in the period of the gate pulse c and the counter 176 does not count the 2fCK signal. In this case also, the AND gate 178 is opened and the pulse signal e is supplied to the 2-bit counter 179.

In response to the output of the 2-bit counter 179, the data selectors 183, 185 selects the delayed outputs of the delay lines 182, 184, respectively.

As described above, the counter 176 operates in response to the gate signal c outputted from the AND gate 175 and the 2fCK signal a. When the count value of the counter 176 is other than "1", the AND gate 178 generates the pulse signal e and the 2-bit counter 179 counts the pulse signal e. In response to the count output of the counter 179, the data selectors 183, 185 output the 2fCK signal a and fCK signal b having the optimal phases from the delay lines 182, 184, whereby the phases of the 4-field period signal 4F and the fCK C K signal can be adjusted as shown in (H) to (J) of Fig. 22.

Fig. 23 is a specified block diagram of the address generating circuit shown in Figs. 10 and 11. Referring to Fig. 23, the address generating circuit 18 comprises a multiplexed position timing generating circuit 19 and a k-base counter 20. In the case of fcK=14/llxfSc, a 361-base counter is used as the k-base counter 20. A clear pulse generating circuit 191 is provided to output a clear pulse d after a prescribed time from a fall of the 4-field period signal 4F to "L" level. The clear pulse d clears the content of the counter 192. The fCK signal b is supplied as a clock signal to the counter 192. The counter 192 is provided to count the clock signal in a period of four fields, and the count output is supplied to a decoder circuit 193.

The decoder circuit 193 outputs a signal indicating a position where a character signal is to be multiplexed in each field. More specifically, the decoder circuit 193 outputs a pulse signal e as a clear signal for each of 7H of the first field, 320H of the second field, 7H of the third field, etc. and supplies the signal to the k-base counter 20. The 4-field period signal a and the fCK signal b are inputted to an EXOR gate 194. The EXOR gate 194 outputs a 2-phase signal c having its phase inverted for two fields and the 2-phase clock signal c is supplied to the k-base counter 20. The k-base counter 20 is cleared by the pulse signal e outputted from the decoder circuit 193 and it counts the 2-phase clock signal c and outputs an address signal.

Figs. 25 to 27 are waveform diagrams for explaining operation of the address generating circuit shown in Fig.

23.

The clear pulse generating circuit 19i generates a clear pulse d shown in Fig. 25 (C) at 7H of the first field for example from the fall of the 4-field period signal 4F shown in Fig. 25 (B) to "L" level, so that the content of the counter 192 is cleared. After that, the counter 192 counts the fCK signal b shown in Fig. 26 (D).

The count output of the counter 192 is decoded by the decoder circuit 193. The decoder circuit 193 supplies a clear signal e to the k-base counter 20 when the count value of the counter 192 is any of 0, 113036, 225712, and 338749.

On the other hand, the EXOR gate 194 has an exclusive logical sum of the 4-field period signal a and the signal b and as shown in Fig. 26 (E), it outputs a 2-phase clock signal c having its phase inverted for two fields to the k-base counter 20. The k-base counter 20 counts the 2-phase clock signal c and outputs an address signal indicating multiplexing timing of 7H to 22H in respective fields. When the 4-field period signal 4F is at "L" level, the 2-phase clock signal c has its phase matching with the phase of the signal fCK- When the 4-field period signal 4F is at "H level, the 2-phase clock signal c is a pulse having the polarity inverted from that of the signal fCK.Accordingly, the k-base counter 20 is cleared in synchronization with the 2-phase clock signal c in the "H" level period of the clear signal, and the output of the decoder circuit 193 has a form as if newly sampled. Thus, as shown in Fig. 26 (G), "1" for the first field, "113037" for the second field, "225712.5" for the third field and "338749.5" for the fourth field can be obtained. Those timings are used to multiplex the character signal for each field.

In the case of f =15/11xfSC' the k-base counter 20 is formed by a 387-base counter. The decoder circuit 193 outputs a timing signal e as shown in Fig. 27 (F). This signal e has a form newly sampled by the k-base counter 20 and a timing signal as shown in Fig. 27-(G) is outputted in the first to eight fields.

Fig. 24 is a schematic block diagram of the address generating circuit with f =16/11xfSC' The address generating circuit shown in Fig. 24 does not have the EXOR gate 194 shown in Fig. 23 and a 413-base counter 32 is provided in place of the k-base counter 20. The 413-base counter 32 receives the fCK signal as a clock signal.

Fig. 28 is a waveform diagram for explaining operation of the address generating circuit shown in Fig.

24.

In the case of fcK-16/llxfsc, as shown in Fig. 6, 7H of the first field corresponds to the first bit and 320H of the second field corresponds to the 129185th bit. As is different from the above described cases of fcK=I4/llxfsc and fcK=15/llxfSc, the 2-phase clock signal is not used. The decoder circuit 193 decodes the count output of the counter 192 and supplies the clear signal e to the 413-base counter 32 in the 0th bit and the 129184th bit, so that the counter 32 is cleared. After that, the 413-base counter 32 counts the fCK signal b and outputs an address signal for multiplexing character signals with timing as shown in Fig. 5 in 7H to 22H of the first field and 320H to 335H of the second field.

Fig. 29 is a waveform diagram for explaining operation of the address generating circuit shown in Fig.

24 with fCK=8/5xfSC In the case of 8/5xfSc, as shown in Fig. 8, 7H of the first field corresponds to the first bit and 320H of the second field corresponds to the 142103rd bit. In the same manner as described previously in connection with Fig. 28, the 2-phase clock signal is not used. The decoder circuit 193 decodes the count output of the counter 192 and supplies a clear signal e to the 454-base counter 32 in the 0th bit, the 142102nd bit, the 283751st bit, ... the 1277109th bit, so that the counter 32 is cleared. After that, the 454-base counter 32 counts the fCK signal b and outputs an address signal for multiplexing character signals with timing as shown in Fig. 7, in 7H to 22H of the first field, and 320H to 335H of the second field.

Fig. 30 is a schematic block diagram of a text broadcasting signal receiving apparatus according to an embodiment of the present invention. Referring to Fig.

30, broadcasting wave is received by a tuner 51 through an antenna 50 and the tuner 51 outputs a sound intermediate frequency signal and a video intermediate frequency signal. The sound intermediate frequency signal is supplied to a sound intermediate frequency amplifier 52, where it is subjected to intermediate frequency amplification. The video intermediate frequency signal is supplied to a video intermediate frequency amplifier 56, where it is subjected to intermediate frequency amplification. The output of the sound intermediate frequency amplifier 52 is supplied to a sound detecting circuit 53, where a sound signal is detected. The sound signal is amplified by an amplifier 54 and the output of the'amplification is supplied to a speaker 55.

The output signal of the video intermediate frequency amplifier 56 is supplied to a video detecting circuit 57, from which a video signal is outputted. The video signal is supplied to a video processing circuit 58 and a character signal processing circuit 59. The video processing circuit 58 processes the video signal and supplies the output to an RGB switching circuit 60. The character signal processing circuit 59 demodulates a character signal and supplies the output to the RGB switching circuit 60. The RGB switching circuit 60 selects RGB in response to the video signal or the character signal, so that the output is displayed on a CRT 61.

Fig. 31 is a schematic block diagram of the character signal processing circuit 59. Referring to Fig. 31, the video signal outputted from the video detecting circuit 57 shown in Fig. 30 is supplied to a bandpass filter 62, a sync separation circuit 64 and a comparator 69. The bandpass filter 62 is provided to separate a color signal component contained in the video signal, and the color signal component thus obtained is supplied to a VCXO 63.

The sync separation circuit 64 separates a composite synchronizing signal from the video signal and supplies the same to a burst gate pulse generating circuit 65 and a kf signal generating circuit 67.

The burst gate pulse generating circuit 65 generates a pulse signal corresponding to a color burst portion and supplies the burst gate signal to the VCXO 63. The VCXO 63 generates a signal fSC having a frequency of 4.53361875MHz identical to that of a color subcarrier signal, in response to the color signal component and the burst gate signal. A PLL circuit 66 generates a signal fCK as a sampling clock signal, in response to the fSC signal and supplies the-same to a framing code detection protecting circuit 68.

The kf signal generating circuit 67 is provided to generate a field signal from the composite synchronizing signal according to a bit rate. The kf signal generating circuit 67 generates a 4-field period signal 4F with fcK=14/llxfsc, an 8-field period signal 8F with fCK=16/11xfsc, and a 10-field period signal 10F with fcK=8/5xfsc. In the following, the case of generating the 4-field period signal 4F will be described. The 4-field period signal 4F generated from the kf signal generating circuit 67 is supplied to the framing code detection protecting circuit 68.

The comparator 69 extracts a character signal component contained in the video signal and the character signal thus extracted is supplied to the framing code detection protecting circuit 68 and an error correction circuit 70. The framing code detection protecting circuit 68 corrects errors based on an error correction function of an inputted framing code itself and also corrects errors by flywheel effect. The correction by the flywheel effect will be described afterwards with reference to Fig.

29. The framing code detected by the framing code detection protecting circuit 68 and the character signal outputted from the comparator 69 are supplied to the error correction circuit 70.

The error correction circuit 70 corrects errors based on the framing code and the character data and supplies the character data to a central processing unit (CPU) 71.

The CPU 71 analyzes the inputted character data and writes character data in a video memory 73 through a display control circuit 72. The display control circuit 72 reads a character font from the video memory 7 in synchronization with a synchronizing signal and supplies it to an RGB output circuit 74. The RGB output circuit 74 converts the read character font to an RGB signal and outputs the same.

Fig. 32 is a block diagram showing the kf signal generating circuit shown in Fig. 31 and a protection circuit thereof. Referring to Fig. 32, the composite synchronizing signal of the negative polarity outputted from the sync separation circuit 64 shown in Fig. 31 is supplied to inverters 81, 86, where the polarity is inverted. An output of the inverter 81 is connected with an integrating circuit 82, where the composite synchronizing signal is integrated and a horizontal synchronizing signal is removed, so that only a vertical synchronizing signal is extracted. The vertical synchronizing signal is shaped by a buffer 83 and the signal thus shaped is supplied to a D input terminal of a D-flip-flop 84.

The composite synchronizing signal having the polarity inverted by the inverter 86 is supplied to a clock input terminal of the D-flip-flop 84 and to a monostable multivibrator 87. The D-flip-flop 84 is provided to synchronize the output of the integrating circuit 82 with the composite synchronizing signal and the output therefrom is supplied to a monostable multivibrator 85 and a CPU 90. The monostable multivibrator 85 generates a pulse signal at a leading edge of the vertical synchronizing signal and supplies it to a clock input terminal of a D-flip-flop 89.

The monostable multivibrator 87 is provided to generate a 3/4H pulse raised to "H" level only in a 3/4H period in response to the composite synchronizing signal, and the generated 3/4H pulse is supplied to a monostable multivibrator 88. The monostable-multivibrator 88 generates a pulse signal e at a leading edge of the 3/4H pulse and supplies it to a D input terminal of the D-flip-flop 89. The D-flip-flop 89 outputs the 2-field period signal 2F in response to the output signal c of the monostable multivibrator 85 and the output signal e of the monostable multivibrator 88. The 2-field period signal 2F is supplied to a D-flip-flop 92 serving as a 2-frequency division circuit through an inverter 91 and it is also supplied to a D-flip-flop 94 through an inverter 93. The D-flip-flop 94 together with the D-flip-flop 95 constitutes a 4-frequency division circuit. The D-flip-flop 92 frequency-divides twice the 2-field period signal 2F and outputs a 4-field period signal 4F.

The 2-field period signal 2F outputted from the above mentioned D-flip-flop 89 is also supplied to a D-flip-flop 202 through an inverter 201. The D-flip-flop 202 as well as D-flip-flops 203, 204 frequency-divides the 2-field period signal five times and outputs a 10-field period signal 10F. More specifically, the Q outputs of the D-flip-flops 202 and 204 are supplied to a NAND gate 205, and when the Q outputs of the D-flip-flops 202 and 204 attain "H" level, the NAND gate 205 supplies a signal of "L" level to the D-flip-flops 202, 203 and 204 through NOR gates 206, 207, 208, so that those flip-flops are cleared.

In the case of fcK=15/llxfsc,- the D-flip-flops 94, 95 frequency-divide the 2-field period signal 2F four times and output an 8-field period signal 8F. The 4-field period signal 4F and the 8-field period signal 8F as well as the 10-field period signal 10F are supplied to the CPU 90.

The CPU 90 is provided to monitor synchronization between the vertical synchronizing signal and the 4-field period signal 4F, the 8-field period signal 8F or the 10-field period signal 10F. More specifically, if an S/N ratio of the inputted video signal is deteriorated, erroneous operation of the kf signal generating circuit 67 might occur. If a failure in the synchronization between the 4-field period signal 4F, the 8-field period signal 8F, or the 10-field period signal 10F and the vertical synchronizing signal due to the erroneous operation is detected, the CPU 90 supplies a preset pulse or a clear pulse to the D-flip-flops 92, 94, 95 so as to protect them from the erroneous operation.

Figs. 33 to 35 are waveform diagrams for explaining operation of the kf signal generating circuit shown in Fig. 32.

Referring to Figs. 32 to 35, the operation of the kf signal generating circuit 67 will be described. The composite synchronizing signal of the negative polarity shown in Fig. 33 (A) is inverted by the inverter 81 and a horizontal synchronizing signal is removed therefrom by the integrating circuit 82, whereby only a vertical synchronizing signal component is supplied to the buffer 83. The buffer 83 shapes the vertical synchronizing signal and outputs a rectangular wave signal a as shown in Fig. 33 (B). The rectangular wave signal a is synchronized with the composite synchronizing signal by the D-flip-flop 84 and a vertical synchronizing signal b as shown in Fig. 33 (C) is obtained. The monostable multivibrattr 85 generates a pulse signal c falling to "L" level at a leading edge of the vertical synchronizing signal b as shown in Fig. 33 (D).

The monostable multivibrator 87 generates a pulse signal d of a 3/4H duration in response to the composite synchronizing signal as shown in Fig. 33 (E). The monostable multivibrator 88 generates a pulse signal e as shown in Fig. 33 (F) at a leading edge of the pulse signal of the 3/4H duration. The D-flip-flop 89 latches the output signal e of the monostable multivibrator 88 with timing of rise of the pulse signal c outputted from the monostable multivibrator 85 and outputs an "L" level signal f from the Q output as shown in Fig. 33 (G).

The D-flip-flop 89 provides an "H" level signal f from the Q output as shown in Fig. 34 (F), when the pulse signal e outputted from the monostable multivibrator 88 is at "H" level with timing of rise of the pulse signal c outputted from the monostable multivibrator 85 in the second field shown in Fig. 34. As a result, the 2-field period signal 2F as shown in Fig. 35 (B) is outputted from the Q output D-flip-flop 89.

On the other hand, the D-flip-flop 92 frequency-divides the above mentioned 2-field period signal 2F twice and outputs a 4-field period signal 4F as shown in Fig. 35 (C). The D-flip-flops 94, 95 frequency-divide four times the 2-field period signal 2F, so that an 8-field period signal 8F as shown in Fig. 35 (D) is outputted. The D-flip-flops 202, 203, 204 frequency-divide five times the 2-fieldperiod signal 2F and output a 10-field period signal 10F as shown in Fig.

35(E). Fig. 35 (A) shows the output signal c of the monostable multivibrator 85 shown in Fig. 33 and Fig. 34 (D). The CPU 90 monitors timing of the 4-field period signal 4F, the 8-field period signal 8F or the 10-field period signal 10F and the vertical synchronizing signal.

and if a deviation occurs in the timing of the 4-field period signal 4F, the 8-field period signal 8F or the 10-field period signal 10F with respect to the vertical synchronizing signal, a reset pulse or a clear pulse is outputted to the D-flip-flops 92, 94, 95, or 202, 203, 204, so that synchronization is attained.

Fig. 36 is a specified block diagram of the framing code detection protecting circuit 68. Referring to Fig.

36, a construction of a main part of the framing code detection protecting circuit 68 will be described. The EXOR gate 109 takes an exclusive logical sum of the 4-field period signal 4F and the fCK signal and generates a 2-phase clock signal. A shift register 101 is provided to convert serial character data to a parallel signal in synchronization with the 2-phase clock signal. A framing code decoder circuit 102 receives the parallel character data from the shift register 101 and detects a framing code. The framing code decoder circuit 102 includes a framing code error correction circuit.

A gate pulse generating circuit 110 outputs a signal a which is at "H" level only in a period of the first H where character signals of th first field are multiplexed, and a signal b which is at "H" level only in a period where character signals are multiplexed in respective fields, in response to the 4-field period signal 4F and the composite synchronizing signal. A k-base counter 105 is set to k=451, 423 with fcK=14/llxfsc, k=967, 335 with fcK=15/llxfsc, and k=257, 957 with fCK=16/11xfSC.

A decoder circuit 106 decodes the count output of the k-base counter 105 and outputs a timing signal e representing the first framing code in each field, and a timing signal f for predicting a position of a framing code coming four fields after the framing code of the first field. An 2-base counter 108 counts the 2-phase clock signal and prepares therein a timing signal g for predicting a position of a framing code in 7H to 22H, 320H to 335H in each field. The 4-base counter 108 is set to =361 with fcK=14/llxfSc,2=387 with fcK=15/llxfsc, SC CK 2=413 with fCK=16/11xfSC, and g=454 with fCK=8/5xfSC. An m-base counter 117 and an n-base counter 118 are provided to protect leading and trailing portions of the framing code. The m-base counter 117 detects that periodicity of the framing code is definitely set, and the n-base counter 118 detects irregularity in the periodicity of the framing code.

Figs. 37 to 40 are waveform diagrams for explaining operation of the framing code detection protecting circuit with fCK=14/11xfSC.

Referring to Figs. 36 to 40, the operation of the framing code detection protecting circuit will be described. The EXOR gate 109 obtains an exclusive logical sum of the fCK signal and the 4-field period signal 4F and outputs a 2-phase clock signal. The shift register 101 converts serial character data to parallel character data in response to the 2-phase clock signal and supplies the parallel character data to the framing code decoder circuit 102. The framing code decoder circuit 102 detects a framing code corresponding to each H of respective fields and supplies a detection signal c as shown in Fig.

38 (D) to one input terminal of each of AND gates 103 and 111.

The gate pulse generating circuit 110 generates a signal a set to "H" level only in the first horizontal period where a character signal of the first field is multiplexed as shown in Fig. 38 (C), and a signal b set to "H" level only in a period where a character signal is multiplexed as shown in Fig. 38 (B), in response to the composite synchronizing signal and the 4-field period signal 4F. The signal a is supplied to the AND gates 103 and 111. Assuming that a signal t as an output Q of an RS flip-flop 119 is at "H" level, an output signal d of the AND gate 103 is as shown in Fig. 38 (E) and the framing code detection signal d is outputted only in the first horizontal period where the character signal of the first field is multiplexed. The k-base counter 105 through an OR gate 104. After the k-base counter 105 is cleared, it counts the fCK signal.

The k-base counter 105 counts the fCK signal up to the numbers 451, 423 and supplies the count output to the decoder circuit 106. The decoder circuit 106 decodes the count output of the k-base counter 105 and decodes the count values 113036, 225712, 338749, 451423 and outputs a decode signal e as shown in Fig. 39 (D). The decode signal e represents the first character-multiplexed position in each field. The decode signal e is supplied as a clear signal to the j-base counter 108 through the OR gate 107. The -base counter 108 is cleared by the decode signal e and counts the 2-phase clock signal up to the number 361.The count output g of the 4-base counter 108 serves as a clear signal of the counter 108 itself and it serves also as a framing code detection signal in each horizontal scanning period of respective fields as shown in Fig. 40 (G).

Fig. 41 is a waveform diagram for explaining leading and trailing protection operation for a framing code.

Referring to Figs. 36 to 41, the leading and trailing protection operation for the framing code will be described. Fig. 41 (A) shows timings of relative periods for four fields, indicated with (1) to (21). The following description is made on the assumption that m=3 is set in the m-base counter 117 and n=4 is set in the n-base counter 118. When the power supply is turned on or when character data is received for the first time, periodicity of a framing code is not fixed and, as shown in Fig. 41 (J), the signal t as the output Q of the RS flip-flop 119 is at "H" level. At that time, the framing code decoder circuit 102 can not detect a framing code and the output signal h of the AND gate 111 is at "L" level as shown in Fig. 41 (B).Since the signal h is inverted by the inverter 111 and the output of the inversion is supplied to the AND gate 112, the output signal i of the AND gate 112 attains "H" level as shown in Fig. 41 (C) and the m=base counter 117 is cleared.

When a framing code is detected by the framing code decoder circuit 102 at the timing (2), the output signal h of the AND gate 111 attains "H" level and, as a result, the signal i falls to 2L* level. Thus, the output signal j of the AND gate 113 attains "H" level as shown in Fig.

41 (D) and the m-base counter 117 counts the signal j, whereby the count value becomes "1" as shown in Fig. 41 (K). At the timing (3), the same operation as that at the timing (2) is performed and the count value of the m-base counter 117 becomes "2".

Since a framing code is not detected at the timing (4); the signal i attains "H" level and the m-base counter 117 is cleared. When the framing code is detected at the timing (5), the m-base counter 117 is incremented to the count value "1". When a framing code is detected at the timing (6), the m-base counter 117 is incremented to the count value "2". Similarly, when a framing code is detected at the timing (7), the m-base counter 117 is incremented to the count value "3" and a carry q is outputted from the m-base counter 117 as shown in Fig. 41 (G), whereby the RS flip-flop 119 is set. As a result, the output signal s of the RS flip-flop 119 attains "H" level as shown in Fig. 41 (I) and the signal t attains "L" level as shown in Fig. 41 (J).At the timings (8) and (9), upon detection of a framing code, the butput signal o of the AND gate 114 attains "H" level as shown in Fig. 41 (E) and the n-base counter 118 is cleared. At the timings (10), (11) and (12), no framing code is detected and accordingly the output signal p of the AND gate 115 attains "H" level as shown in Fig. 41 (F) and the n-base counter 118 is incremented to the count values "1", "2", "3", as shown in Fig. 41 (L).

At the timings (13) and (14), upon detection of a framing code, the signal o attains "H" level and the n-base counter 118 is cleared. At the timings (15), (16) and (17), no framing code is detected and accordingly the signal p attains "H" level and the n-base counter 118-is incremented to the count values "1", "2", "3". At the timing (18), no framing code is detected and the signal p attains "H" level. The n-base counter 118 is incremented to the count value "4" and a carry r is outputted from the n-base counter 118 as shown in Fig. 41 (H), whereby the RS flip-flop 119 is reset.

As a result, the signal s falls to "L" level and the signal t rises to "H" level. When no framing code is detected at the timing (19), the signal i attains "H" level and the n-base counter 117 is cleared. When a framing code is detected at the timings (20), (21), the signal i attains "H" level and the m-base counter 117 is incremented.

The k-base counter 118 operates based on the decode signal e from the decoder circuit 106. The signal e indicates a detection position of the first framing code of each field and a detection signal of the framing code of each H is generated based on the signal e. When the signal s of the RS flip-flop 119 is at "H" level, the k-base counter 105 automatically operates and the framing code detection signal from the Q-base counter 118 is regarded as the final framing code detection signal.

When the signal s is at "L" level, the framing code detection signal detected by the framing code decoder circuit 102 is regarded as the final framing code detection signal.

The above described example is related with n=3 and m=4. In general, if the value of n is small, periodicity of a framing code is liable to be unstable due to influence of noise. If the value of n is increased, the framing code periodicity is less liable to be unstable and reliability of leading and trailing protection for a framing code is enhanced. In such a case, however, there are demerits as described below. If the k-base counter 105, the j-base counter 108 or the like operates erroneously due to noise or other effect, the framing-code detection signal reproduced from the 2-base counter 108 should have an error at that time and it would be necessary to search for the periodicity of the framing code detection signal at that time.However, since the count value of the n-base counter 118 is a large value, a delay occurs in determination that the periodicity of the framing code detection signal becomes unstable.

Fig. 42 is a waveform diagram of the framing code detection protecting circuit shown in Fig. 36 in the case of fcK=15/llxfsc, and Fig. 43 is an enlarged view of a part of the waveform in Fig. 42.

In the case of fcK=15/llxfsc, a framing code is detected for 967335 bits as shown in Fig. 42 (C) from the AND gate 103 shown in Fig. 36. A detection signal e of the first framing code in each field is outputted from the decoder circuit 106 for 0, 121110, 241833 ..., bits as shown in Fig. 42 (D) and a pulse f predicting a detection position of a framing code coming eight fields after the present one is outputted as shown in Fig. 42 (E). The case counter is formed by a 387-base counter and as shown in Fig. 43 (B), a framing code detection signal of each H is generated for 387 bits.

Fig. 44 is a waveform diagram of the framing code detection protecting circuit in the case of fcK=16/llxfSc, and Fig. 45 is a waveform diagram showing a part thereof in an enlarged manner.

In the case of f =16/11xfSC, a framing code is detected for two fields from the AND gate 103 as shown in Fig. 44 (C). A detection signal e of the first framing code of each field is outputted from the decoder circuit 106 and a pulse f for predicting a framing code coming two fields later is outputted. The 2-base counter 108 is formed by a 413-base counter and a timing signal g for generating a framing code detection signal of each H of respective fields is outputted as shown in Fig. 45 (B).

In the case of fcK=8/5xfSc, a framing code is detected for ten fields from the AND gate 103 and a detection signal of the first framing code of each field is outputted from the decoder circuit 106. A pulse predicting a framing code coming ten fields later is outputted. The -base counter 108 is formed by a 454-base counter and a timing signal for generating a framing code detection signal of all the respective fields is outputted.

As described above, according to the text broadcasting signal generating apparatus of the embodiment of the present invention, a timing signal for indicating the first position of a framing code in a prescribed horizontal scanning period of each field is generated and, in response to the timing signal, a framing code and character data are inserted in the prescribed horizontal scanning period of each field. Consequently, the framing code and the character data exert no adverse effect on color burst or the horizontal synchronizing signal. In addition, since periodicity can be set in a framing code with several fields as a cycle, the error correction effect by the framing code can be enhanced. In addition, according to the text broadcasting signal receiving apparatus of the present invention, a framing code detection signal is generated in a prescribed horizontal scanning period of each field in response to the framing code of the first field among detected several fields.

Consequently, a character signal having a phase deviated in the prescribed horizontal scanning period of each field can be demodulated in good condition. Further, the error correction effect can be enhanced using the framing codes having periodicity.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A text broadcasting system generating apparatus of a text broadcasting system where a framing code and character data are multiplexed and transmitted by using a composite video signal including a horizontal synchronizing signal, a vertical synchronizing signal, a video signal and a color subcarrier signal, in a predetermined horizontal scanning period in a vertical blanking period of a television broadcasting signal with a frequency of said colorsubcarrier signal being not set in a relation of a fraction consisting of an integer denominator and an integer numerator with respect to a horizontal frequency of said horizontal synchronizing signal, comprising:: clock signal generating means for generating a clock signal having periodicity to set an identical phase with identical timing in a horizontal scanning period corresponding to a predetermined number of fields, said clock signal synchronizing with said color subcarrier signal and having a bit rate in a relation of a fraction consisting of a denominator of a relatively simple first integer and a numerator of a second integer different from said first integer with respect to the frequency of said color subcarrier signal, periodicity signal generating means responsive to said synchronizing signal for generating a periodicity signal having a period of said predetermined number of fields, leading timing signal generating means responsive to the clock signal generated from said clock signal generating means and the periodicity signal generated from said periodicity signal generating means, for generating a timing signal representing a timing of a leading edge of a framing code in said predetermined horizontal scanning period in each field, and output means responsive to the timing signal generated from said leading timing signal generating means, for multiplexing the framing code and the character data to set the leading edge according to said timing and providing the output of the multiplexing in said predetermined horizontal scanning period of each field.

2. A text broadcasting signal generating apparatus in accordance with claim 1, further comprising means for synchronizing the periodicity signal generated from said periodicity generating means with the clock signal generated from said clock signal generating means.

3. A text broadcasting signal generating apparatus in accordance with claim 1, wherein said clock signal generating means comprises second clock signal generating means for generating a second clock signal having a frequency twice that of said clock signal, frequency dividing means for frequency-dividing twice said second clock signal generated from said second clock signal generating means and generating said clock signal, first delay means for delaying said clock signal generated from said frequency dividing means by an amount equal to or less than one period of said clock signal, second delay means for delaying said second clock signal generated from said second clock signal generating means by the same period as that of said first delay means, comparing means for comparing phases of said periodicity signal and said clock signal delayed by said first delay means, detecting means for detecting a magnitude of a phase difference detected by said comparing means based on said second clock signal delayed by said second delay means, and means responsive to an output of said detecting means for changing delay amounts of said first and second delay means to cause the phase of said periodicity signal to be within a prescribed range with respect to the phase of said clock signal.

4. A text broadcasting signal receiving apparatus for a text broadcasting system where a framing code and character data are multiplexed and transmitted by using a composite video signal including a horizontal synchronizing signal, a vertical synchronizing signal, a video signal and a color subcarrier signal, in a predetermined horizontal scanning period in a vertical blanking period of a television broadcasting signal with a frequency of said color subcarrier signal being not selected to be in a relation of a fraction consisting of an integer denominator and an integer numerator with respect to a horizontal frequency of said horizontal synchronizing signal, said framing code and said character data synchronizing with said color subcarrier signal and having a bit rate of a relation of a fraction consisting of a denominator of a relatively simple first integer and a numerator of a second integer different from said first integer with respect to the frequency of said color subcarrier signal, said bit rate having periodicity to set an identical phase at identical timing in a horizontal scanning period corresponding to a predetermined number of fields, and said framing code and said character data being multiplexed in said composite video signal to change a timing of a leading edge of a framing code regularly in said predetermined horizontal scanning period of each field using said predetermined number of fields as a period, said text broadcasting signal receiving apparatus comprising:: receiving means for receiving a television broadcasting signal where said framing code and said character data are multiplexed, synchronizing signal separating means for separating a synchronizing signal from the television broadcasting signal received by said receiving means, clock signal generating means for generating a clock signal synchronizing with said color subcarrier signal, having a bit rate in a relation of a fraction consisting of a denominator of a relatively simple first integer and a numerator of a second integer different from said first integer with respect to said color subcarrier signal, and having periodicity to set an identical phase with identical timing in a horizontal scanning period corresponding to a predetermined number of fields, periodicity signal generating means responsive to the synchronizing signal separated by said synchronizing signal separating means, for generating a periodicity signal having a period of said predetermined number of fields, framing code detecting means for detecting a framing code from said received composite-video signal, framing code detection signal forming means responsive to a first framing code detection signal of the first field among the predetermined number of fields detected by said framing code detecting means and to said periodicity signal, for forming a framing code detection signal with timing in said predetermined horizontal scanning period of each field, and demodulating means responsive to the framing code detection signal formed by said framing code detection signal forming means and the clock signal generated by said clock signal generating means, for demodulating the character data in said text broadcasting signal.

5. A text broadcasting signal receiving apparatus in accordance with claim 4, wherein said periodicity signal generating means comprises field detecting means for detecting a first field and a second field in response to said synchronizing signal, and counting means for counting a detection signal of the first filed detected by said field detecting means and outputting the periodicity signal having the period of said predetermined number of fields.

6. A text broadcasting signal receiving apparatus in accordance with claim 4, further comprising vertical synchronizing signal separating means for separating a vertical synchronizing signal from said synchronizing signal, detecting means for detecting synchronization/non-synchronization between said periodicity signal outputted from said counting means and said vertical synchronizing signal separated by said vertical synchronizing signal separating means, and correction means responsive to detection of a deviation in synchronization of said periodicity signal with respect to said vertical synchronizing signal by said detecting means, for correcting said deviation in synchronization.

7. A text broadcasting signal receiving apparatus in accordance with claim 4, wherein said framing code detection signal forming means comprises prediction timing signal generating means responsiye to detection of the first framing code by said framing code detecting means, for counting said clock signal and generating a timing signal predicting a detection position of a framing code a predetermined number of fields subsequent thereto, and means for determining match/mismatch between a phase of the first framing code detection signal detected by said framing code detecting means and a phase of said predicting timing signal, and defining a framing code detection timing in said predetermined horizontal scanning period of each field in response to the result of the determination.

8. A text broadcasting method or apparatus in which text signals are transmitted and/or received digitally within a signal format having fields at a predetermined frequency, having lines at a predetermind frequency greater than the field frequency, and having a predetermined sub-carrier frequency greater than the line frequency, the said digital text signals having a frequency which is a fraction of the sub-carrier frequency which fraction has relatively simple integers for both its numerator and its denominator, and the frequency of the said digital text signals is such that they return to their previous phase position relative to the line frequency after a predetermined number of field periods.

9. A method or apparatus according to claim 8 in which the said numerator and denominator are both less than 100.

10. A method or apparatus according to claim 9 in which the said numerator and denominator are both less than 20.

11. A method or apparatus according to any one of claims 8 to 10 in which the said signal format is a PAL television signal format.

12. A text broadcasting method or apparatus substantially as herein described with reference to Figures 1 to 45 of the accompanying drawings.