JPH04290383A - Synchronizing signal detection circuit - Google Patents

Abstract

PURPOSE:To provide the synchronizing signal detection circuit realized with simple circuitry using a CMOS process. CONSTITUTION:Using an AFC circuit 2 and a pseudo H pulse generation circuit 3, a pseudo H pulse with the same frequency, phase, and pulse width as that of an H pulse to be outputted from a synchronizing separation circuit is generated. When the H pulse is outputted, the output of a D flip-flop 6 is always 'H'. When the H pulse is not outputted, the D flip-flop 6 outputs alternately the 'H' and 'L'. On one terminal 10 of a hysteresis comparator 12, the output of the D flip-flop 6 is inputted through an integration circuit 9, and the prescribed voltage is applied to the other terminal 11. The output of the hysteresis comparator 12 is changed depending on whether or not the H pulse is outputted, and the presence or absence of the H pulse can be judged.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal detection circuit, and more particularly to a synchronization signal detection circuit for detecting a horizontal synchronization signal contained in a TV signal or a video signal.

0002

2. Description of the Related Art In recent VTRs, in order to prevent the monitor screen from becoming a sandstorm when no video signal is input to the video signal input terminal, horizontal synchronization pulses are sent from the output of a synchronization separation circuit. Processing that determines whether a video signal is being input by detecting the (H pulse) and turns the entire monitor screen blue when no horizontal sync pulse is detected, that is, when no video signal is being input. is being carried out.

0003

However, conventionally, in order to detect such horizontal synchronizing pulses, a synchronizing signal detection circuit having a complicated circuit configuration has been used. The present invention is intended to solve the problems of the prior art, and aims to provide a synchronization signal detection circuit that can be realized with a simple circuit configuration using a CMOS process.

0004

[Means for Solving the Problems] A feature of the synchronization signal detection circuit of the present invention for achieving this object is that it receives an output from a synchronization separation circuit and generates a horizontal synchronization pulse (hereinafter referred to as H pulse) from the synchronization separation circuit. Automatic frequency control circuit (hereinafter referred to as AFC circuit) that outputs an output signal whose frequency and phase are equal or almost equal to this H pulse when outputting normally.
and a pseudo-horizontal synchronizing pulse generation circuit (hereinafter referred to as pseudo-H pulse generation circuit) which receives the output signal of this AFC circuit and outputs a pseudo-horizontal synchronization pulse (hereinafter referred to as pseudo-H pulse) having the same frequency, phase, and pulse width as the H pulse. , a logic that receives a clock pulse with a higher frequency than the H pulse at the clock terminal and outputs the exclusive OR (or NOT-exclusive OR) of the output from the synchronous separation circuit and the output from the pseudo H pulse generation circuit. The comparator includes a circuit, and a comparator having one input terminal to which the output of the logic circuit is input via an integrating circuit, and the other input terminal to which a predetermined voltage is applied.

[0005]

[Operation] When the H pulse is output from the synchronization separation circuit at a predetermined normal level, a pseudo H pulse having the same frequency, phase and pulse width as the H pulse is output from the pseudo H pulse generation circuit. On the other hand, when no H pulse is output from the sync separation circuit, or when an H pulse below a predetermined level is output, the AFC circuit enters a free running state, and the pseudo H pulse generation circuit outputs the output from the sync separation circuit. outputs an unrelated pulse train. Therefore, when the H pulse is output from the sync separation circuit at a normal level, the output of the sync separation circuit and the output of the pseudo H pulse generation circuit are equal, and the exclusive OR of both is always "L", NOT- In the case of exclusive OR, it is always "H", and the output of the logic circuit is always "H" or always "L", but when the H pulse is not output from the synchronous separation circuit, or when the composite When the signal output level is extremely low, the logic circuit outputs “H” in accordance with the free running output of the AFC circuit.
and "L" are output alternately. Therefore,
When the output of this logic circuit is input to the integrating circuit, the output voltage value of the integrating circuit becomes different depending on whether the H pulse is being outputted from the synchronization separation circuit or not. The output of this integrating circuit is input to one terminal of the comparator, and a predetermined voltage is input to the other terminal (the output voltage of the integrating circuit when an H pulse is output and the output voltage when an H pulse is not output or Since a voltage (intermediate between the output voltage of the integrating circuit and the output voltage when the output is not within the normal range) is applied, the output of the comparator changes depending on whether or not the H pulse is output. Judgment can be made.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing the circuit configuration of an embodiment of the synchronization signal detection circuit of the present invention. The input terminal 1 is connected to the output terminal of a synchronization signal separation circuit that separates and outputs a synchronization signal from a composite signal obtained from a TV signal or a video signal. The AFC circuit 2 receives the output of the synchronous signal separation circuit, and outputs a signal with a frequency synchronized with the H pulse when the synchronous separation circuit outputs an H pulse, but when the synchronous separation circuit does not output an H pulse. When it is not present or its output level is not within the normal value range, it enters a free running state and outputs a signal with a frequency unrelated to the output of the synchronization separation circuit.

[0007] The pseudo H pulse generation circuit 3 is connected to the AFC circuit 2.
In response to the output of the AFC circuit 2, a pseudo H pulse having the same frequency and phase as the output signal of the AFC circuit 2 and the same pulse width as the H pulse is output. Therefore, when the H pulse is output from the synchronization separation circuit, the H pulse and the frequency
A pseudo H pulse having substantially the same phase and pulse width is output from the pseudo H pulse generating circuit 3. On the other hand, when the H pulse is not output from the synchronous separation circuit, the AFC circuit 2
A pulse train unrelated to the output of the synchronization separation circuit is output from the pseudo H pulse generation circuit 3 in accordance with the free running output of the synchronous separation circuit.

The NOT-exclusive OR circuit 4 has two input terminals, one of which receives the output of the pseudo H pulse generation circuit 3, and the other of which receives the output of the synchronous separation circuit. Therefore, when an H pulse is being output from the sync separation circuit, the output of the sync separation circuit and the output of the pseudo H pulse generation circuit are equal, so the output of the NOT-exclusive OR circuit 4 is always "H" (HIGH). level). On the other hand, when the H pulse is not output from the sync separator circuit, the output of the sync separator circuit and the output of the pseudo H pulse are unrelated.
” (LOW level) are mixed and the output is often “L”.

In the D flip-flop 6, the output of the NOT-exclusive OR circuit 4 is input to the D input terminal (data input terminal), and the clock pulse (input to the terminal C) is input from the clock terminal 5 (CK). This data is set by . Here, the frequency of the clock pulse is set to be sufficiently higher than the frequency of the H pulse. The Q output of the D flip-flop 6 always outputs "H" when the H pulse is output from the sync separator circuit, and when the H pulse is not output from the sync separator circuit or when the output level is at the normal value. When it is not within the range, "H" and "L" are mixed and output. Therefore, when such a Q output is input to an integrating circuit 9 composed of a resistor 7 and a capacitor 8, the output voltage of the integrating circuit 9 when an H pulse is output from the synchronous separating circuit is the same as that of the synchronous separating circuit. It becomes higher than when no H pulse is output from the circuit.

The output of the integrating circuit 9 is input to the (+) terminal 10 of the hysteresis comparator 12, and the (-) terminal 1
1 shows the output voltage of the integrating circuit 9 when the H pulse is output and the integrating circuit 9 when the H pulse is not output.
A voltage intermediate between the output voltage and the output voltage is applied. Therefore, when the H pulse is output from the synchronous separation circuit, the voltage at the (+) terminal 10 becomes higher than the voltage at the (-) terminal 11, and the output terminal 1 of the hysteresis comparator 12
"H" is output to 3. On the other hand, when the H pulse is not output from the synchronous separation circuit, the voltage at the (+) terminal 10 becomes lower than the voltage at the (-) terminal 11, and the voltage at the output terminal 13 becomes lower than the voltage at the (-) terminal 11.
“L” is output. In this way, the output of the hysteresis comparator 12 changes depending on whether or not the H pulse is output from the synchronization separation circuit, making it possible to determine the presence or absence of the H pulse. In this embodiment, a hysteresis comparator is used, so once this H pulse detection circuit is
When a pulseless state is detected, the detection signal is not reset unless the input level rises above a certain value. Therefore, a stable detection operation that is not affected by noise or the like is realized. Note that the above circuit configuration can be easily realized using a CMOS process because each circuit, except for the capacitor 8, can be realized by a combination of logic circuits.

In the embodiment described above, when the H pulse is output from the synchronous separation circuit, the output terminal 1 is
3, and when the H pulse is not output, the output terminal 13 outputs "L". However, depending on the specifications, the H pulse may be output from the synchronous separation circuit. "L" is output to the output terminal 13 when the pulse is being output, and when the H pulse is not output, the output terminal 13 is
Needless to say, "H" may also be output. Therefore, the NOT-exclusive OR circuit 4 may be a normal exclusive OR circuit. Also, the output of the integrating circuit 9 is input to the (-) terminal 11 side of the hysteresis comparator 12, and the output voltage and H pulse of the integrating circuit 9 when the H pulse is output to the (+) terminal 10 side are output. It goes without saying that a voltage intermediate between the output voltage of the integrating circuit 9 and the output voltage when the integrating circuit 9 is not being applied may be applied.

0012

As described above, according to the present invention, an H pulse can be detected from the output of the synchronous separation circuit with a simple circuit configuration using a CMOS process.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of a synchronization signal detection circuit of the present invention.

[Explanation of symbols]

1 Input terminal 2 AFC circuit 3 Pseudo H pulse generation circuit 4 Negative logic exclusive OR circuit 5 Clock terminal 6 D flip-flop 7 Resistance 8 Capacitor 9 Integral circuit 10 (+) input terminal 11 (-) input terminal 12 Hysteresis comparator 13 Output terminal

Claims (1)

[Claims] 1. An automatic frequency control circuit that receives an output from a synchronization separation circuit and outputs an output signal having a frequency equal to the horizontal synchronization pulse when the horizontal synchronization pulse is normally output from the synchronization separation circuit; a pseudo-horizontal sync pulse generation circuit that receives an output signal from the automatic frequency control circuit and outputs a pseudo-horizontal sync pulse whose frequency, phase, and pulse width are equal to or approximately equal to the horizontal sync pulse; a logic circuit that receives a clock pulse at a clock terminal and outputs an exclusive OR (or NOT-exclusive OR) of the output from the synchronization separation circuit and the output from the pseudo horizontal synchronization pulse generation circuit; 1. A synchronization signal detection circuit comprising: an input terminal to which the output of the logic circuit is input via an integrating circuit; and a comparator to which a predetermined voltage is applied to the other input terminal.