JPS6165668A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To eliminate an erroneous detecting signal when the erroneous detecting signal is included in a synchronizing signal by obtaining an 'or' with a synchronizing signal outputted from a comparing circuit and a delay synchronizing signal which delays the said signal. CONSTITUTION:A delay circuit 6 and an 'or' circuit 7 are added to a conventional synchronizing separator circuit. When a television signal (including noise) is inputted to an input terminal 3 of a clamp circuit 1, an erroneous detecting signal, which erroneously detects a noise, is included in a synchronizing signal, an output of a comparing circuit 2. The output (b) of the comparing circuit 2 is respectively inputted into one side input terminal of the delay circuit 6 and the 'or' circuit 7. The delay circuit 6 delays the synchronizing signal including the erroneous detecting signal to a delay time (t) only. In this case, the delay time (t) is selected so that it may become shorter than the time of a pulse width of an equalizing pulse of a television signal. An output (c) of the delay circuit 6 is inputted to other inputs terminal of the 'or' circuit 7. The 'or' circuit 7 obtains 'or' of the output (b) and the output (c) and as the result, the erroneous detecting signal is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization separation circuit that separates a synchronization signal from a composite video signal, and particularly to a synchronization separation circuit that can separate a synchronization signal that is not affected by noise.

[Prior art]

A conventional synchronization separation circuit for separating a synchronization signal from a composite video signal (hereinafter referred to as a television signal) includes a 1-clamp circuit 1 and a comparison circuit 2, as shown in FIG. According to such a conventional sync separation circuit, the TV signal input to the input terminal 3 of the clamp circuit 10 is clamped to a predetermined voltage at the top of the sync signal by the clamp circuit 1, and then the level of the sync tip is clamped to a predetermined voltage. Input to the non-inverting input terminal.

A reference voltage Vref set to a predetermined value between the black level of the television signal and the level of the synchronization tip is inputted from the reference voltage source 4 to the inverting input terminal of the comparator circuit 2, and is connected to the output of the clamp circuit 1. As a result of the comparison, the synchronizing signals are separated and outputted from the output terminal 5 of the comparator circuit 2.

[Problem that the invention seeks to solve]

Generally, external noise may be added to a television signal during transmission from a signal source to a receiving terminal. For example, if the transmission path is in free space, impulsive noise emitted from an automobile's spark plug is added to the television signal, and the video signal is mixed into the p-synchronization signal section due to the noise. When such a television signal is input to a conventional sync separation circuit as described in FIG. 3, noise parts other than the sync signal may be regarded as sync signals and separated, that is, erroneously detected. If the synchronization signal includes an erroneously detected signal, a problem arises in that, for example, a high-efficiency encoding device for television signals cannot perform encoding processing. That is, in the efficiency encoding device for television signals, the synchronization signal of the television signal is separated, and the phase ratio is 412 (412) with the next synchronization signal as a reference (in the phase synchronization circuit consisting of the i21 path and the voltage controlled oscillation circuit, A clock signal synchronized with the synchronization signal is generated and high-efficiency encoding processing is performed. Therefore, if a synchronization signal containing a signal that is erroneously detected as a result of added noise is input, the phase synchronization circuit will malfunction. The ninth clock signal becomes out of synchronization with the synchronization signal, making it impossible to perform high-efficiency encoding processing. [Object of the Invention] An object of the present invention is to prevent false detections due to noise when separating the synchronization signal from the television signal. An object of the present invention is to provide a synchronization separation circuit capable of generating a stable synchronization signal that is not affected by noise.

[Structure of the invention]

The synchronization separation circuit of the present invention includes a clamp circuit that clamps a television signal, and a voltage set to an arbitrary voltage between the black level of the television signal of the output of the clamp circuit and the level of the synchronization tip, and the next reference voltage and the clamp circuit. a comparison circuit for comparing the output of the comparison circuit with the output of the comparison circuit; a delay circuit for delaying the output of the comparison circuit by a time smaller than the vertical equalization pulse width of the television signal; and the output of the comparison circuit and the output of the delay circuit. When the synchronization signal outputted from the comparator circuit is ORed with a delayed synchronization signal obtained by delaying this synchronization signal by a predetermined time, synchronization is achieved. If the signal contains a falsely detected signal,
Since there is a time difference between the erroneous detection signal in the synchronization signal and the erroneous detection signal in the delayed synchronization signal (due to the delay), the erroneous detection signal can be deleted as a result of the logical sum. In this case, it is necessary to select the delay so that the delay time is smaller than the time equal to the vertical equalization minus the pulse width so that even the vertical equalization pulse is not deleted by the logical sum.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the synchronous separation circuit of the present invention. In this embodiment, a delay circuit 6 and an OR circuit 7 are added to the conventional synchronous separation circuit shown in FIG. be. Therefore, the elements that are the same as those in FIG.
The same numbers are superscripted.

FIG. 2 is a waveform diagram of each part signal for explaining the operation of this embodiment), each signal waveform a, b, c.

d indicates the waveform of the signal at each part a, b, c, and d shown in FIG. 1, respectively.

In FIGS. 1 and 2, when a television signal (including noise) is input to the input terminal 3 of the clamp circuit 10,
The clamp circuit 1 clamps the level of the synchronization tip of the television signal to a predetermined voltage (hereinafter referred to as clamp voltage) K. Waveform a in Figure 2 shows the waveform of a clamped TV signal, 9.9 shows the synchronization tip of the TV signal, and f shows impulsive noise added to the video signal. . It is assumed that this noise f has an amplitude extending below the clamp voltage.

The output a1 of the clamp circuit 1, that is, the clamped television signal, is input to the non-inverting input terminal of the comparator circuit 2. The inverting input terminal of the comparator circuit 1 receives a reference voltage Vref set to an arbitrary voltage between the black level of the clamped television signal and the level of the synchronization tip 9, that is, the clamp voltage. It has been entered. In the comparator circuit 2, the output a of the clamp circuit 1 and the reference voltage Vref are compared, the sync signal portion below the reference voltage Vref is separated, and a sync signal having the waveform shown in Figure 2 is output.

This synchronization signal contains nine erroneous detection signals f'
It is included.

The output of the comparator circuit 2 containing the false detection signal f' is input to the delay circuit 6 and one input terminal of the OR gate [7]. The AI extension circuit 6 delays the synchronization signal t containing the false detection signal f' by the delay time t, and outputs a delayed synchronization signal as shown in waveform C in FIG.

In this case, the delay time t is selected so that it is also smaller than the pulse width time of the equalization pulse of the television signal. The reason for this is to prevent the vertical equalization pulse from disappearing due to the logical sum in the logical sum circuit 7, which will be described later.If the vertical equalization pulse were to disappear, This is because the image/ratio synchronization signal is not separated correctly. The output C of the fc delay circuit 6 delayed as described above is input to the other input terminal of the OR circuit 7.

The OR circuit 7 performs a logical OR between the output of the comparator circuit and the output C of the delay circuit 6. As is clear from waveforms S and C in Figure K2, there is a time lag between the false detection signal f' in waveform A and the false detection signal f' in waveform C, so the false detection signal f' is determined by logical sum. You can see that it will be deleted. Waveform d in FIG. 2 shows a synchronization signal from which the false detection signal f' has been removed, and this synchronization signal is output to the output terminal 8 of the OR circuit 7. The output d of the OR circuit 7 is a synchronization signal that is not affected by noise.

〔Effect of the invention〕

As explained above, according to the present invention, even in a television signal in which a noisy video signal has entered the sync level part,
It is possible to separate synchronization signals that are not affected by noise. Then, for example, in a high-capacity encoding device for television signals,
Since the phase synchronization circuit does not malfunction, it becomes possible to perform high-performance encoding processing.

[Brief explanation of drawings]

Figure 1 shows an example of the synchronous separation circuit of the present invention! FIG. 2 is a diagram showing signal waveforms of various parts for explaining the operation of the first embodiment, and FIG. 3 is a diagram showing a conventional synchronization separation circuit. l... Clamp circuit, 2... Comparison circuit, 3... Clamp circuit input terminal, 4...
...Reference i pressure source, 5... Output terminal of comparison circuit, 6... Delay circuit, F... OR circuit, 8... Logic Output terminal of sum circuit, 9...
・Television signal synchronization tip. Strawberry l Illustration potato 3 Illustration

Claims (1)

[Claims] (1) A clamp circuit that clamps a television signal, and a reference voltage set to an arbitrary voltage between the black level of the television signal of the output of the clamp circuit and the level of the synchronization tip, and the output of the clamp circuit. a comparison circuit for comparison, a delay circuit for delaying the output of the comparison circuit by a time smaller than the vertical equalization pulse width of the television signal, and a logical OR of the output of the comparison circuit and the output of the delay circuit. A synchronous separation circuit comprising an OR circuit.