JPS62207071A - Vertical synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To obtain a vertical synchronizing signal free from the inflence of noises by providing a pulse generating circuit which generates a pulse whose width is wider than that of a horizontal synchronizing signal but narrower than that of the vertical synchronizing width of a vertical synchronizing cycle, and providing a resistor which reads a composite synchronizing signal at the rising of an output pulse from said pulse generating circuit. CONSTITUTION:When there is a noise N in the composite synchronizing signal, a monostable multivibrator circuit 1 generates a pulse of a width t2 at a point (g) which is the rising point of the pulse due to the noise but not the trailing edge of the composite synchronizing signal. Accordingly, the register circuit 2 is made read the point (i) of the composite synchronizing signal by the rising point (h) of said pulse of the width t2 triggered by the noise. However, at this point of reading, the influence of the noise (d) is already eliminated from the point (i), hence the circuit 2 is not subjected to the influence of noise. In such a way, a vertical synchronizing signal free from the influence of noise is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit that detects a vertical synchronization signal from a composite synchronization signal of a television, and more specifically, to a circuit that detects a vertical synchronization signal from a composite synchronization signal of a television. The present invention relates to a vertical synchronization separation circuit that separates vertical synchronization signals.

[Conventional technology]

A vertical synchronization separation circuit separates a vertical synchronization signal from a composite synchronization signal consisting of a horizontal synchronization signal and a vertical synchronization signal. , a system that uses a clock to digitally separate the signals is also known. Conventionally, when separating the vertical synchronization signal from the composite synchronization signal of a television, the latter method separates the composite synchronization signal by dividing the horizontal synchronization frequency by two times. The signal is input to a register operating with a clock of twice the frequency, and the output of the register is used as a separated vertical synchronization signal (for example, Japanese Patent Application No. 129009/1982).

Figure 4 shows the phase relationship of each signal in the case of such a conventional configuration. Figure 4 (a) shows the composite synchronization signal input to the register, Figure 4 (b) shows the clock, and 4
Figure (c) shows the waveform of the separated vertical synchronization signal obtained as an output from the register.

[Problem that the invention seeks to solve]

In the conventional vertical synchronization separation circuit described above, as in the composite synchronization signal shown in FIG. 5(a), the noise pulse N between two horizontal synchronizations overlaps with the rising edge of the clock shown in FIG. 5(b). When ε appears, a noise waveform E as shown in FIG. 5(C) is generated at that point, so there is a drawback that the vertical synchronization signal is erroneously detected.

An object of the present invention is to eliminate such drawbacks and provide a vertical synchronization separation circuit that does not cause false detection.

[Means for solving problems]

The present invention provides a vertical synchronization separation circuit that separates a vertical synchronization signal from a composite synchronization signal of a television signal. It is characterized by having a pulse generation circuit that generates a pulse with a width narrower than the pulse width, and a register that reads a composite synchronization signal at the rising edge of the output of this pulse generation circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In Figure 1,
A composite synchronization signal of the television is applied to terminal A. Terminal A
The composite synchronization signal applied to is applied to the data input terminals of the monomulti circuit 1 and the register circuit 2. The output of the monomulti circuit 1 is connected to a clock terminal of a register circuit 2, and a separated vertical synchronization signal is output from the register circuit 2 and sent to a terminal B.

The monomulti circuit 1 is a pulse generation circuit that generates a pulse having a width wider than a horizontal synchronization signal and narrower than a vertical synchronization width in a vertical synchronization period, based on the falling edge of a composite synchronization signal of a television signal. The register circuit 2 reads the composite synchronization signal of the television signal at the rising edge of the pulse and separates the vertical synchronization signal.

Next, the operation of separating vertical synchronizing signals will be explained in detail using FIGS. 2 and 3.

FIG. 2(a) shows a television composite synchronization signal input to terminal A. When this composite sync signal is applied to the mono multi-circuit 1, the mono-multi circuit 1 uses the falling point of the composite sync signal (for example, point d in Fig. 2) as a reference, and the horizontal sync signal width to is wider than the horizontal sync signal width to. The vertical synchronization width of the synchronization period t3 is 1. Since a pulse having a width of t2, which is narrower than the vertical synchronization width of the synchronization period t3, is generated,
A signal having a waveform as shown in FIG. 2(b) is generated from the monomulti circuit shown in FIG. 1. At the rising point of the signal output from this mono multi-circuit 1 (for example, point e in Figure 2),
The register circuit 2 of FIG. 1 reads the composite synchronization signal (point f) of FIG. 2(a), and obtains a vertical synchronization signal as shown in FIG. 2(C).

Next, the operation when there is noise in the composite synchronization signal will be explained using FIG.

As shown in FIG. 3(a), when there is noise N in the composite synchronization signal, the output of the mono multi-circuit 1 is at the falling point g due to noise other than the falling point of the composite synchronization signal mentioned above. As shown in FIG. 3(b), a pulse of width t2 is generated. Therefore, in this case, the register circuit 2 reads the i point of the composite synchronization signal at the rising point h of the pulse of width t2 generated by the noise as a trigger.

However, at the time of reading, the influence of the noise d has already disappeared, so the register circuit 2
The output of is not affected by noise. Therefore, even if there is noise, a vertical synchronization signal that is not affected by noise as shown in FIG. 3(C) can be obtained.

〔Effect of the invention〕

As explained above, the present invention prevents noise from being affected by a composite synchronization signal by reading the composite synchronization signal with a register circuit after a predetermined period of time after the noise has been added. This has the effect that a vertical synchronization signal can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1, and 311! l is a waveform diagram to explain the operation when noise pulses are included, Figure 4 is a waveform diagram to explain the operation when using a conventional vertical synchronization separation circuit, and Figure 5 is a waveform diagram to explain the operation when noise pulses are included. FIG. 3 is a waveform diagram showing how false detection occurs when l...Mono multi circuit 2...Register circuit A, B...Terminal

Claims (1)

[Claims] (1) In the vertical synchronization separation circuit that separates the vertical synchronization signal from the composite synchronization signal of the television signal, with reference to the falling edge of the composite synchronization signal of the television signal,
It is characterized by having a pulse generation circuit that generates a pulse whose width is wider than the horizontal synchronization signal and narrower than the vertical synchronization width of the vertical synchronization period, and a register that reads the composite synchronization signal at the rising edge of the output of this pulse generation circuit. Vertical sync separation circuit.