JPS5990463A - Field discriminating circuit of television signal - Google Patents

Abstract

PURPOSE:To detect a horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync) at the same time by utilizing that the phase between the Vsync and the Hsync has 1/2H at an odd and an even number field so as to apply field discrimination. CONSTITUTION:A monostable multivibrator is triggered by a composite synchronizing signal (Csync), extracts an equivalent pulse in the Csync and gives a delay of r1 for the separation of the Hsync. This time constant r1 is 0.5H-0.9H, which gives a sufficient margin on the design and adjustment. The Vsync separating circuit consists of an integrating circuit and a Schmitt trigger circuit, and the time constant r2 of the integrated circuit has a sufficient margin as 0.5H-0.9H. An OR circuit 8 ORs the input Csync and the separated Hsync. An OR circuit 9 ORs the output of the OR circuit 8 and the Vsync and a field discriminating pulse as shown in Ke in figure is obtained at the even number fields.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization signal separation circuit for a device for recording or reproducing video signals, and in particular to a circuit for distinguishing between even and odd fields necessary for screen synchronization and editing. This is related to the improvement of.

Conventional structure and its problems Traditionally, field identification was performed using a composite synchronization signal (hereinafter referred to as C3y
Obtained from n (abbreviated). 111 synchronization signal (hereinafter v
It utilizes the fact that the number of equivalent pulses before or after the horizontal synchronization signal (hereinafter referred to as H5sync) and the time interval between the horizontal synchronizing signal (hereinafter referred to as H5sync) differs between odd and even fields. Therefore, (a) a relatively high-precision monostable multivibrator (hereinafter abbreviated as mono-multi), a calculation circuit, a comparison circuit, etc. are required, and the circuit configuration becomes complicated.

(b) Easily affected by noise such as dropouts.

(c) A dedicated field identification circuit is required, and a separate horizontal synchronization signal separation circuit is required.

There are other problems.

Next, an example of a conventionally used circuit will be explained using a diagram. FIG. 1 is its block diagram.

FIG. 2 is a timing diagram thereof. (1) is vsync
This is a separation circuit, consisting of an integrating circuit, a Schmitt trigger circuit, etc., and is input to point (A). v5 from csync
．． . Separate 0. (2) is the first monomulti.

It is triggered by the leading edge of the vsync and outputs a pulse with a width of about 5H. The accuracy of this monomulti (2), including temperature characteristics, is within ±1/4 H at maximum, and when the adjustment range is taken into account, it needs to be within about 5%.

(3) is a second monomulti, which is triggered by the falling edge of monomulti (2) and outputs a pulse with a width of approximately 1/2H. (4) is an inverting circuit, and input C5yn
C5ync is inserted according to the polarity of C5ync, and its output C5ync is connected to the output of the second monomulti (3) (ANI).
5). As shown in the timing diagram of FIG. 2, both inputs of this ANT) circuit (5) differ in whether they contain one Hsync or not in an odd field and an even field, so in an odd field, Output (E)
Generate a pulse at a point.

Ao"□Eo in FIG. 2 is an odd field.

Ae”-Ee is each A-E in Fig. 1 when the field is an even number.
Shows the waveform of the points.

In this case, there are problems such as the accuracy and difficulty of adjusting the first mono multi There is.

Another method using a counter is
No. 7, No. 57-28284, etc., but all of them have some of the problems mentioned above.

OBJECTS OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide a field identification circuit which can simplify the circuit configuration and at the same time provide 1 (S7nC*vsync).

Structure of the Invention The present invention focuses on the fact that the phase of vsync and n5sync has a difference of 1/2H between an odd field and an even field, and is triggered by an input composite synchronization signal, and an equalization pulse is generated from the composite synchronization signal. Remove it.

A delay circuit that separates a horizontal synchronization signal, a vertical synchronization signal separation circuit that passes the composite synchronization signal through an appropriate time constant circuit, shapes the waveform, and separates a vertical synchronization signal, and a composite synchronization signal and delay circuit as described in IW. a first gate circuit that ORs the output of the first gate circuit with the horizontal synchronization signal separated by r, and a first gate circuit that ORs the output of the first gate circuit with the vertical synchronization signal separated by the vertical synchronization signal separation circuit. 2 gate circuits, and the second
The field identification pulse of the composite synchronizing signal is obtained from the output of the gate circuit of the sensor, and since field identification is performed using this, the detection delay time is small and almost no adjustment is required. Furthermore, since *Hsync and Vsync are used to detect the phase difference, there is an advantage that H8ynC+"5ynC can also be output at the same time, although the field identification circuit has a simple configuration.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 8th
The figure is a block diagram showing the basic configuration of the present invention, and FIG. 4 is a timing diagram thereof. (6) is a monomulti, which is triggered by csync input at point (G) and extracts the equivalent pulse in I csync.

I (11 delay operations are performed to perform sync separation.

The time constant τ1 of this monomulti (6) is 0.5) 1-0.
9H, there is sufficient margin in terms of design and adjustment. (7) is v8
．． . This is a C separation circuit, and in this embodiment, it is composed of an integrating circuit and a Schmitt trigger circuit. The time constant τ2 of this integrating circuit also has a design value of 0.51T to 0.9H, which is a sufficiently large margin.

(8) is a first OR circuit, and the inputs C8,. . H5. . . Take the logical OR with. (9) is the second
The output of the OR circuit (8) and V5. □
. If it is an even field, K in Figure 4
A field identification pulse, denoted e, can be obtained.

In Figure 3, the data 1 circuit shown as an OR circuit can be changed to NAND, NOR, ANI depending on the pulse polarity etc.
This can actually be done through circuits and their composition. Nu r
Monomulti (61Lt) used to extract the valence pulse
If necessary, it can also be implemented with a delay circuit that combines an oscillator, counter, and gate.

Next, another embodiment of the present invention will be described using the block diagram of FIG. 5 and the timing diagram of FIG. 6.

In FIGS. 5 and 6, components and pulses designated by the same reference numerals as in FIGS. 3N and 4 have the same operation and timing, and therefore will not be described here. (+1 is an integrating circuit (or mono-multi), which is inserted to compensate for the delay in the rise time of mono-multi (6), and an integrating circuit of a resistor and capacitor configured to have a small time constant is sufficient for the purpose. achieved.

This is inserted so that field detection can be maintained in normal operation even when noise is superimposed on the Vsync separated by the Vsync circuit (7) in the mono-multiple circuit (7). 04 is a flip-flop, which divides the frequency of the monomulti Ov output vsync pulse into 1/2 and
It is configured to be constantly reset by the field identification pulse of the R circuit (0) output, and after that, the output E M If Vsync is completely reset, and its polarity indicates whether the field is odd or even. Become.

Effects of the Invention (1) The present invention focuses on the phase difference between Vsync and Hsync, and in order to obtain a field identification pulse, the delay time of the conventionally used Vsync and Hsync separation circuit is set to an appropriate value, and an OR circuit etc. A field identification pulse can be easily obtained by simply adding a gate.

As a result, it is possible to obtain Vsync"Hsync, which is used as a control signal for the motor that rotates the recording medium, and at the same time obtain the field identification pulse, which is essential for single-screen synchronization, editing, etc.
By using c, the absolute address of ln5ync can be easily obtained, and it can also be conveniently used for address detection on video disks, etc., and for measuring video signals using VIT and VTR signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of a field identification circuit, and FIG. 2 is a timing diagram of a first match. 8th figure is a basic configuration diagram of the field identification circuit according to the present invention, and FIG. 4 is a timing diagram of each point in FIG. 8. FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a timing diagram of FIG. 5. (6)... Mono multi (delay circuit), (7)...
・Vsync separation circuit, f8H9)...OR circuit,
00...Integrator circuit once...Mono multi, Q4...
・Flip-flop agent Yoshihiro Morimoto Figure 1 Figure 2 (a) @ Soft fee 71F' (b) Tetsu Kaede 14-ld' Ee □ Figure 3 Figure 4 K. e Fig. 5 n Fig. 5 M even

Claims (1)

[Claims] 1. In a circuit that separates a horizontal synchronization signal and a vertical synchronization signal from a decoded synchronization signal of a TV signal, the circuit is triggered by an input composite synchronization signal and removes an equalization pulse from the composite synchronization signal. a delay circuit that separates the horizontal synchronization signal; a vertical synchronization signal separation circuit that passes the composite synchronization signal through an appropriate time constant circuit, shapes the waveform, and separates the vertical synchronization signal; and the composite synchronization signal and the delay circuit. a first gate circuit that performs a logical sum with the separated horizontal synchronizing signal; and a second gate circuit that performs a logical sum between the output of the first gate circuit and the vertical synchronizing signal separated by the vertical synchronizing signal separation circuit. 1. A field identification circuit for a television signal, characterized in that the field identification pulse of a composite synchronization signal is obtained from the output of the second gate circuit. 2. When calculating the logical sum of the composite synchronization signal and the horizontal synchronization signal, in order to compensate for the delay time of the delay circuit, the composite synchronization signal is passed through a circuit that slightly delays it, and then the input of the first gate circuit and Claim 1 characterized in that
Field identification circuit for television signals as described in Section 1. 8. The field identification pulse is changed to a signal with 1/2 period of the previous vertical 1nl ILA signal synchronized with even and odd fields by resetting the flip-flop circuit that divides the vertical 11 synchronization signal by 172. 2. A field identification circuit for television signals according to claim 1, characterized in that: