JPH0234510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a synchronization signal separation circuit for a device for recording or reproducing video signals, and in particular to a circuit for identifying even and odd fields necessary for screen synchronization and editing. This is related to the improvement of.

Conventional structure and its problems Conventionally, fields are identified by the number of equivalent pulses in front or behind the vertical synchronization signal (hereinafter referred to as Vsync) obtained from the composite synchronization signal (hereinafter referred to as Csync), or by the horizontal It takes advantage of the fact that the time interval with the synchronization signal (hereinafter abbreviated as Hysnc) differs between odd and even fields. Therefore, (a) a relatively high-precision monostable multivibrator (hereinafter abbreviated as mono-multi), a calculation circuit, a comparison circuit, etc. are required, making the circuit configuration complicated.

(b) Easily affected by noise such as dropouts.

(c) A dedicated circuit for field identification is required, and a separate horizontal synchronization signal separation circuit is required.

There are other problems.

Next, an example of a conventionally used circuit will be explained using a diagram. Figure 1 is its block diagram.
FIG. 2 is a timing diagram. 1 is a Vsync separation circuit, which is composed of an integrating circuit, a Schmitt trigger circuit, etc.
Separate Vsync. 2 is the first monomulti, triggered by the leading edge of the Vsnyc, about 5H
Outputs a pulse with a width of . The accuracy of this MonoMulti 2, including temperature characteristics, is within ±1/4H at maximum, and if the adjustment range is taken into account, it needs to be tightened to about 5%. 3 is the second monomulti, which is triggered by the falling edge of mono multi 2 and outputs a pulse with a width of approximately 1/2H. 4 is an inverting circuit, and the input
inserted depending on the polarity of Csync and its output
Csync is AND with the output of the second monomulti 3
It is input to circuit 5. Both inputs of this AND circuit 5, as shown in the timing diagram of FIG. generates a pulse.

In FIG. 2, A _p to E _p represent the waveforms at points A to E in FIG. 1 when the field is an odd field, and A _e through E _e when the field is an even field.

In this case, there are problems such as the accuracy and difficulty of adjusting the first monomulti 2, the need for a separate Hsync separation circuit, the fact that the detected output is much slower than Vsync, and the fact that it is susceptible to noise. .

Another method using a counter is
No. 1847, No. 57-28234, etc., but all of them have some of the problems mentioned above.

OBJECTS OF THE INVENTION In view of the above points, an object of the present invention is to provide a field identification circuit that has a simple circuit configuration and can simultaneously detect Hsync and Vsync.

Structure of the Invention The present invention focuses on the fact that there is a 1/2H difference in phase between Vsync and Hsync between odd and even fields, and is triggered by an input composite synchronization signal, and an equalization pulse is generated from the composite synchronization signal. remove,
a horizontal synchronization signal separation circuit that separates the horizontal synchronization signal; a vertical synchronization signal separation circuit that passes the composite synchronization signal through an appropriate integration circuit and then shapes the waveform to separate the vertical synchronization signal; a first gate circuit that takes a logical sum with the horizontal synchronizing signal separated by the synchronizing signal separation circuit; and a logical sum of the output of the first gate circuit and the vertical synchronizing signal separated by the vertical synchronizing signal separating circuit; A field identification pulse of a composite synchronization signal is obtained from the output of the second gate circuit, and this is used as a reset pulse for a flip-flop that divides the frequency of the vertical synchronization signal by 1/2. With this configuration, field identification is performed, so the detection delay time is small and adjustment is almost unnecessary. Also, when detecting the phase difference,
Since Hsync and Vsync are used, it is a simple field identification circuit configuration, but at the same time
It also has the advantage of being able to output Hsync and Vsync.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on the drawings. FIG. 3 is a block diagram of the field identification circuit of the first embodiment showing the basic configuration of the present invention, and FIGS. 4a and 4b and FIG. 5 are timing diagrams thereof. 6 is mono multi and is input to point G
Triggered by Csync (indicated by G _p and G _e in Figure 4 a and b), extracting the equivalent pulse during Csync,
A delay operation of τ ₁ is performed to perform Hsync separation. The time constant τ ₁ of this monomulti 6 is 0.5H to 0.9H, which has sufficient margin for design and adjustment, and is shown in Figure 4 a and b.
Outputs waveforms shown by H _p and _He . Figure 4 a and b are timing diagrams drawn at the horizontal synchronization signal rate (63.5 μs), and G _p ~ K _p in Figure 4 a in the upper row.
In the case of an odd number field, in Figure 4b in the lower row
Each G in Figure 3 when G _e ~K _e is an even field
The waveform at point K is shown. 7 is a Vsync isolation circuit;
In this embodiment, it is composed of an integrating circuit and a Schmitt trigger circuit. The time constant τ ₂ of this integrator circuit is also
A design value of 0.5H to 0.9H can be obtained with sufficient margin.
These waveforms are shown as J _p and J _e in FIG. 8 is the first
It is an OR circuit, and takes the logical sum of Csync G _p , G _e and Hsync H _p , H _e separated by the monomulti 6. As shown by I _p and I _e , this output waveform has different phases from Vsync J _p and J _e in odd and even fields. 9 is a second OR circuit, which takes the logical sum of the outputs I _p and _e of the OR circuit 8 and Vsync J _p and J _e ,
In the case of an even field, a field identification pulse shown as K _e in FIG. 4b can be obtained. 12
is a flip-flop, and is configured to divide the Vsync J _p and J _e pulses by 1/2 and to be constantly reset by the field identification pulse of the OR circuit 9 output. Therefore, its output M is completely synchronized with Vsync. The polarity indicates whether the field is odd or even.

This situation will be briefly explained using FIG. Figure 5 is a timing diagram written at the vertical synchronization signal rate (16.7ms), and Vsync, denoted by J, is
As mentioned above, the frequency is divided by 1/2 by the flip-flop 12, and a 30 Hz signal with a duty of 50% is obtained as shown by M in FIG. Flip-flop 12 in Fig. 3
is reset by K, which is the output of the second OR circuit 9, and it is possible to obtain a 50% duty field identification signal M that always rises during even fields and rises during odd fields.

Next, a second embodiment will be described using FIG. 6, FIG. 7, FIG. 8, and FIG. 9.

FIG. 6 shows a block diagram of the field identification circuit in the second embodiment. The basic configuration and operation are the same as those in the first embodiment shown in FIG. Integrating circuit 10 for preventing noise pulses (hazard)
A second monomulti 11 has been newly inserted to prevent malfunctions even if there is a large dropout in Csync.

The operation of the integrating circuit 10 will be explained using FIG. 7. G in FIG. 7 is the input Csync, which is particularly an enlarged period of an equivalent pulse. H
is the output of the monomulti 6 which is triggered by the falling edge of G and has a time constant sufficient to erase the equivalent pulse. Here, a delay time of τ ₄ occurs after the monomulti 6 is triggered until the output rises, and if this delay time τ ₄ is longer than the response time of the OR circuit 8, the OR
A hazard indicated by a broken line _I2 is output as noise to the output I of the circuit 8. Therefore, the occurrence of hazard I ₂ is prevented by inserting an integrating circuit 10 to slightly delay the input N of the OR circuit 8 and giving it a slope as shown by N in FIG.

The operation of the second monomulti 11 will be explained using FIGS. 8a and 8b and FIG. 9. In Figure 8 a and b
L _p and L _e are triggered by J _p and L _e in Fig. 4 a and b, and are outputted as τ ₃ during the 3/4 to 4/5 vertical synchronization signal period to the Vsync separation circuit 7 in Fig. 9. At the output J of J _D
Even if a dropout occurs, it is not input to the flip-flop 12 and the field identification signal M
prevents it from being disturbed.

As described above, by inserting the integrating circuit 10 and the second monomulti 11, a more stable field identification circuit can be realized.

Since the integration circuit 10 compensates for the delay of the monomulti 6, it can be replaced with a delay gate that uses several stages of inverters or the like to delay the delay.

In Figures 3 and 6, the gate circuits shown as OR circuits are NAND,
This can also be achieved using NOR, AND circuits, or their combination. Furthermore, the monomulti 6 used to extract the equivalent pulses can be realized by a delay circuit combining an oscillator, a counter, and a gate, if necessary.

Effects of the Invention As described above, the present invention focuses on the phase difference between Vsync and Hsync, and sets the delay time of the conventionally used Vsync and Hsync separation circuit to an appropriate value in order to obtain a field identification pulse. A field identification pulse can be easily obtained by simply adding a gate. In addition, it is fully synchronized with the vertical synchronization signal edge, and the duty is exactly 50%.
In addition, the field identification signal is not disturbed even if the field identification pulse is not output due to noise or the like.

This allows Vsync and Hsync, which are used as control signals for the motor that rotates the recording medium, to
At the same time, you can also obtain the field identification pulse necessary for screen synchronization editing, etc. Also, by using the field identification pulse and Hsync, you can easily obtain the absolute address of Hsync, which can be used for address detection of video disks, etc. It can also be conveniently used for measurements using VIT and VTR signals.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example of a field identification circuit, Fig. 2 is a timing diagram of each point in Fig. 1,
FIG. 3 is a block diagram of a field identification circuit according to the first embodiment of the present invention, FIGS.
The figure is a timing diagram of each point in FIG. 3, FIG. 6 is a block diagram of a field identification circuit according to a second embodiment of the present invention, and FIGS. FIG. 6...Mono multi (delay circuit), 7...Vsync
Separation circuit, 8, 9...OR circuit, 10...integrator circuit, 11...mono multi, 12...flip-flop.

Claims (1)

[Claims] 1. Triggered by a composite synchronization signal of a TV signal,
A horizontal synchronization signal separation circuit using a mono-multivibrator etc. removes the equalization pulse from the composite synchronization signal and separates the horizontal synchronization signal, and the composite synchronization signal is passed through an appropriate integration circuit, then waveform-shaped and vertical synchronization is performed. A vertical synchronization signal separation circuit that separates signals,
a flip-flop that frequency-divides the output of the vertical synchronization signal separation circuit by 1/2; a first gate circuit that performs an OR of the composite synchronization signal and the horizontal synchronization signal separated by the horizontal synchronization signal separation circuit; a second gate circuit that takes the logical sum of the first gate circuit output and the vertical synchronization signal separated by the vertical synchronization signal separation circuit; A field identification circuit for a television signal, characterized in that a field identification circuit for a television signal is obtained, and is used as a reset input of the flip-flop. 2. When calculating the logical sum of the composite synchronization signal and the horizontal synchronization signal, in order to compensate for the delay time of the horizontal synchronization signal separation circuit, the composite synchronization signal is passed through a delay circuit using a delay gate or an integration circuit to slightly delay the signal. 2. The television signal field identification circuit according to claim 1, wherein the television signal field identification circuit is used as an input to the first gate circuit after the signal is inputted.