JPS6351440B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization pull-in circuit that generates a signal synchronized with a horizontal synchronization signal separated from an NTSC television signal.

High-efficiency encoding devices for NTSC television signals use signals that are synchronized with the input television signal.

Conventionally, as a method of generating the above-mentioned signal, NTSC
The counter of the frequency divider circuit that divides the clock synchronized with the color burst signal of the television signal is set to a constant value using the horizontal synchronization signal separated from the NTSC television signal, and the phase is synchronized with the horizontal synchronization signal of the NTSC television signal. A method is used to generate a signal synchronized with the horizontal synchronization signal of the NTSC television signal. However, distortion and noise are added when the NTSC television signal passes through the transmission path, so
When the horizontal synchronization signal is separated from the NTSC television signal, distortion and noise are converted to distortion in the time axis direction, that is, jitter, and then appear in the separated horizontal synchronization signal. When a horizontal synchronization signal having this jitter component is input to a conventional synchronization generation circuit, jitter appears in the set signal of the counter that constitutes the frequency dividing circuit generated by the horizontal synchronization signal, and the period of the output of the synchronization signal generation circuit is It has the disadvantage that it causes confusion.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization pull-in circuit for eliminating the above-mentioned drawbacks of the prior art.

In this invention, the phase difference between the NTSC television horizontal synchronization signal and the signal generated from the frequency dividing circuit is detected,
When the phase difference is below a certain value and the frequency with which the relationship satisfying the above conditions is established is above a certain value, the set signal of a counter constituting a frequency dividing circuit that divides the frequency of the clock is inhibited.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In the figure, parallel bit signals pass through thick lines, and serial bit signals pass through thin lines.

In the figure, a horizontal synchronizing signal separated from the NTSC television signal is input to terminal a, and the differential circuit 1
If an edge portion is detected in , and there is jitter in the input horizontal synchronizing signal, timing signals b1 to b5 in FIG. 2 are output. A clock d synchronized with the color burst signal of the NTSC television signal is input to a frequency divider 3, where the frequency is divided into the period of the horizontal synchronizing signal. A pulse generator 5 generates a signal c having a clock pulse width T from the output of the frequency divider 3. In this embodiment, the clock pulse width T is set to three times the clock width. Counter 4 divides the output of frequency divider 3 into 16
The clear pulse e of the counter 8 and the write pulse e of the memory circuit 7 are output. Counter 8
A signal g, which is the result of the logical product of the output b of the differentiating circuit and the output c of the pulse generator 5, is input from the AND gate 6, and the counting result of the signal g is calculated in response to the write pulse e. The data is written into the memory circuit 7. Further, the contents of the counter 8 are cleared by the output signal e of the counter 4, and the output of the counter 8 is read into the memory circuit 7. This memory circuit 7
The output signal is input to the NAND gate 2 together with the output b of the differentiating circuit 1 and the output c of the pulse generator 5.

Next, the operation of the circuit of the present invention will be explained with reference to FIG. If there is jitter in the horizontal synchronizing signal separated from the NTSC television signal, jitter will also occur in the output b of the differentiating circuit 1. From this jitter, the differential circuit 1
Possible outputs are shown in b1 to b5.

The output signal from memory circuit 7 is HIGH
When the other two inputs of the NAND game 2 are not inhibited by the level, the output c of the pulse generator 5 and the output b of the differentiating circuit 1 are c and b1 or b shown in FIG.
2 or b3, the output of the NAND gate 2, which is the set signal for the frequency divider 3, is constant and the frequency divider circuit 3 is not set. When the output of the differentiating circuit 1 is in phase b4 or b5 shown in FIG. The output b has the relationship between c and b1 in FIG.

Next, when the phase relationship between the output b of the differentiating circuit 1 and the output c of the pulse generator 5 is the relationship between b4 or b5 and c in FIG. 2, the output of the AND gate 6 is
This becomes g1 or g2 shown in FIG. 2, respectively. This output signal is input to a counter 8 and counted in an AND gate 6 during the period specified by the counter 4. The count result of this counter 8 is taken into the memory circuit 7 in response to the signal e. A memory circuit 7 consisting of a plurality of flip-flops (not shown) has a memory circuit 7 which stores an AND signal if the count value output from the counter 8 is 7 or less, that is, within the time counted by the counter 4.
A pattern detector (not shown) consisting of at least one AND gate is provided to detect that the probability of output generation from the gate 6 is 1/2 or less, and when the detection is performed, the memory circuit 7 An output is generated from the gate and inhibits the output of NAND gate 2.

As described above, when the horizontal synchronizing signal separated from the NTSC television signal contains a jitter component, the present invention is capable of separating even if a signal having jitter within the pulse width T of the output signal c of the pulse generator 5 is input. No set signal is input to the frequency generator 3. Also, signal c
Even if a signal having jitter with a pulse width T or more is input, if the proportion of horizontal synchronization signals input within the interval T is 1/2 or more, the frequency divider is activated by controlling the signal output of the memory circuit 7. Since the set signal of 3 is not generated, the frequency divider 3 can operate stably.

Note that the pulse width T of the output c of the pulse generator 5,
The count value of the counter 4 and the output judgment criteria of the memory circuit 7 are not limited to those of this embodiment.
Further, the phase difference determination circuit constituted by the NAND gate 2 and the AND gate 6 is not limited to this embodiment.

As mentioned above, the present invention contains a jitter component.
This has the effect of supplying stable output for NTSC television horizontal synchronization signals.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
Figures c to g2 show operational waveform diagrams of the present invention. In Figure 1, 1...differential circuit, 2...NAND
Gate, 3... Frequency divider, 4... Counter, 5... Pulse generator, 6... AND gate, 7... Memory circuit, 8...
Counter.

Claims (1)

[Claims] 1. Differentiating the horizontal synchronization signal of the television signal in a synchronization pull-in circuit that matches the phase of the synchronization signal obtained by dividing the frequency of a clock synchronized with the color burst signal of the television signal to the phase of the horizontal synchronization signal of the television signal. a NAND gate having first to third input terminals, the output of the differentiating circuit being input to the first input terminal; A frequency divider circuit that is reset by the output of the NAND gate, a first counting circuit that counts the output of the frequency divider circuit, and a frequency divider circuit that is connected to the frequency divider circuit before and after the frequency divider circuit is reset by the output of the frequency divider circuit. a pulse generator that supplies a low-level pulse to a second input terminal of the NAND gate for a period of five times or less the supplied clock width; and a second counting circuit that is reset by the output of the first counting circuit. , and a memory circuit that takes in the output of the second counting circuit at the cycle of the output of the first counting circuit and supplies the output to the third input terminal of the NAND gate. retraction circuit.