JPH066835A - Horizontal frequency measurement circuit - Google Patents

Abstract

PURPOSE:To measure automatically a horizontal frequency of various video signals with different specifications such as a vertical frequency, a horizontal frequency and the presence of an equalization pulse without revision of a circuit parameter. CONSTITUTION:A counter 13 measures a time between adjacent leading times or trailing times in a synchronizing signal in a composite video signal and number of times of appearance of the same count in each count by the counter 13 is stored in a RAM 15 and the result of count when the number of times of appearance reaches a prescribed value or over is outputted as a measurement result D4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for measuring the horizontal frequency of an input composite sync signal or a composite video signal to which the composite sync signal is added.

[0002]

2. Description of the Related Art In a multi-input type video equipment, etc., it is necessary to switch the internal circuit of the equipment according to the horizontal frequency of the input video signal. Is used.

As such a horizontal frequency measuring circuit,
Generally, a method of measuring the time between two adjacent horizontal synchronizing pulses or counting the number of horizontal synchronizing pulses input within a certain period to calculate the horizontal frequency is adopted.

By the way, no matter which method is adopted, when the input signal is a television composite video signal, 1/2 of the vertical synchronizing signal in the vertical blanking period is provided around the input signal.
Since there are equalizing pulses of H periods and there are no horizontal sync pulses in the vertical sync signal periods, measuring the horizontal frequency during these periods will give erroneous results.

Therefore, conventionally, in the former method, as shown in FIG. 5, the gate pulse generating circuit 41 triggered by the vertical synchronizing signal is used to shift the vertical blanking period and the periphery of the vertical synchronizing signal within this period. A gate pulse to be covered is generated, and the count enable signal which is generated from the composite synchronizing signal CS by the flip-flop 42 and becomes high over the horizontal synchronizing period (1H) is prohibited only during the period of the gate pulse. In the latter method shown in FIG. 6, the gate pulse creating circuit 51 creates a gate pulse similar to the above, and the operation of the timer circuit 52 that enables the counter 53 for a certain period is prohibited only during the period of the gate pulse. I am trying to do it.

Incidentally, in FIGS. 5 and 6, 46 and 5
A latch circuit 5 latches the count results of the counters 44 and 53, respectively.

[0007]

In each of the above-mentioned conventional examples, since the above-mentioned gate pulse is created from the vertical synchronizing signal, this gate pulse can cover the equalizing pulse existing immediately before the vertical synchronizing signal. In order to do so, the start timing of the gate pulse for the next vertical synchronizing signal portion must be determined with the current vertical synchronizing signal as a reference, and therefore the vertical period must be known in advance.

This means that for video signals having different specifications such as vertical frequency, horizontal frequency, and presence / absence of equalization pulse, a gate pulse generation circuit or circuit parameter switching having circuit parameters suitable for each is provided. This means that a gate pulse generating circuit, which requires a circuit and whose circuit parameters are fixed, can support only one type of video signal.

Further, since the gate pulse is generated from the vertical synchronizing signal, the horizontal frequency measuring circuit has a drawback that the vertical synchronizing signal must be separated from the composite video signal in advance.

Therefore, an object of the present invention is to provide a horizontal frequency measuring circuit which eliminates the above-mentioned drawbacks.

[0011]

SUMMARY OF THE INVENTION According to the present invention, the time between adjacent rising or falling edges of a sync signal in a composite video signal is measured a plurality of times within a fixed time, and a predetermined value among the measured values of the plurality of times is determined. The horizontal frequency of the input composite video signal is calculated from the measured value equal to or higher than the appearance frequency.

[0012]

According to the present invention, the above measured values are different in the vertical blanking period and in other video signal periods, but the appearance frequency of the measured values in the video signal period is within the vertical blanking period. Since the measured value in this video signal period is a normal value, the horizontal frequency is correctly calculated based on this.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention shown in FIG.
This will be described with reference to the time chart of FIG. In addition,
2 shows a time chart during the measurement operation, and FIG. 3 shows a time chart at the end of the counting operation.

In FIG. 1, a clock pulse CK set to a frequency sufficiently higher than the horizontal frequency and a composite sync signal CS separated by a comparator 11 from a composite video signal are input to the circuit 12 in consideration of measurement accuracy. It is a timing controller. The controller 11 obtains both of the pulses CK and CS and repeats a high and a low at each falling edge of the composite synchronizing signal CS.
To the first counter 13, and this counter 13 counts the clock CK during that period.

The output of the first counter 13 is set to 3 by the latch pulse L1 output from the timing controller 12 in synchronization with the fall of the enable signal CE.
It is latched by the first latch circuit 14 in the state. Then, the latched count result is given as the address data DA of the next RAM 15.

The RAM 15 is for storing how many times the same count value of the first counter 13 appears, and when the count result of the first counter 13 is given,
RAM 15 corresponding to the address indicated by the count result
The data inside (the data of each address is all 0 at first) is read and given to the next adder 16, and the data is incremented by 1. Therefore, the first counter 1
When the first counting operation of 3 is completed, the RAM
The data D1 read from 15 is 0, and in response to this, the data D2 of the adder 16 becomes 1.

The data D2 of the adder 16 is latched at the timing of the latch pulse L2 in the second latch circuit 17 of three states, and then as the data D3 of the R.
It is fed back to AM15 and written at the same address as before. In order to perform such an operation, the RAM 15
Is in the read state during the low level period of the enable signal E2 and is in the write state during the low level period of the write control signal WR. Also, the second latch circuit 17 is in a high impedance state when reading the RAM 15, and the enable signal E3 is output so as to output the data D3 when writing the RAM 15.
Is controlled by.

In this way, while the data D3 from the second latch circuit 17 is being rewritten in the RAM 15, the data D2 from the adder 16 is input to the comparison circuit 18 to set a preset threshold value. When the data D2 is compared with SH and the data D2 becomes larger than the threshold value SH, a horizontal frequency measurement end signal CO is output, and this signal CO is given as a latch pulse of the third latch circuit 19.

In the third latch circuit 19, the count value of the first counter 13 latched by the first latch circuit 14 at the rising timing of the end signal CO (see FIG. 3), that is, the composite synchronizing signal CS (see FIG. 2). The number of counts of the clock pulse CK from the falling edge of (see) to the next falling edge is output as the horizontal period count result D4.

On the other hand, the end signal CO from the comparison circuit 18 is given to the timing controller 12. Then, the controller 12 sends the end signal C
When O is input, the reset signal RS is output and the first counter 13 is reset during the low level period of the count enable signal CE. Also, this controller 12
By setting the enable signals E1 and E3 to the high level at the rising timing of the end signal CO,
The second latch circuits 14 and 17 are reset and RA
Return M to initial write state.

When the data D4 is obtained from the third latch circuit 19 in this manner, the above circuits are reset to complete the horizontal frequency measurement. The data D4 indicates the number of clocks in one horizontal period. Therefore, the horizontal frequency is calculated from the number of clocks by the arithmetic circuit (not shown) at the next stage, but since this point is already well known, further description will be omitted.

Now, assuming that the odd field composite video signal shown in A of FIG. 4 is input to the embodiment of FIG. 1,
In the first to ninth H periods within the vertical blanking period,
Due to the cut pulse of the vertical synchronizing signal and the equalizing pulses before and after the vertical synchronizing signal, the period from the fall of each pulse to the next fall is approximately 1 / 2H, which is within the vertical blanking period. It is just 1H in the 10th to 20th periods and the video signal period. The composite sync signal separated from this composite video signal becomes as shown by B in the figure, and the first counter 13 created from this composite sync signal.
The count enable signal CE is as shown by C in FIG.

Therefore, the above-mentioned composite video signal is a normal NTSC, which is not affected by noise or level fluctuation.
If it is a signal, the data written in the address corresponding to the count value of the 1 / 2H period of the RAM 15 of FIG. 1 is 9, and the data written in the address corresponding to the count value of the 1H period is (263-9 ) / 2 = 127.

Therefore, if the value of the threshold value SH given to the comparison circuit 18 is set to, for example, 120 in consideration of the influence of the above-mentioned noise and level fluctuation, the value is added just before the end of the odd field of the composite video signal. The data D2 from the device 16 exceeds the threshold value 120, and at this time, the count result DA of the first counter 13 latched by the first latch circuit 14 is derived from the third latch circuit 19 as the output data D4,
The measurement will be completed.

[0025]

According to the present invention, switching of circuit parameters or the like is not required at all for video signal inputs having different specifications such as vertical frequency, horizontal frequency, and presence / absence of equalizing pulse.
Can respond automatically. Further, since the horizontal frequency can be measured only by the composite sync signal, the vertical sync separation circuit is not required separately, and the circuit scale can be reduced. Further, since all the circuits can be configured by digital circuits, there are advantages that they are highly reliable and can be easily integrated into an IC.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a time chart during the measurement operation.

FIG. 3 is a diagram showing a time chart at the end of the measurement operation.

FIG. 4 is a diagram showing an input composite video signal and a signal generated therefrom.

FIG. 5 is a block diagram showing an example of a conventional horizontal frequency measuring circuit.

FIG. 6 is a block diagram showing another example of a conventional horizontal frequency measuring circuit.

[Explanation of symbols]

 CK clock pulse CS composite sync signal CE count enable signal SH threshold D4 output data

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuaki Uwa 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. A circuit for measuring the horizontal frequency of an input composite video signal, the counter measuring the time between adjacent rising or falling edges of a sync signal in the composite video signal, and this counter. A horizontal frequency having a circuit for accumulating the number of appearances of the same count value among the respective count results, and a circuit for deriving the count value as a measurement output when the accumulated number of appearances exceeds a predetermined value. Measurement circuit.