JP3203667B2 - Vertical synchronization processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronization processing circuit used for a monitor receiver or the like.

[0002]

2. Description of the Related Art In a vertical synchronization processing circuit used in a monitor receiver or the like, an apparatus has been proposed which counts a horizontal synchronization signal and generates a vertical synchronization timing signal or the like from the counted value (countdown processing). However, conventionally proposed devices have been constituted by so-called hard logic.

FIG. 7 shows the structure of a conventional apparatus. In this figure, a vertical synchronizing signal supplied to an input terminal 61 is supplied to a reset terminal of a counter 63 through an input inhibit gate 62. A clock signal synchronized with the horizontal synchronizing signal is supplied from a terminal 64 to the counter 63 and counted. When the counted value reaches a predetermined value, for example, a timing signal of vertical deflection is taken out to the output terminal 65. Further, the counted value is supplied to the window setting logic circuit 66, a detection window for the vertical synchronization signal is formed and supplied to the input inhibition gate 62. When the vertical synchronization signal is not detected during the period of the detection window, A reset signal corresponding to the end of the period of the detection window is supplied from the logic circuit 66 to the reset terminal of the counter 63.

However, in such an apparatus, only one to three kinds of detection windows can be provided in a hard logic configuration in a fixed range. On the other hand, this detection window has to consider non-standard signals such as variable-speed reproduction of the VTR, and cannot be made too narrow. Therefore, there is a high possibility that noise or the like which is erroneously detected as the vertical synchronization signal in the detection window is generated, and the erroneous detection may cause a malfunction or the like.

In the above-described apparatus, when the vertical synchronizing signal is not detected, the counter 63 is reset at the end of the detection window, and the vertical synchronizing signal is interpolated by this reset. Therefore, jitter occurs due to this interpolation. Furthermore, since the distribution of the vertical synchronization signal differs depending on the input signal, the distribution is not always at the center of the detection window. Therefore, the amount of jitter differs between the case where the distribution is in the first half of the detection window and the case where the distribution is in the second half.

[0006]

The problems to be solved are that the vertical synchronization processing circuit constituted by the conventional hard logic cannot reduce the width of the detection window, so that the noise immunity and the jitter with respect to the non-standard signal are reduced. And the like, there is a limit to the stability performance.

[0007]

According to the present invention, when a vertical synchronizing signal included in a supplied video signal is detected,
Generates a timing pulse for vertical deflection synchronized with the vertical synchronization signal.If no vertical synchronization signal is detected, the timing pulse for vertical deflection synchronized with the vertical synchronization signal interpolated with the missing vertical synchronization signal is generated. In the vertical synchronization processing circuit for generating, the vertical synchronization processing circuit is operated in a standard mode in which the cycle of the vertical synchronization signal of the video signal is determined to be a predetermined one, or the cycle of the vertical synchronization signal of the video signal is The count value is reset to an initial value in the vertical cycle in order to operate in either the non-standard mode determined to be not the predetermined one or the no-signal mode determined to be no signal. Also, after the operation mode of the vertical synchronization processing circuit is set to the non-standard mode, software that is repeatedly started at a cycle of an integer multiple of the horizontal frequency is used. A first procedure (step [1]) for determining whether at least a vertical synchronization signal of the video signal is detected, and detecting the vertical synchronization signal of the video signal in the first procedure. If not, the operation mode of the vertical synchronization processing circuit is the standard mode, the non-standard mode, or
In a second procedure (step [2]) for determining whether the mode is the no-signal mode, and when the operation mode of the vertical synchronization processing circuit is determined to be the standard mode in the second procedure, The numerical value is compared with a predetermined set value corresponding to the number of times the software is started within one vertical cycle, and if the count value is equal to or more than the predetermined set value, the count value is written into the memory. A third procedure (steps [3] to [5]) in which the count value is incremented by a fixed value if not, and then written into the memory;
When the operation mode of the vertical synchronization processing circuit is determined to be the non-standard mode in the above procedure, the count value is compared with an upper limit value of a window indicating a period for detecting a vertical synchronization signal, and the count value is If the count value is equal to or more than the upper limit of the window, the count value is written to the memory and reset. Otherwise, the count value is incremented by a constant value and then written to the memory. Step [6] ~
[8]), when the operation mode of the vertical synchronization processing circuit is determined to be the no-signal mode in the second procedure, the count value is compared with the predetermined set value, and the count value If the value is equal to or more than the predetermined set value, the count value is written into the memory and reset. Otherwise, the count value is incremented by a constant value and then written into the memory. (Step

[9] to [11]) and when the vertical synchronization signal of the video signal is detected in the first procedure, the operation mode of the vertical synchronization processing circuit is the standard mode or the non-standard mode. A sixth procedure (step [12]) for determining whether the mode is the mode or the no-signal mode, and determining that the operation mode of the vertical synchronization processing circuit is the standard mode in the sixth procedure. In the case where the count value is equal to the predetermined set value, the count value is written to a memory and reset if the count value is equal to the predetermined set value. Otherwise, the count value is reset. Is incremented by a constant value, and then written to the memory (steps [13] to [15]). In the sixth step, the operation mode of the vertical synchronization processing circuit is the non-standard mode. If determined, Compare the count value with the lower limit of the window, if the count value is smaller than the lower limit of the window, after increasing the count value by a certain value, write to the memory, otherwise, An eighth procedure of updating the window according to the current count value and the plurality of maximum values and minimum values written to the memory, writing the count value to the memory, and then resetting the window (step [ 16] to [20])
And when the operation mode of the vertical synchronization processing circuit is determined to be the no-signal mode in the sixth procedure, the ninth procedure (step [ 21)), and in the eighth procedure, when it is determined that the count value is equal to or more than the predetermined value a predetermined number of times, the tenth procedure (step 10) is to set the operation mode of the vertical synchronization processing circuit to the standard mode. Step [19] and paragraph number [0023]), and when the fourth step determines that the count value is equal to or greater than the upper limit of the window a predetermined number of times, the operation of the vertical synchronization processing circuit is performed. Storage means for storing software including an eleventh procedure for setting the mode to the no-signal mode (described in step [8] and paragraph number [0017]); and the software stored in the memory. A vertical synchronization processing circuit for running E A and a computing means for generating timing pulses for the vertical deflection.

[0008]

According to this, the count value when the vertical synchronizing signal is detected is stored and the detection window is formed from these stored values, so that the detection window can be sufficiently applied to a non-standard signal or the like. A narrowed detection window can be formed, and good vertical synchronization processing can be performed with a simple configuration.

[0009]

FIG. 1 shows an example of hardware for realizing a vertical synchronization processing circuit. In the figure, a timing signal of twice the horizontal frequency (2f _H ) and a clock signal of, for example, 4 MHz are supplied to an instruction address generator 1. The address generated by the generator 1 is supplied to an instruction (I) ROM and a RAM 2,
The signals generated by the ROM and the RAM 2 are supplied to the ROM 3 and the RAM 4 for data and to the instruction decoder 5. Further, data from the ROM 3 and the RAM 4 is supplied to the ALU 6, and the output of the ALU 6 is fed back to the ROM 3 and the RAM 4 and the ALU 6 via an accumulator (ACC) 7. The operation of the ALU 6 and the accumulator 7 is controlled by the instruction decoder 5.
Controlled by a signal from Further, the signal from the accumulator 7 and the vertical synchronizing signal are supplied to a jump instruction generator 8, and the jump instruction from the generator 8 is supplied to the instruction address generator 1. In this circuit, a software operation shown in a flowchart described later is performed, and the operation result is taken out to the registers 9 and 10.

FIG. 2 shows a flowchart of an example of the software stored in the above-mentioned instruction (I) ROM and RAM 2. In this figure, this software is started (started) at a cycle twice (2f _H ) the horizontal frequency. When it is started, it is first determined in step [1] whether or not a vertical synchronizing signal has been detected . Here, the vertical synchronization signal is not detected (N
O) In step [2], the standard / non-standard / no signal mode is determined. This step [2] is determined by a flag described later.

In the standard mode in step [2], the count value (X) is set to a predetermined value (Tstm) in step [3].
It is determined whether or not X ≧ Tstm. If X ≧ Tstm is not satisfied (NO), the count value (X) is incremented by 1 in step [4], and X ≧ Tstm is satisfied (YE
At S), the count value (X) is reset to 0 in step [5]. Thereafter, the flowchart is stopped.

In the non-standard mode in step [2], it is determined in step [6] whether the count value (X) satisfies X ≧ Wmax with respect to an upper limit value (Wmax) of a detection window described later. Is determined. And X ≧ Wmax is not satisfied (NO)
In this case, the count value (X) is incremented by 1 in step [7].
If X ≧ Wmax (YES), the count value (X) is reset to 0 in step [8]. Thereafter, the flowchart is stopped.

Further, when the signal is in the no-signal mode in step [2], the step

In [9], the count value (X) becomes a predetermined value (Tstm
), It is determined whether or not X ≧ Tstm.
If X ≧ Tstm is not satisfied (NO), step [1]
In [0], the count value (X) is incremented by 1. If X ≧ Tstm is satisfied (YES), the count value (X) is reset to 0 in step [11]. Thereafter, the flowchart is stopped.

On the other hand, in step [1], a vertical synchronizing signal is detected.
When the mode is issued (YES), the standard / non-standard / no signal mode is determined in step [12] in the same manner as in step [2] described above. When the mode is the standard mode in step [12], it is determined in step [13] whether or not X = Tstm between the count value (X) and the predetermined value (Tstm). When X = Tstm is not satisfied (NO), the count value (X) is incremented by 1 in step [14], and when X = Tstm (YES), the count value (X) is determined in step [15].
Is reset to 0. Thereafter, the flowchart is stopped.

If the mode is the non-standard mode in step [12], it is determined in step [16] whether the count value (X) satisfies X <Wmin with respect to a lower limit value (Wmin) of a detection window described later. Is determined. And X <Wmin (Y
ES), the count value (X) is incremented by 1 in step [17]. On the other hand, in step [16], X <Wmin
If not (NO), the system whose vertical frequency is 50/60 Hz is determined from the count value (X) at that time in step [18], the detection window is updated in step [19], and the detection window is updated in step [20]. The count value (X) is reset to zero. Thereafter, the flowchart is stopped.

Further, if the mode is the no-signal mode in step [12], the mode flag is set to the non-standard mode in step [21], and the count value (X) is set to X> 1 in step [22].
It is determined whether it is 00 or not. If X> 100 is not satisfied (NO), the count value (X) is incremented by 1 in step [23], and if X> 100 (YES), the count value (X) is reduced to 0 in step [24]. Reset. Thereafter, the flowchart is stopped.
The above software is, for example, twice the horizontal frequency (2
repeated in a cycle of f _H) is activated (start).

In the initial state, the count value (X) is set to an initial value of 0, and the mode flag is set to the non-standard mode. This allows the above flow chart to:
In the initial state, steps [1] → [2] → [6] → [7]
Or driven through [8] and twice the horizontal frequency (2
count in a cycle of f _H) (X) is incremented by 1. Thus, for example, the detection of the vertical synchronizing signal is not determined in step [1], and when this count value (X) exceeds the upper limit value (Wmax) of the detection window, the count value (X) is reset to 0. Is done. If this reset is performed, for example, three times in succession, the mode flag is set to the no-signal mode. Thus, the flowchart is changed from step [1] → [2] →

It is driven through [9] → [10] or [11], and the count value (X) is added one by one at a cycle of twice the horizontal frequency (2f _H ), and the value of 0 → Tstm is repeated.

On the other hand, if the detection of the vertical synchronizing signal is determined in the step [1] in the non-standard mode, the flow chart shows the steps [1] → [12] → [16] → [1]
7] or [18] → [19] → [20]. Here, in the initial state, step [16] is X <W
Step [1] while the value is still min (YES)
In step no longer determines the detection of the vertical synchronization signal [1] → [2] →

The drive is returned to the drive through [9] → [10] or [11], and while these are repeated, the drive is pulled in step [16] so that X <Wmin is not satisfied (NO).

In this state, in step [18], a system determination of 50/60 Hz of the vertical frequency is performed. The determination is performed when this state is repeated, for example, four times. When the average value of the count value (X) during this period is approximately 625, 50H is determined.
When z is approximately 525, it is determined to be 60 Hz. Thus, for example, the value of Tstm is set to 625 at 50 Hz and 525 at 60 Hz, respectively.

In this state, the detection window is updated in step [19]. This update is also performed when this state is repeated, for example, four times. The maximum value and the minimum value of the count value (X) during this time are each added with a predetermined margin to obtain the upper limit value (Wmax) of the detection window.
) And the lower limit (Wmin).

That is, FIG. 3 shows a flowchart relating to the update of the detection window in more detail.
In this figure, when the software is started, the count value (X) is incremented by 1 in step [31]. Next, in step [32], it is determined whether or not a vertical synchronization signal has been detected . If a vertical synchronization signal is detected (YES), it is determined in step [33] whether or not the count value (X) is within the detection window. If it is within the detection window (YES), the count value (X) is stored in the memory at step [34], and the detection window updated from the stored count value (X) at step [35] is calculated. Is done. Further, in step [36], the count value (X) is reset to zero. Thereafter, the flowchart is stopped. When the count value (X) is not in the detection window (NO) in step [33], this flowchart is stopped (stopped).

On the other hand, when the vertical synchronizing signal is not detected in step [32] (NO), step [3]
7], it is determined whether or not the count value (X) is larger than the detection window. Here, it is larger than the detection window (YE
In step S), it is determined in step [38] whether or not there is a vertical synchronization signal outside the detection window. If there is a vertical synchronizing signal (YES), the detection window is expanded in the direction in which the vertical synchronizing signal exists in step [39], and the count value (X) is reset to 0 in step [36]. Thereafter, the flowchart is stopped. If there is no vertical synchronization signal in step [38] (NO), the count value (X) is obtained in step [36].
Is reset to 0, and thereafter, this flowchart is stopped (stopped). If the count value (X) is not larger than the detection window (NO) in step [37], this flowchart is stopped (stopped).

FIG. 4 also shows a flowchart for calculating the detection window to be updated. In this figure, the value of T _4, which is stored in step [41] is rewritten to T _3, the value of T ₃ is rewritten to T _2, the value of T ₂ is rewritten to T _1, T ₁ Is rewritten to X. Therefore, the past four count values (X) are stored in T _{4 to} T ₁ . Then, at step [42], T
₄ Maximum value Tmax of the through T ₁ is determined, the Wmax = Tmax + α α margin is calculated. It prompted further minimum value Tmin of T ₄ through T ₁ at step [43], the Wmin = Tmin-beta beta margin is calculated. Note that the upper limit of the detection window (Wmax)
And the lower limit (Wmin) has a sufficiently large width including 625 and 525, and is reset to the initial value when the mode flag is changed to the non-standard mode. Further, the above-mentioned maximum value Tmax and minimum value T
When the values of min are both substantially Tstm and the difference is equal to or less than a predetermined value, the mode flag is set to the standard mode.

In the standard mode, normally, steps [1] → [2] → [3] → [4], and the vertical synchronizing signal is detected.
When it is done, step [1] → [12] → [13] →
It is driven through [14] or [15]. As a result, the count value (X) is incremented by one at a cycle of twice the horizontal frequency (2f _H ), reset to 0 when X = Tstm, and the value of 0 → Tstm is repeated. On the other hand, when the vertical synchronizing signal cannot be obtained, when X = Tstm in step [3], the count value (X) is reset to 0 in step [5], and 0 → Tstm. The value is repeated. Therefore, in the standard mode, the count value (X) is always added one by one at a cycle of twice the horizontal frequency (2f _H ), and is reset to 0 when X = Tstm.
The value of m is repeated. Further, if the state in which the count value (X) is reset to 0 in step [5] is repeated, for example, eight times consecutively, the mode flag is set to the non-standard mode.

Therefore, in this flowchart, the count value (X) indicates that the vertical synchronization signal is detected in the standard mode .
Is reset to 0 at the time of X = Tstm, and
Even if the vertical synchronizing signal is lost, it is reset to 0 at the time of X = Tstm as long as the loss is not continued eight times or more. As a result, the missing vertical synchronizing signal is interpolated.

That is, in the standard mode, the count value (X) is changed as shown in FIG. 5B with respect to the input vertical synchronizing signal as shown in FIG. Therefore, this count value (X)
When a timing pulse for vertical deflection is formed in a period where is equal to or larger than a predetermined value a and equal to or smaller than a value b, the timing pulse becomes as shown in C of FIG. On the other hand, if the input vertical synchronizing signal is missing as shown in D of the figure, the count value (X) is changed as shown in E of the figure. Here, the count value (X) has the same change regardless of the lack of the input vertical synchronization signal.

Therefore, a timing pulse for vertical deflection is formed during a period in which the count value (X) is equal to or more than a predetermined value a and equal to or less than a value b.
As shown in (1), the missing vertical synchronizing signal is interpolated. Since the interpolated vertical synchronizing signal has the same change regardless of the lack of the input vertical synchronizing signal, the count value (X) is formed at exactly the same timing as the original position, thereby eliminating jitter and the like. The vertical synchronization signal is interpolated.

In the non-standard mode, as shown in FIG. 6A, the width of the detection window is increased at the initial value, and the vertical synchronization signal as shown in B of FIG. Then, according to the maximum value Tmax and the minimum value Tmin of the count value (X) at this time, the detection window is changed to a width obtained by adding predetermined margins α and β to this value as shown in C of FIG. You. As a result, the width of the detection window is large in the initial value, and the vertical synchronization signal can be determined (pulled in) quickly. After the vertical synchronization signal is pulled in, the width of the detection window is narrowed. Near noise and the like can be removed.

Further, when the interval between the vertical synchronizing signals is gradually changing in the non-standard mode, the above-mentioned margin α,
If it is in the range of β, the detection window is changed accordingly, and the vertical synchronization signal can be discriminated well in the non-standard mode. When the phase of the vertical synchronization signal changes significantly, for example, the mode flag is temporarily set to the no-signal mode because the vertical synchronization signal is not determined in the detection window, and then the non-standard mode is determined by the determination of the vertical synchronization signal. As a result, the width of the detection window is reset to the initial value, and the determination (pull-in) of the vertical synchronization signal is quickly performed.

Thus, according to the above-described apparatus, the count value when the vertical synchronizing signal is detected is stored, and the detection window is formed from these stored values. Thus, it is possible to form the detected detection window and perform a good vertical synchronization process with a simple configuration.

That is, in the above-described apparatus, by performing the countdown processing by software, complicated condition judgment can be easily performed by a program. Therefore, for example, even if the synchronization signal is lost, it is possible to prevent the displacement of the screen position by interpolating from some past synchronization signals. In addition, by making the detection window width variable so that it becomes wider when the synchronization signal is pulled in and becomes narrower when the synchronization signal is stabilized, noise near the synchronization signal can be removed and jitter can be prevented. Further, since the system determination is also performed by the same processor as the above-described processing, there is no need to add logic for that purpose, and the chip area in the case of LSI is not increased.

In the above-described apparatus, the number of count values (X) stored for calculating the detection window may be more than four. Further, the calculation method is not limited to the method using the maximum value Tmax and the minimum value Tmin, but may be a method in which an average value is obtained and a predetermined margin is provided before and after the average value to form a detection window. Further, the margins α and β affect tracking performance and jitter performance, and are arbitrarily determined in consideration of them.

In the above-mentioned apparatus, the count value (X) corresponds to the absolute position in the vertical direction on the screen of the monitor receiver. Therefore, a vertical deflection waveform and a horizontal deflection width correction waveform are formed by calculation. If so, this count value (X)
Can be used as it is to perform the calculation. Also, the count value (X) in step [22] of the above-described flowchart>
In the determination of 100, the vertical synchronization signal is frequently determined by erroneous detection of noise or the like, and the vertical deflection width is reduced, thereby preventing the circuit from being overloaded.

[0034]

According to the present invention, a vertical synchronization signal is detected.
Since the count value at the time of the detection is stored and the detection window is formed from these stored values, it is possible to form a detection window which is sufficiently narrowed even for non-standard signals, etc. Vertical synchronization can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of hardware for realizing a vertical synchronization processing circuit of the present invention.

FIG. 2 is a flowchart illustrating an example of software for implementing a circuit;

FIG. 3 is a flowchart of a main part for explanation.

FIG. 4 is a flowchart of a main part for explanation.

FIG. 5 is a waveform diagram for explanation.

FIG. 6 is a waveform diagram for explanation.

FIG. 7 is a configuration diagram of a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction address generator 2 Instruction ROM and RAM 3 ROM for data 4 RAM for data 5 Instruction decoder 6 ALU 7 Accumulator 8 Generator of jump instruction 9 Register 10 Register

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yumiko Mito 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-2-121572 (JP, A) JP-A Sho JP-A-2-194774 (JP, A) JP-A-2-202778 (JP, A) JP-A-1-289377 (JP, A) JP-A-4-276984 (JP, A) A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (1)

(57) [Claims] When a vertical synchronization signal included in a supplied video signal is detected, a timing pulse for vertical deflection synchronized with the vertical synchronization signal is generated, and when a vertical synchronization signal is not detected, A vertical synchronization processing circuit for generating a timing pulse for vertical deflection synchronized with the vertical synchronization signal in which the missing vertical synchronization signal is interpolated, wherein the vertical synchronization processing circuit is provided with a period of the vertical synchronization signal of the video signal. Is the standard mode in which
In order to operate in either the non-standard mode in which the cycle of the vertical synchronizing signal of the video signal is determined not to be a predetermined one or the no-signal mode in which it is determined that there is no signal, the vertical cycle Software that is repeatedly started at a cycle of an integral multiple of the horizontal frequency after the count value is reset to an initial value and the operation mode of the vertical synchronization processing circuit is set to the non-standard mode, and
A first procedure for determining whether or not a vertical synchronization signal of the video signal has been detected; and a vertical synchronization processing circuit in a case where the vertical synchronization signal of the video signal has not been detected in the first procedure. A second procedure for determining whether the operation mode is the standard mode, the non-standard mode, or the no-signal mode; and When it is determined that the operation mode is the standard mode, the count value is compared with a predetermined set value corresponding to the number of times the software is started within one vertical cycle, and the count value is set to the predetermined set value. If the above is the case, the above-mentioned count value is written into the memory, and then reset. Otherwise, the above-mentioned count value is incremented by a constant value and then written into the memory. procedure When it is determined that the operation mode of the vertical synchronization processing circuit is the non-standard mode, the count value is compared with an upper limit value of a window indicating a period for detecting a vertical synchronization signal, and the count value is determined based on the window. If the count value is equal to or more than the upper limit value, the count value is written to the memory, and then reset. Otherwise, the count value is incremented by a constant value and then written to the memory. When it is determined in step 2 that the operation mode of the vertical synchronization processing circuit is the no-signal mode, the count value is compared with the predetermined set value, and if the count value is equal to or greater than the predetermined set value, In a certain case, the above-mentioned count value is written into the memory, and then reset. Otherwise, the above-mentioned count value is incremented by a constant value and then written into the memory. Drop of above video signal In the case where a direct synchronization signal is detected, a sixth operation is performed to determine whether the operation mode of the vertical synchronization processing circuit is the standard mode, the non-standard mode, or the non-signal mode. And when the operation mode of the vertical synchronization processing circuit is determined to be the standard mode in the sixth procedure, the count value is equal to the predetermined set value as compared with the predetermined set value. In this case, the above-mentioned count value is written into the memory, and then reset. Otherwise, the above-mentioned count value is incremented by a constant value, and then written into the memory. When it is determined that the operation mode of the vertical synchronization processing circuit is the non-standard mode, the count value is compared with the lower limit value of the window, and if the count value is smaller than the lower limit value of the window, After incrementing the numerical value by a constant value, the value is written to the memory. Otherwise, the window is updated according to the current count value and the plurality of maximum values and the minimum values written to the memory. After writing the count value to memory,
Eighth procedure for resetting, and setting the operation mode of the vertical synchronization processing circuit to the non-standard mode when it is determined in the sixth procedure that the operation mode of the vertical synchronization processing circuit is the no-signal mode. 9
And a tenth procedure for setting the operation mode of the vertical synchronization processing circuit to the standard mode when it is determined that the count value is equal to or more than the predetermined value in the eighth procedure for a predetermined number of times. If it is determined in the fourth procedure that the count value is equal to or larger than the upper limit value of the window for a predetermined number of times, the operation mode of the vertical synchronization processing circuit is set to a no-signal mode.
A vertical synchronization processing circuit comprising: a storage unit storing software including the steps of: and a calculation unit configured to execute the software stored in the memory to generate the timing pulse for vertical deflection.