KR0182002B1 - Digitalized pal/mesecam discriminator circuit - Google Patents

Abstract

The present invention discloses a digital arm / mecam (P / M) discrimination circuit. Vertical synchronization with P / M signal output from analog P / M discrimination circuit with 1H period in arm mode PM and 2H period in mechcam mode MM, and 1 field period and 1H period, respectively. The digital circuit for inputting the signal VS and the horizontal synchronizing signal HS and outputting the P / M discrimination signal in a digital form inputs HS and responds to the P / M signal at a first level signal or 2H. A first reset signal that outputs a pulse having a period of and a second counter signal according to each mode by inputting the output of the first counter, or when a predetermined number of output signals of the first counter are input, the reference reset signal is input to the first counter. The second counter outputs a signal of the first level until the level is reached, and VS is input in response to the HS, and the first level is 1H at the rear and front edge portions of the VS, and has a period of one field period. Means for outputting a reference reset signal and a reference clock signal, and a second count; Means for inputting the output of the digital signal and outputting a P / M discrimination signal which is a first level in PM and a first level in MM in response to a reference clock signal, and is resistant to noise to prevent malfunction of P / M discrimination. In addition, even if a malfunction occurs in the previous field, a stable discrimination operation can be realized because the discrimination result pulse is generated by inputting data at the beginning of the next field.

Description

Digital Arm / Messcam Discrimination Circuit

1 is a circuit diagram of a digital arm / meccam discrimination circuit according to the present invention.

2A to 2D are timing diagrams of respective parts of the first counter shown in FIG.

3a to f are timing diagrams at each terminal of the second counter shown in FIG.

4A to H are timing diagrams of respective terminals of the reference signal generator shown in FIG.

5A to 5F are timing diagrams for explaining the operation of the latch unit shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video tape recorder (VTR) or a camcorder (camcoder). In particular, when recording or playing back data in a VTR or camcorder, the color signal processing method is PAL (Phase Alternate Lines) method or The present invention relates to a digital arm / mescam discrimination circuit for discriminating the MESECAM (MESEquential Color And Memory) method of application on a digital basis in units of one field.

The arm method is a widely known method, and the mesekham method refers to a method of recording data by converting data from the SECAM method to the arm method.

The conventional arm / meccam discrimination circuit is composed of an analog method, and the analog arm / meccam discrimination circuit is 1H (Hsync: Horizontal synchronous) which is every 63.5uS when the determined method is the arm (PAL) method. It has a period, and outputs a high level pulse in a burst gate pulse (BGP) period. In the case of the mesemchem method, a pulse having a period of every 2H and a high level is also output in a BGP period. However, such a conventional analog arm / meccam circuit has a problem in that malfunctions occur in the determination of the arm / meccam method because it is easily affected by noise.

In addition, there is a problem that it is difficult to operate normally once a malfunction occurs because arm / mescam is not discriminated on a field basis.

It is an object of the present invention to digitally determine the arm / meccam method by one field unit so that a malfunction does not occur in the next field even if a malfunction occurs in the previous field in order to solve the conventional problems as described above. It is to provide a mesencam discrimination circuit.

In order to achieve the above object, a P / M signal output from an analog arm / meccam discrimination circuit having a period of H in the arm mode according to the present invention and a period of 2H in the mesecam mode, and one field period A digital arm / meccam discrimination circuit for inputting a vertical synchronizing signal having a period and a horizontal synchronizing signal having a period of 1H and outputting an arm / meccam discrimination signal in a digital form, inputs the horizontal synchronizing signal, First counting means for outputting a first level signal or a pulse having a period of 2H in response to the P / M signal, and an output of the first counting means for inputting a second level signal according to each mode. Second counting means for outputting or outputting a signal of a first level until a reference reset signal reaches a first level when a predetermined number of output signals of the first counting means are input; A reference for inputting the vertical synchronization signal and outputting the reference reset signal and the reference clock signal having the first level by the 1H and having a period of the first field period at the rear and front edge portions of the vertical synchronization signal, respectively. Inputting a signal generating means and an output of the second counting means, and outputting the arm / meccam discrimination signal of a first level in the arm mode and a first level in the mescam mode in response to the reference clock signal; It is preferable that it is comprised by a latch means.

Hereinafter, the configuration of the digital arm / meccam discrimination circuit according to the present invention will be described in detail with reference to FIG.

1 is a circuit diagram of a digital arm / meccam determination circuit according to the present invention, and includes a first counter 10, a second counter 20, a reference signal generator 30, and a latch unit 40. .

The first counter 10 shown in FIG. 1 inputs a horizontal synchronizing signal to the clock terminal CK through the input terminal IN1, and inputs an P / M: Pal / Mesecam signal to the input terminal IN2. The output of the first T flip-flop (f / f: flip / flop) 12 and the first T flip-flop 12, which are inputted to the clear terminal C, via the clock input, and the P / M signal is the clear input. 2T flip-flop 14 which outputs a fixed output to the 2nd counter 20. FIG.

The second counter 20 includes a first inverse logical product (NAND) 21 that inversely ANDs the output of the first counter 10 and its own output of the second counter 20, and the first inverted logical product ( 21T is the clock input, and the third T flip-flop 22 and the constant output of the third T flip-flop 22 which input the reference reset signal output from the reference signal generator 30 as the clear input are clock inputs. The fifth T flip-flop 23 whose clock output is the clock output and the fourth T flip-flop 23 whose reference reset signal is the clear input is used as the clock input, and the reference reset signal is the clear input. ), The 6T flip-flop 25 having the positive output of the 5T flip-flop 24 as the clock input, and the 6T flip-flop 25 having the reference reset signal as the clear input; The 7T flip-flop 26 outputting the sub-output to the first inversion logical product 21 and the latch unit 50 with the reference reset signal as a clear input. )

The reference signal generator 30 includes a first reference signal generator 43 and a second reference signal generator 44.

The first reference signal generator 43 inputs the first inverter 32 for inverting the vertical synchronization signal input through the input terminal IN3 and the output of the first inverter 32 to the data terminal D, and A first D flip-flop 37 for inputting a time-delayed horizontal synchronization signal to the clock terminal CK, second and third inverters 31 and 33 for delaying a predetermined time horizontal synchronization signal, and a second inverter 31. The fourth inverter 34 for inverting the output of the predetermined time and delaying the horizontal synchronizing signal and the signal output from the fourth inverter 34 are clock inputs, and the positive output of the first flip-flop 37 is performed. Second inverting logic for inverting AND outputting the 2D flip-flop 38 and the positive output of the 1D flip-flop 37 and the negative output of the 2D flip-flop 38 as a reference reset signal. The product 41 is comprised.

In addition, the second reference signal generator 44 inverts the signal output from the second inverter 31 again to output the vertical synchronization signal and the vertical synchronization signal to delay the predetermined time horizontal synchronization signal. A third D flip-flop 39 which is an input and outputs the fifth inverter 35 as a clock input, and an inverting signal output from the second inverter 31 to delay the horizontal synchronization signal for a predetermined time. 4D flip-flop 40 which uses the 6-inverter 36 and the positive output of the 3D flip-flop 39 as a data input, and uses the clock output as the signal output from the 6th inverter 36, and 3D And a third inversion logical product 42 which inverts and outputs the positive output of the flip-flop 39 and the sub-output of the 4D flip-flop 40 and outputs them as a reference clock signal.

The latch unit 50 is composed of a 5D flip-flop 50 which outputs the arm / mescam discrimination signal to the sub-output using the output of the second counter 20 as a data input and the reference clock signal as a clock input. .

Hereinafter, with reference to the attached timing diagrams of the operation of the digital arm / meccam determination circuit according to the present invention having the above-described configuration will be described as follows.

2a to 2d are timing diagrams of respective parts of the first counter 10 shown in FIG. 1, and FIG. 2a is a horizontal synchronization signal input through the input terminal IN1, and FIG. 2b is a P / in input through the input terminal IN2. 2C is a timing diagram of a signal outputted at the constant output of the first T flip-flop 12, and 2d is a timing diagram of a signal outputted at the constant output of the second T flip-flop 14, and (a) denotes an arm. The mode and (b) each show a mesechum mode. Here, the P / M signal shown in FIG. 2B is a high level pulse in the BGP period in any mode and low level in other periods.

First, the operation of the first counter 10 shown in FIG. 1 will be described.

The first T flip-flop 12 inputs a horizontal synchronization signal having a 1H period of 63.5 uS (15.75 KHz) shown in FIG. 2A and a P / M signal shown in FIG. 2B to perform a binary counting operation. The signal shown in FIG. 2C is output to the clock terminal of the second T flip-flop 14 through Q.

In detail for each mode, as shown in FIG. 2D, the second T flip-flop 14 continuously outputs only the low-level signal that is the initial state of the flip-flop in the arm mode, because the second T flip-flop ( The P / M signal shown in FIG. 2B is input to the clear terminal at the moment when the second T flip-flop 14 tries to perform the counting operation at the falling edge of the signal inputted to the clock terminal of FIG. Because it stops.

In the Messekam mode, the signal input to the clock terminal of the second T flip-flop 14 is a signal having a period of 2H, and the P / M signal having a period of 2H input to the clear terminal is the second T flip-flop 14. Even when the operation of reset is performed, since the constant output signal of the second T flip-flop 14 at that time is at the low level and is the same as the initial state, the first counter 10 realizes the operation as a ternary counter of the horizontal synchronization signal input.

3a to 3f are timing diagrams at each terminal of the second counter 20, and FIGS. 3a and 3b are the positive output of the second T flip-flop 14 and the negative output and seventh output of the 7T flip-flop 26 in the arm mode. 3c to 3f are the positive output of the second T flip-flop 14, the output of the second inverse logical product 41, the output of the first inverted logical product 21 and the negative portion of the 7T flip-flop 26 in mesekham mode. The timing chart of the output signal is indicated by reference numeral (c) for 16 pulses and (d) for one field period.

Next, when the operation of the second counter 20 is described for each mode, in the arm mode, the signal input to the first inversion logical product 21 of the second counter 20 is as shown in FIG. 3A. Similarly, since the signal is always at a low level, the constant output of the 7T flip-flop 26 is always at a high level as shown in FIG. 3B. In the case of the mesekham mode, when sixteen pulses of a signal having a period of 2H shown in FIG. 3C are input to the first inversion logical product 21, the seventh T flip-flop 26 shown in FIG. The sub output goes from a high level to a low level, which is input to the first inversion logical product 21 so that the output of the first inversion logical product 21 becomes a high level as shown in FIG. 3E. This is because the negative output of the 7T flip-flop 26 reaches the low level until the low level signal is applied to the clear terminal from the 3T flip-flop 22 to the 7T flip-flop 26. The second counter 20 continues to operate as a hexadecimal counter.

At this time, the signal output from the second inversion logical product 41 which transitions from the high level to the low level is a reference reset pulse which counts and detects an arm or mescam signal input for each field as one field period (262.5H). to be.

4a to 4h are timing diagrams of the respective terminals of the reference signal generator 30 in FIG. 1, and FIG. 4a is a horizontal synchronization signal input to the input terminal IN1, FIG. 4b is a vertical synchronization signal input to the input terminal IN3, 4c shows the positive output signal of the first D flip-flop 37, 4d shows the negative output signal of the second D flip-flop 38, 4e shows the output signal of the second inversion logical product 41, and 4f shows the third output. The positive output signal of the D flip-flop 39, 4g is a negative output signal of the 4D flip-flop 40, 4h is a timing diagram of the signal output from the third inversion logical product 42, and (e). Are 10H and (f) represents one field period, respectively.

Referring to the operation of the reference signal generator 30, the reference signal generator 30 inputs the horizontal synchronization signal shown in FIG. 4A and the vertical synchronization signal shown in FIG. 4B to generate one field reference signals. At this time, the pulse width at the edge portion of each field was made as small as 1H in width and used as the clear input of the second counter 20 and the clock input of the latch section 50. To this end, a signal that is the inverse of the vertical synchronization signal shown in FIG. 4B is input to the data input of the first D flip-flop 37 through the first inverter 32, and the clock terminal of the first D flip-flop 37 is input to the first terminal 32. The horizontal synchronizing signal shown in FIG. 4a delayed by the second and third inverters 31 and 33 is input so that the positive output signal of the 1D flip-flop 37 is inversely opposite to the vertical synchronizing signal as shown in FIG. 4c. Signal is delayed by 1H period and output. This delayed signal is directly input to the data input terminal D of the 2D flip-flop 38 so that the sub-output signal of the 2D flip-flop 38 shown in FIG. 4d is finally vertical as shown in FIG. 4b. The signal is delayed by 2H period compared to the synchronization signal. Then, the second inversion logical product 41 inputs the positive output signals of the first D flip-flop 37 and the sub output signals of the second D flip-flop 38 to the rear end of the vertical synchronization signal shown in FIG. 4E. The pulse of one field period which is low level by the width of 1H is output from the edge part.

Further, the 3D flip-flop 39 and the 4D flip-flop 40 are similar to the operations of the first D flip-flop 37 and the second D flip-flop 38, respectively, as shown in FIGS. 4F and 4G. Are output to the third inversion logical product 42, and the third inversion logical product 42 has a width of 1H at the front edge portion of the vertical synchronization signal and is shown in FIG. 4h of the low level one field period. The signal is output to the latch unit 50.

5a to 5f are timing diagrams for explaining the operation of the latch unit 50. FIG. 5a is an output signal of the second inversion logical product 41, and FIG. 5b is an output of the third inversion logical product 42. 5C and 5D show the sub-output of the 7T flip-flop 26 and the sub-output of the 5D flip-flop 52 (signal output through the output terminal OUT shown in FIG. 1) in the arm mode, 5e and 5f show the sub-output of the 7T flip-flop 26 and the sub-output signals of the 5D flip-flop 52 (signal output through the output terminal OUT shown in FIG. 1) in the mesekham mode. For each timing diagram, reference numeral g denotes a hexadecimal counting period, respectively.

Finally, when the operation of the latch unit 50 shown in FIG. 1 is described for each mode, in the arm mode, the signal shown in FIG. 5C and the signal shown in FIG. A low level signal shown in FIG. 5D is output to the negative output of the 5D flip-flop 52 through the output terminal OUT through the data terminal and the clock terminal of 52), respectively, and the clock of the 5D flip-flop 52 is output. When the signal shown in Fig. 5B input as an input is operated in one field period and continues in arm mode, a low level signal is output through the output terminal OUT. However, in the case of the mesekham mode, the signal shown in FIG. 5E input to the data input terminal D of the 5D flip-flop 52 is the clock terminal shown in FIG. 5B as the clock terminal of the flip-flop 52. Since it is low level at this falling edge, a high level signal is output to the output terminal OUT as shown in Fig. 5f. However, in the case of the message mode continuously after one field has elapsed, the output signal continues to maintain a high level.

As described above, the digital arm / meccam discrimination circuit according to the present invention improves the discrimination of the arm or methecam method in the field of signal system of the VTR or camcorder from the conventional analog method to the digital method. It is possible to realize stable discrimination operation by preventing malfunction of message discrimination and by constructing the system in units of 1 field and inputting data at the beginning of the next field to generate a pulse as a result of discrimination even if the system is malfunctioned in the previous field. There is.

Claims (7)

An arm / meccam signal outputted from an analog arm / meccam discrimination circuit having a period of H in the arm mode and a period of 2H in the mesekham mode, a vertical synchronization signal having a period of one field period, and A digital arm / meccam discrimination circuit for inputting a horizontal sync signal having a period of 1H and outputting an arm / meccam discrimination signal in a digital form, wherein the horizontal sync signal is inputted to the arm / meccam signal. First counting means in response to outputting a signal of a first level or a pulse having a period of 2H; Inputting the output of the first counting means to output a second level signal according to each mode, or when a predetermined number of output signals of the first counting means are input, the first level until the reference reset signal becomes the first level Second counting means for outputting a signal of; The reference reset signal and a reference clock input the vertical synchronization signal in response to the horizontal synchronization signal, and each of the first and second edge portions of the vertical synchronization signal is the first level by 1H and has a period of the one field period; Reference signal generating means for outputting a signal; And latch means for inputting an output of said second counting means and outputting said arm / mescam discrimination signal at a first level in an arm mode and a first level in a mescam mode in response to said reference clock signal. A digital arm / meccam discrimination circuit, characterized in that. The method of claim 1, wherein the reference signal generating means inputs the horizontal synchronization signal to delay a predetermined time, and generates a first reference signal for outputting the reference reset signal at a trailing edge of the vertical synchronization signal input in response thereto. Way; And second reference signal generation means for inputting the horizontal synchronization signal to delay the predetermined time and outputting the reference clock signal at the leading edge portion of the vertical synchronization signal input in response thereto. Arm / Messcam discrimination circuit. 2. The apparatus of claim 1, wherein the first counting means comprises: a first T flip-flop that uses the horizontal sync signal as a clock input and the arm / mescam signal as a clear input; And a second T flip flop for outputting the positive output to the second counting means with the positive output of the first T flip-flop as the clock input and the arm / mescam signal as the clear input. Arm / Messcam discrimination circuit. 2. The apparatus of claim 1, wherein the second counting means comprises: a first inverted AND that inverts and outputs the output of the first counting means and the output of the second counting means; A third T flip-flop for outputting the first inverse logical product as a clock input and for setting the reference reset signal as a clear input; A fourth T flip-flop that uses the positive output of the third T flip-flop as a clock input and the reference reset signal as a clear input; A fifth T flip-flop that has a positive output of the fourth T flip-flop as a clock input and the reference reset signal as a clear input; A sixth T flip-flop that has a positive output of the fifth T flip-flop as a clock input and the reference reset signal as a clear input; And a seventh T flip-flop for outputting the negative output to the first inverted AND and the latch means with the positive output of the sixth T flip-flop as a clock input and the reference reset signal as a clear input. Arm / messcam discrimination circuit of digital system to say. 3. The apparatus of claim 2, wherein the first reference signal generating means comprises: a first inverter for inverting the vertical synchronization signal; A first D flip-flop that uses the output of the first inverter as a data input and uses the horizontal synchronization signal delayed by the predetermined time as a clock input; A second D flip-flop that uses the horizontal synchronizing signal delayed by a predetermined time as a clock input and uses a constant output of the first D flip-flop as a data input; And a second inversion AND product that inverts and outputs the positive output of the first D flip-flop and the negative output of the second D flip-flop to output the reference reset signal as the reference reset signal. 3. The apparatus of claim 2, wherein the second reference signal generating means comprises: a 3D flip-flop for inputting the vertical synchronization signal as a data input and for inputting the horizontal synchronization signal delayed by a predetermined time as a clock input; A fourth 4D flip-flop that uses the output of the third 3D flip-flop as a data input and uses the horizontal synchronization signal delayed by a predetermined time as a clock input; And a third inversion AND product that inverts and outputs the positive output of the 3D flip-flop and the negative output of the 4D flip-flop. The 5D flip-flop according to claim 1, wherein the latching means is configured to output a fifth / flop flop for outputting the arm / meccam discrimination signal as a negative output using the output of the second counting means as a data input and the reference clock signal as a clock input. A digital arm / meccam discrimination circuit, characterized in that it is provided.