JP2596163B2 - Field identification device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a field identification device for distinguishing between odd and even fields of a television signal.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional example of this type of field identification device. FIGS. 6 (a) and 6 (b) show the operation of the conventional example of FIG. 5 at the end of an odd field and at the end of an even field, respectively. It is a timing chart.

The burst detection circuit 11 extracts the envelope of the burst signal BU and outputs it as a detection output BD. Pulse generation circuit 12
Outputs a pulse output SP having a pulse width T shown in Expression (1) every time the detection output BD is input.

0.5H <T <(H−B) (1) where H is a horizontal scanning period B is a horizontal blanking period The gate circuit 13 is an equivalent pulse extracted from the composite synchronization signal.
The logical product of the EQ and the pulse output SP is calculated, and a field identification signal FD is output.

Next, the operation of the conventional example will be described with reference to FIGS. 6 (a) and 6 (b).

(1) At the end of the odd field (FIG. 6 (a)).

Each time the horizontal synchronizing signal is input, the pulse generation circuit 12 outputs a pulse output SP having a pulse width T in synchronization with the detection output BD of the burst signal BU at the trailing edge of the horizontal synchronizing signal, and outputs a vertical synchronizing signal (not shown). ) Is output, the new pulse output SP is stopped until the output of the equivalent pulse EQ related to the vertical synchronization signal ends. Therefore, the horizontal synchronization signal number 262,263
After the pulse output SP is output between the two, the pulse output SP is temporarily stopped. The equivalent pulse EQ is the horizontal sync signal number
Output is started after 262 horizontal synchronization signals are output. Since the gate circuit 13 takes the logical product of the pulse output SP and the equivalent pulse EQ, the pulse output SP between the horizontal synchronization signal numbers 262 and 263 is output, and while the equivalent pulse EQ is output, The identification signal FD is set to the logic level high.

(1) At the end of an even field (FIG. 6 (b)).

Since the vertical synchronization signal is output after the horizontal synchronization signal number 1, the pulse output SP is stopped. Pulse output S
Is output, the equivalent pulse EQ is not output, so the field identification signal FD is at the logic low level.

Accordingly, the start of the even field and the start of the odd field are identified by the high and low logic levels of the field identification signal FD when the vertical synchronization signal is input.

[Problems to be solved by the invention]

The conventional field identification device described above uses an equivalent pulse EQ.
However, there is a disadvantage that the VTR signal cannot be used because there is no equivalent pulse EQ.

[Means for solving the problem]

The field identification device of the present invention, during each horizontal scanning period of the television signal, during a period other than when the horizontal synchronization signal is input, an oscillation circuit that oscillates a clock at a preset frequency, for each horizontal synchronization signal input, The number of clocks output from the oscillation circuit is counted, and when the counted result reaches the first set number, the output is changed from the first logical level to the second logical level, and the counted result becomes larger than the first set number. A data signal generating circuit for returning an output from the second logical level to the first logical level when the second determined number becomes large;
When the vertical synchronizing signal is input, the start of the odd field is detected when the output of the data signal generation circuit is at the first logic level, and the start of the even field is detected when the output is at the second logic level. Wherein the first set number and the second set number are set such that when the start of the odd field is started, the output of the data signal generation circuit is at the first logic level. A synchronization signal is set to be input, and in the case of the start of the even field, the vertical synchronization signal is set to be input when the output of the data signal generation circuit is at the second logic level. It is characterized by having.

[Action]

The rising timing of the vertical synchronizing signal at the end of the even and odd fields is synchronized with the rising of the horizontal synchronizing signal or between the horizontal synchronizing signals.
Looking at the output of the data signal generating circuit at the first logic level near the horizontal synchronizing signal and at the second logic level at other places, even numbers,
Odd fields can be identified.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a field identification device of the present invention, and FIGS. 2 and 3 are oscillator circuits of the embodiment of FIG.
1, a configuration diagram showing the data signal generation circuit 2 in detail,
FIGS. 4A and 4B are timing charts showing the operation of the embodiment of FIG. 1 at the end of the even field and at the end of the odd field, respectively.

The oscillation circuit 1 oscillates only during a period during which the horizontal synchronization signal HS is not input, and outputs an oscillation output PP. The data signal generating circuit 2 receives an oscillation output PP oscillated every time the horizontal synchronizing signal HS falls, and when the number of pulses reaches a preset m number, sets the output to a logic level low (hereinafter referred to as logic L), (M + n)
When the number reaches the logic level, the logic level is set high (hereinafter referred to as logic H). The D-type flip-flop 3 (hereinafter referred to as DDF3) is a rising edge of the vertical synchronizing signal VS input to the clock terminal CK,
The data signal DP input to the data input terminal D is latched and output to the non-inverting output terminal Q as the field identification signal FD.

The oscillation circuit 1 includes inverters 11 ₁ and 11 ₂ and an AND circuit 12
, A resistor R, and capacitors C ₀ and C ₁ . Inverter 11 ₁ inverts the logic level of the horizontal synchronizing signal HS,
Since the signal is applied to one gate of the AND circuit 12, the other gate of the AND circuit 12 is opened when the horizontal synchronizing signal HS is not input, and the inverter 11, the AND circuit 12, the resistor R, the capacitors C ₀ , C ₁ forms an oscillation circuit and outputs an oscillation output PP. The oscillation frequency is determined by the resistor R and the capacitors C ₀ and C ₁ .

Data signal generation circuit 2 includes a clock counter 21, a coincidence detection circuit 22 _m, 22 _{m + n,} an OR circuit 23, are made of DFF24 Prefecture. The clock counter 21 is reset every time the horizontal synchronization signal HS is input, and counts the oscillation output PP. The coincidence detecting circuits 22 _m and 22 _{m + n} hold predetermined numerical values m and m + n, respectively (m and n are natural numbers), and logically output when the count of the clock counter 21 reaches the numerical value m and m + n. H. The DFF 24 is set every time the horizontal synchronizing signal HS is input. Each time the output of the OR circuit 23 becomes logic H, the output of the inverted output terminal is latched from the data input terminal D, and the data signal is output from the non-inverted output terminal Q. Output as DD.

Next, the operation of the embodiment of FIG. 1 will be described with reference to FIGS.
This will be described with reference to FIG.

(1) At the end of the even field (FIG. 4 (a)).

When the horizontal synchronization signal HS falls, the oscillation circuit 1 starts oscillating in synchronization with the fall. The count output of the clock counter 21 is reset by the horizontal synchronization signal HS. However, when the oscillation circuit 1 starts oscillating at the fall of the horizontal synchronization signal HS,
Counts the oscillation output PP. When the coincidence detection circuit 22 _m detects that the count of the clock cow counter 21 has reached m, the DFF 24 latches the logic L at the inverted output terminal, falls the data signal DP, and sets it to logic L. Match detection circuit 22 _{m + n}
Detects that the count of the clock counter 21 has reached (m + n), the DFF 24 latches the logic H at the inverting output terminal, raises the data signal DP, and sets it to logic H. Data signal DP is time T ₀ becomes the logic L is intended to be determined by the period × n of the oscillation output PP, in the present embodiment 1 / 4H <T <3 / 4H
(1H is one horizontal scanning period). Since DFF3 latches the data signal DP of logic H at the rise of the vertical synchronizing signal VS, the field identification signal FD becomes logic H, and it is transmitted that the odd field has started.

(2) At the end of the odd field (FIG. 4 (b)).

The relationship between the horizontal synchronizing signal HS and the data signal DP is the same as that at the end of the even field, and a description thereof will be omitted. Since DFF3 latches the data signal DP of logic L at the rise of the vertical synchronization signal VS, the field identification signal FD becomes logic L, and it is transmitted that the even field has started.

However, the horizontal synchronizing signal HS is always output even during the vertical blanking period (including the vertical synchronizing signal) by the synchronizing separation circuit (not shown) of the television receiver.

Even if the phase relationship between the horizontal synchronization signal and the vertical synchronization signal slightly changes due to the influence of a circuit or the like, the data signal for the horizontal synchronization signal is changed by changing the set values m and m + n of the matching circuits 2 _m and 2 _{m + n.} can modify the phase and the pulse width T ₀ of DP, easily cope.

〔The invention's effect〕

As described above, according to the present invention, the output of the data signal generating circuit is set to the second logical level for a predetermined period during which the horizontal synchronizing signal is not output, and the data is output outside the predetermined period including the period during which the horizontal synchronizing signal is output. Since the output of the vertical synchronization signal at the end of the even and odd fields is synchronized with the rise of the horizontal synchronization or between the horizontal synchronization signals, the rising edge of the vertical synchronization signal By judging the logical level of the output of the data signal generating circuit at the time, there is an effect that even-numbered and odd-numbered fields can be distinguished even for a television signal that does not include an equivalent pulse.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the field identification device of the present invention, and FIGS. 2 and 3 are oscillator circuits 1 and 2 of the embodiment of FIG.
FIG. 4A and FIG. 4B are timing charts showing the operation of the embodiment of FIG. 1 at the end of the even field and the end of the odd field, respectively. 6A and 6B are timing charts showing the operation of the conventional example shown in FIG. 5 at the end of an odd field and at the end of an even field, respectively. 1 Oscillation circuit 2 Data signal generation circuit 3 24 DFF 11 ₁ and 11 ₂ Inverter 12 AND circuit 21 Clock counter 22 _m and 22 _{m + n} … Match detection circuit, 23 …… OR circuit.

Claims (1)

(57) [Claims] An oscillator circuit for oscillating a clock at a preset frequency during a period other than when a horizontal synchronizing signal is input during each horizontal scanning period of a television signal, and an oscillator circuit for each horizontal synchronizing signal input. The number of clocks output is counted, and when the counted result reaches the first set number, the output is changed from the first logical level to the second logical level, and the counted result is larger than the first set number. And a data signal generating circuit for returning the output from the second logical level to the first logical level when the set number is reached, and when the output of the data signal generating circuit is at the first logical level when the vertical synchronizing signal is inputted. Detects the start of an odd field,
A logic circuit for detecting that the start of an even field is at a second logic level, wherein the first set number and the second set number are the data signals in the case of the start of the odd field. The vertical synchronizing signal is set to be input when the output of the generation circuit is at the first logic level, and when the even field starts, the output of the data signal generation circuit is set to the second logic level. A field identification device which is set so that the vertical synchronizing signal is input when the level is at a level.