JPH0193266A - Separation device for composite synchronizing signal - Google Patents

Abstract

PURPOSE:To prevent an adverse effect due to an environmental factor from being generated and to easily make a circuit into an integrated circuit by extracting a horizontal synchronizing signal by a first gate means in which the output on one side of complementary output derived from a counter means is used as a gate signal and outputting the output on the other side by extracting a vertical synchronizing signal by a second gate means. CONSTITUTION:A composite synchronizing signal inputted from a composite synchronizing signal input terminal 1 is inputted to the input terminal on one side of an AND gate 2 for separating the horizontal synchronizing signal and the input terminal on one side of an AND gate 3 for separating the vertical synchronizing signal. And the output Out and Out' of a counter circuit 4 are supplied to the input terminals on the other side of the AND gates 2 and 3. Also, those output Out and Out' are count up output outputted by counting the prescribed number of clock pulses from a clock source 5 by the counter circuit 4, and they are the complementary output in which the output on one side is set at a low level when the output on the other side is set at a high level. Therefore, it is possible to prevent the cycle of the gate signal from being disordered by the environmental factor such as temperature change, etc., and also, to make the circuit into the integrated circuit easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention is used, for example, in image communication devices such as television receivers and video signal processing devices such as magnetic recording and reproducing devices to determine the scanning timing of scanning lines. However, regarding a composite synchronizing signal separation device for synchronizing the developing operation on the receiving side with that on the transmitting side, in detail, it includes repeating a horizontal synchronizing signal at a predetermined horizontal period, and the horizontal synchronizing signal has a signal that does not overlap with the horizontal synchronizing signal. The present invention relates to a composite synchronization signal separation device that separates a composite synchronization signal having a phase shift and repeating a vertical synchronization signal at a predetermined vertical period into a horizontal synchronization signal and a vertical synchronization signal.

[Prior Art] Conventionally, for example, in a television receiver, in order to reproduce an image on the receiving side, the scanning on the receiving side must be completely synchronized both vertically and horizontally with the transmitting side. , a pulse signal (horizontal synchronization signal) that determines the start of each scanning line and a pulse signal (vertical synchronization signal) that determines the start of each field are inserted into the blanking period of the image signal. Transmitting at a level below black. and,
On the receiving side, the video signal is removed from the signal received from the antenna, only a composite sync signal containing a horizontal sync signal and a vertical sync signal is extracted, and then the composite sync signal is combined into a horizontal sync signal and a vertical sync signal. The aim was to use these synchronization signals to synchronize scanning both vertically and horizontally with the transmitting side.

In recent years, for example, a high-definition standard synchronization signal has been considered as a synchronization signal for high-definition television, and this high-definition standard synchronization signal includes repetition of a horizontal synchronization signal at a predetermined horizontal period. It is a pulse-like signal that has a phase shift that does not overlap with the signals and includes repetition of a vertical synchronizing signal at a predetermined vertical period.

A conventionally known composite synchronizing signal separating device for separating the composite synchronizing signal into a horizontal synchronizing signal and a vertical synchronizing signal is, for example, the circuit shown in FIG.

Composite synchronization signal input from composite synchronization signal input terminal 8 (
The high-definition standard synchronizing signal) is inputted to one input terminal of an AND gate 9 for extracting a horizontal synchronizing signal and one input terminal of an AND gate 11 for extracting a vertical synchronizing signal. Also,
The q output of the monostable multivibrator 10 is input to the other input terminal of the AND gate 9 for horizontal synchronization signal extraction, and the q output of the monostable multivibrator 10 is input to the other input terminal of the AND gate 11 for vertical synchronization signal extraction. It is configured so that the Q output is input. Further, the output from the AND gate 9 for horizontal synchronization signal extraction is input as a trigger input to the trigger input terminal T of the monostable multivibrator 10, and is output as a horizontal synchronization signal from the horizontal synchronization signal output terminal 12. Furthermore, the output from the AND gate 11 for vertical synchronization signal extraction is outputted from the vertical synchronization signal output terminal 13 as a vertical synchronization signal. In addition, in the figure,
C is a capacitance, and R is a resistance, which determines the CR time constant and the oscillation frequency of the monostable multi-bibreak 10.

Next, the operation will be explained based on FIG.

FIG. 5 is a timing chart for explaining the operation of FIG. 4.

In the initial state, the q output of the monostable multivibrator 10 is at a high level, and the Q output is at a low level. When the composite synchronization signal (a) (logical level) is input to the composite synchronization signal input terminal 8, a q output, that is, a high level signal is input to one input terminal of the AND gate 9 for horizontal synchronization signal extraction. Therefore, the pulse of the composite synchronization signal (a) is output from the output terminal of the AND gate 9 for extracting the horizontal synchronization signal. And its output is a monostable multi-bi break 10 with tri as input
The monostable multivibrator is set so that a positive pulse appears on the output Q side of the monostable multivibrator 10 at a timing coinciding with the fall of the pulse of the trigger input. Furthermore, the capacitance C of the resistor R5 is selected so that the output pulse width t has an appropriate value that sufficiently covers the vertical synchronizing signal and does not extend to the adjacent horizontal synchronizing signal. Therefore, the Q output of the monostable multivibrator becomes as shown in FIG. 5(b), and only the horizontal synchronizing signal appears at the output of the AND gate 9, that is, the output terminal 12, as shown in FIG. 5(C).

On the other hand, the Q output of the monostable multivibrator 10 is as shown in FIG. 5(d), and the output of the AND gate 11, that is, the output terminal 13, has only the vertical synchronizing signal as shown in FIG. 5(e). . In other words, monostable multivibrator 10
Complementary outputs oscillated from the two are used as gate signals, and the horizontal synchronizing signal and the vertical synchronizing signal are separated by the AND gate 9 for extracting the horizontal synchronizing signal and the AND gate 11 for extracting the vertical synchronizing signal.

[Problems to be Solved by the Invention] However, since the conventional composite synchronous signal separation device uses a monostable multivibrator, external resistance and capacitance are essential to determine the 02 time constant. For this reason, the resistance and capacitance values change with changes in the environment such as temperature changes, the oscillation frequency of the monostable multivibrator goes out of order, and the pulse width t shown in Fig. 5 goes out of order.
For example, there are drawbacks in that a portion of the horizontal synchronizing signal is missing in a portion X indicated by a broken line in the figure, and an extra pulse (Y in the figure) is generated in the vertical synchronizing signal. Furthermore, there is also the problem that it is difficult to integrate into an integrated circuit due to external resistance and capacitance.

In view of the above circumstances, it is an object of the present invention to provide a composite synchronization signal separation device that is not adversely affected by environmental factors such as temperature changes and is easy to integrate into an integrated circuit.

[Means for Solving the Problems] A composite synchronization signal separation device according to the present invention includes: a clock source that generates a clock pulse with a predetermined period shorter than a horizontal synchronization signal; and the horizontal synchronization signal separated from the clock pulse. is received, the number of clock pulses corresponding to the horizontal period is counted, and the signal is reset by the separated horizontal synchronizing signal, thereby controlling the first level and the second level at a predetermined interval.
counter means for deriving complementary outputs in which the levels of and the levels of are repeated; one output of the complementary outputs is inputted as a gate signal and the composite synchronization signal is inputted to derive the separated horizontal synchronization signals; a first gate means; and a second gate means for deriving the separated vertical synchronization signal by inputting the other output of the complementary outputs as a gate signal and inputting the composite synchronization signal. It is characterized by

[Operation] Since the output signal from the first gate means, that is, the separated horizontal synchronizing signal, is given to the counter means as a reset signal, the complementary outputs derived from the counter means are The first level and the second level are repeated, and a horizontal synchronizing signal is extracted and outputted by the first gate means which uses one of the complementary outputs as a gate signal, and the other complementary output is extracted and outputted. A vertical synchronizing signal is extracted and output by the second gate means used as a gate signal. And the above-mentioned 1. Since the second gate signal is a signal whose cycle is a predetermined count period in response to the clock signal from the clock source, there is no problem of the cycle being disrupted due to adverse effects caused by environmental factors such as temperature changes. .

Furthermore, since a clock source and a counter are used as the gate signal generation means, there is no need to add a resistor and capacitance to determine the period of the complementary output used as the gate signal, and it is possible to integrate the circuit. Cheap.

[Embodiments of the invention] Next, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, 1 is a composite sync signal input terminal, 2 is an AND gate for horizontal sync signal separation, 3 is an AND gate for vertical sync signal separation, 4 is a counter circuit which is an example of a counter means, and 5 is a counter circuit. 6 is a horizontal synchronizing signal output terminal, and 7 is a vertical synchronizing signal output terminal.

The composite synchronizing signal input from the composite synchronizing signal input terminal 1 is input to one input terminal of an AND gate 2 for horizontal synchronizing signal separation and one input terminal of an AND gate 3 for vertical synchronizing signal separation. The other input terminal of the AND gate 2 for horizontal synchronization signal separation is connected to the O of the counter circuit 4.
ut output is given, and the other input terminal of the AND gate 3 for vertical synchronization signal separation is given the Ou output of the counter circuit 4.
r output is given. Note that these Out outputs and Out
The output is a count-up output produced by the counter circuit 4 counting a predetermined number of clock pulses from the clock source 5, and is a complementary output in which if one is at a high level, the other is at a low level. The output from the AND gate 2 for horizontal synchronization signal separation is input to the reset terminal of the counter circuit 4 and output from the horizontal synchronization signal output terminal 6. Further, the output from the AND gate 3 for vertical synchronization signal separation is output from the vertical synchronization signal output terminal 7.

The counter circuit 4 is a well-known type consisting of a flip-flop, and the clock source 5 is also composed of a well-known type such as a clock pulse generator. Further, in this embodiment, a counter circuit is used as the counter means, but the present invention is not limited to this, and the present invention is not limited to this, but the present invention is not limited to this. A microcomputer with a built-in program may also be used.

Next, the operation will be explained. FIG. 2 is a timing chart of the circuit shown in FIG.

When a high-quality standard synchronization signal (A) (logic level), which is an example of a composite synchronization signal, is input to the composite synchronization signal input terminal 1, the output Out of the counter circuit 4 is at a high level and the output Out is at a low level in the initial state. It becomes. Therefore, the horizontal synchronization signal among the composite synchronization signals inputted first passes through the AND gate 2 and resets the counter circuit 4. Immediately after that, the counter circuit 4 starts counting, and during the counting period T, the output Out goes to low level.
It operates so that the output Out becomes high level.

These situations are shown in Figure 2 CB) and (D).

(A).

Therefore, the pulse shown in FIG. 2(C) is the output signal from the AND gate 2 into which both the pulses shown in (A) and (B) are input, and both (A) and (B) are at high level. A high level signal is output only when the Therefore, the pulse signal shown in (C) becomes a horizontal synchronization signal separated from the composite synchronization signal. Also, only this horizontal synchronizing signal is input to the reset input of the counter circuit 4, and at that moment, the count-up output (high level) from the counter circuit is switched to low level. On the other hand, in FIG. 2, the pulse shown in (E) is an output signal from the AND gate 3 into which both pulse signals (A) and (D) are input, This is a signal that becomes high level only when both are high level. Therefore, the signal (E) becomes a vertical synchronization signal separated from the composite synchronization signal. Then, this vertical synchronization signal is output from the vertical synchronization signal output terminal 7.

In other words, by AND gate 2 for horizontal synchronization signal separation,
A first gate means is configured to extract a horizontal synchronizing signal using the Out output from the counter circuit 4 as a gate signal, and an AND gate 3 for separating the vertical synchronizing signal gates the Out output from the counter circuit 4. A second gate means is configured to extract a vertical synchronization signal as a signal.

In addition, in FIG. 2, T is 29.66 μSec.

T2 is 28.43μsec, T is 9.3uSecST
4 is 0.46 μSec. Moreover, T, >74 T, -2T6<TNT, -T4.

That is, the count period T is set to an appropriate value that sufficiently covers the vertical synchronizing signal in the composite synchronizing signal and does not cover the adjacent horizontal synchronizing signal. Furthermore, since the clock source is in a free-running state, it must have a frequency that allows at least three clocks to pass between the odd field vertical synchronizing signal and the adjacent horizontal synchronizing signal (see FIG. 3). In other words, if the clock pulse has a frequency less than 3 clocks between an odd field vertical synchronizing signal and an adjacent horizontal synchronizing signal, the count-up output from the counter circuit 4 will increase when the clock pulse is out of phase with the odd field vertical synchronizing signal. The signal is output within the pulse width of the vertical synchronizing signal or the adjacent horizontal synchronizing signal, making it impossible to separate the horizontal synchronizing signal and the vertical synchronizing signal well. Therefore, the clock pulse should have a frequency of at least 3 clocks,
Even if the phase of the clock pulse is slightly shifted, the count-up output from the counter circuit 4 is generated between the odd field vertical synchronizing signal and the adjacent horizontal synchronizing signal. Note that, as shown in FIG. 3, if the clock pulse has a frequency that allows three clocks to occur between the odd field vertical synchronizing signal and the adjacent horizontal synchronizing signal, the count up output from the counter circuit 4 is derived from the count number. The minimum value is 186 counts.

[Effects of the Invention] Since the present invention has the above-mentioned configuration, the gate signal does not have the inconvenience of having its cycle deviated due to environmental factors such as temperature changes, and is not adversely affected by environmental factors such as temperature changes. It has now been possible to provide a composite synchronization signal separation device that is easy to integrate into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a composite synchronizing signal separation circuit which is an example of the composite synchronizing signal separating device of the present invention, FIG. 2 is a timing chart of the circuit shown in FIG. 1, and FIG. 3 is a clock from a clock source. 4 is a block diagram showing a conventional composite synchronizing signal separation circuit, and FIG. 5 is a timing chart of the circuit shown in FIG. 4. In the figure, 2 is an AND gate that is an example of the first gate means, 3 is an AND gate that is an example of the second gate means, and 4 is an AND gate that is an example of the second gate means.
5 is a counter circuit which is an example of counter means, and 5 is a clock source.

Claims (3)

[Claims] (1) A composite synchronization signal that includes repetition of a horizontal synchronization signal with a predetermined horizontal period, has a phase shift that does not overlap with the horizontal synchronization signal, and includes repetition of a vertical synchronization signal with a predetermined vertical period. , a composite synchronization signal separation device that separates a horizontal synchronization signal and a vertical synchronization signal, the clock source generating a clock pulse having a predetermined period shorter than the horizontal synchronization signal; and the horizontal synchronization signal separated from the clock pulse. the first level and the second level at a predetermined interval by counting a number of clock pulses corresponding to the horizontal period and being reset by the separated horizontal synchronizing signal.
counter means for deriving complementary outputs whose levels are repeated; one output of the complementary outputs being input as a gate signal and the composite synchronizing signal being input, thereby deriving the separated horizontal synchronizing signal; a first gate means; and a second gate means for deriving the separated vertical synchronization signal by inputting the other output of the complementary outputs as a gate signal and inputting the composite synchronization signal. , composite synchronous signal separation device. (2) The composite synchronization signal separation device according to claim 1, wherein the first gate means and the second gate means include AND gates. (3) The composite synchronization signal separation device according to claim 1 or 2, wherein the counter means includes a counter circuit.