KR950005055B1 - Synchronizing signal selection circuit - Google Patents

Abstract

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Description

Sync signal selection circuit

1 is a block diagram showing a synchronization signal selection circuit in the first embodiment of the present invention.

2 is a timing chart for explaining the operation of the first embodiment.

3 is a block diagram showing an example of a horizontal synchronous signal separation circuit for use with the synchronous signal selection circuit of the present invention.

FIG. 4 is a timing chart illustrating the operation of the horizontal synchronous signal separation circuit of FIG. 3 when pulses generated by noise are mixed in a complex synchronous time signal.

5 is a circuit diagram for explaining a second embodiment of the present invention.

6 is a circuit diagram for explaining a third embodiment of the present invention.

7 shows an example of a horizontal synchronizing signal obtained from the composite synchronizing signal by the synchronizing signal selecting circuit of the present invention, and a horizontal synchronizing signal separation circuit shown in FIG.

8 is a block diagram showing a PLL circuit used to generate a sampling clock in a prior art LCD device.

9A to 9C show a composite synchronous signal used in an NTSC system.

Figure 10 shows the composite synchronous signal obtained from the video which was dependent on the double prevention process.

11 is a block diagram showing a fourth embodiment of the present invention.

12 is a timing chart for explaining the operation of the fourth embodiment.

Fig. 13 is a block diagram showing an example of variation of the fourth embodiment.

14 is a block diagram showing a fifth embodiment of the present invention.

FIG. 15 is a timing chart for explaining the operation of the fifth embodiment.

16 and 17 are block diagrams showing examples of variations of the fifth embodiment.

* Explanation of symbols for main parts of the drawings

1: selection circuit 2, 13: counter

3, 14: decoder 4, 16: RS flip flop

5, selector 10: horizontal synchronous signal separation circuit

11: rising edge detection circuit 12, 17: AND gate

21: horizontal synchronization signal 22: equalization pulse

25: vertical synchronization signal

The present invention relates to a synchronization signal selection circuit, and more particularly, to a synchronization signal selection circuit for extracting a timing of a horizontal synchronization signal from a composite synchronization signal.

Thereafter, the "sync signal" is weakened to the "sync signal".

In a television system such as a NTSC (National Television Systerm Committee) system or a PAL (Phase Alternation Line) system, only a composite synchronization signal in which the vertical synchronization signal and the horizontal synchronization signal are combined is supplied as a synchronization signal to the television device.

As is well known, this composite synchronization signal is obtained by separating it from the composite video signal carried on the transmission broadcast wave.

In a matrix liquid crystal display (LCD) device that has been widely used in recent years, a clock signal for sampling the video signal of the LCD device is generated.

This clock signal must be precisely synchronized with the horizontal synchronous signal when the display is executed based on the image information in the television system, so that the clock signal is generated using a phase-locked loop (PLL) circuit as shown in FIG. do.

The PLL circuit 100 has a loop including a voltage controlled oscillator (VOC) 101, a frequency divider 102, a phase compensator 103, and a low-pad filter (LPF) 104.

It is preferable to supply the horizontal synchronizing signal as the synchronizing signal sync which is an input signal of the PLL circuit 100.

However, in the prior art, the composite synchronization signal is supplied as such.

9A to 9C show a combined synchronization signal used in an NTSC system.

9A shows the composite synchronization signal with the transition period from even fields to odd fields.

9B shows a portion of the composite synchronization signal in one field.

In Fig. 9C, the composite ceramic signal in the transition period from odd field to even field is displayed.

As shown in Figs. 9A and 9E, in addition to the horizontal synchronizing signal 21, a vertical synchronizing signal and an equalization pulse 22 are present in the composite synchronizing signal in the transition period from one field to the next. Equalization pulses 22 are inserted to equalize the waveform of the composite synchronous signal at and around the vertical synchronous signal during the transition period from the even field to the odd field and from the odd field to the even field.

At the periphery of the vertical synchronization signal, the width of the horizontal synchronization signal 21 and the equalizing pulse 22 is half (1/2) of that of the normal horizontal synchronization signal 21.

In the prior art, since the composite synchronous signal is input to the PLL circuit 100 (Fig. 8), the phase relationship in the PLL circuit 100 is disturbed due to the presence of the vertical synchronous signal and is shown in Figs. 9A and 9C. Equalize the pulses in the composite synchronization signal.

This disturbance causes the oscillation frequency of the VCO101 to oscillate.

If the fluctuation at the oscillation frequency of 101 is not absorbed until the display period enters the display period while the image information of the display area is supplied from the LCD device, the resulting image is distorted.

In order to avoid image distortion occurring, it is necessary to absorb fluctuations at the oscillation frequency of VCO101 for a period preceding the display period (vertical retrace interval).

This is a major obstacle in simplifying the design of PLL circuits for matrix display devices such as LCD devices.

In addition, for some commercially available video tapes, the AGC (Auot Gain Control) signal of the luminance signal is partially inserted into the composite video signal to destabilize the reproduction of the video tapes produced by copying. do.

In the reproduction of such videotape, the AGC signal cannot be completely removed by the low-pass filter in the extraction of the composite synchronization signal from the composite video signal, and thus, the pulse (spurious as shown in FIG. The synchronous signal) is immediately mixed after the vertical synchronous signal in the extracted composite synchronous signal.

As shown in FIG. 10, when the composite synchronization signal in which the spurious synchronization signal is immediately present before the display period is input to the PLL circuit 100, it is practical to stabilize the PLL circuit 100 which is the spurious synchronization signal before the display period. It is impossible.

To solve this problem in the prior art, such dimensions as narrowing the area where the image is actually displayed on the display screen are used, but it is necessary to completely mask the image distortion appearing at the top of the display screen. Difficult, and satisfactory indications cannot be obtained in many cases.

To solve this problem, an improved horizontal synchronous signal separation circuit has been proposed (Japanese Patent Application No. 2-156522, US Patent Application No. 07 / 712,873, European Patent Application No. 91305351.8).

This circuit can separate the horizontal synchronization signal from the composite synchronization signal. This horizontal synchronous signal separation circuit can obtain a very stable sampling clock by supplying the horizontal synchronous signal separated by the horizontal synchronous signal separation circuit to the PLL circuit instead of the composite synchronous signal.

Thus, the display section of the matrix type display device such as the LCD device is largely opened.

However, when the quality of the composite synchronization signal is dropped due to the deteriorated propagation state in the reception of the broadcast wave, the horizontal synchronization signal separation circuit does not continue the quality of the horizontal synchronization signal from which the image quality is separated. There is a light defect that does not deteriorate quickly as a result of the film.

The synchronous signal selection circuit of the present invention, which surpasses the above coupling and coupling of the prior art, responds to the input of the vertical synchronous signal extracted to the composite synchronous signal, and generates a control signal for generating a control signal for a predetermined period of time. And the period starts when a first predetermined time period after the input of the vertical synchronization signal has elapsed, and receives the composite synchronization signal, a horizontal synchronization signal separated from the composite synchronization signal, and the control signal, and Selecting means for outputting the composite synchronization signal when the control signal is in the predetermined state, and outputting the separated horizontal synchronization signal when the control signal is in a state different from the predetermined state.

In an embodiment, said first predetermined time period is shorter than said second predetermined time period.

In one embodiment, the control signal generating means includes: counting means for receiving a periodic pulse string and calculating the number of pulses included in the periodic pulse string, and an output of the counting means is a first predetermined value. When the control signal is set to the predetermined state, and the first predetermined value corresponds to the first predetermined time period, and when the output of the counting means becomes a second predetermined value, And decoding means connected to an output of said counting means for setting said control signal in another state, said second predetermined value corresponding to said second predetermined time period.

In one embodiment, the counting means is reset by the rising edge of the vertical synchronization signal. In an embodiment, the control signal generating means includes first pulse signal generating means for responding to the input of the vertical synchronization signal and generating a first pulse signal, wherein the first pulse signal is after the input of the vertical synchronization signal. A second pulse signal generating means for ending when the first predetermined time period has elapsed, responsive to the input of the vertical synchronization signal, and issuing a second pulse signal, wherein the second pulse signal is the first pulse signal; Means for terminating when a predetermined time period results after said input of said vertical synchronization signal and generating said control signal based on said first and second pulse signals.

Preferably, the control signal generating means comprises a first pulse signal generating means for generating a first pulse signal in response to the vertical synchronization signal and the input, wherein the first pulse signal is the first predetermined signal; A second pulse signal generating means for ending when the time period has elapsed after the input of the vertical synchronization signal, in response to the termination of the first pulse signal, and generating a second pulse signal, wherein the second pulse The signal includes means for ending when the second predetermined time period has elapsed after the end of the first pulse signal and on the basis of the first and second pulse signals, generating means for generating the control signal do.

Thus, the present invention described herein enables the following objects.

(1) Provides a synchronization signal selection circuit that can accurately extract the timing of the horizontal synchronization signal from the composite synchronization signal.

(2) Provides a synchronization signal selection signal that can reliably obtain a horizontal synchronization signal from the composite synchronization signal even when noise is present in the mixed synchronization signal.

(3) Provide a synchronization signal selection circuit that can improve the image quality of display devices such as LCD devices.

Example

1 is a block diagram of a first embodiment of the present invention.

The synchronization signal selection circuit 1 of FIG. 1 includes a counter 2, a decoder 3, an RS flip-flop 4, and a selector 5. As shown in FIG.

The counter 2, the decoder 3 and the RS flip-flop 4 function together as a signal generating circuit for generating the selection signal SEL.

The vertical synchronous signal V _{syn, which} is separated from the composite synchronous signal C _sync , is input to the clear terminal CL of the counter 2.

The counter 2 is _{cleared by} the rising edge of the vertical synchronizing signal V _syn . A circuit called the vertical synchronizing signal V _syn in the composite synchronizing signal C _{sync is known} from the publication of the television institute, "Television" (Corona Publishing Co., Ltd, Jepan).

The signal HSYO, which is a periodic pulse string, is input to the clock terminal C of the counter 2.

Immediately after the counter 2 is cleared, it starts to calculate a pulse in the signal HSYC, and the operation result is supplied to the decoder 3.

The decoder 3 outputs the set signal T _S when the operation result indicates the first predetermined value after the first predetermined time period has elapsed when the counter 2 is cleared.

The decoder 3 also outputs the reset signal T _R when the operation result indicates the second predetermined value after the second predetermined time period has elapsed since the counter 2 cleared.

T set signal _S and reset signal _R T is supplied to the set terminal S and the reset terminal R of the R _S flip-flop (4).

Thus, R _S selection signal SEL output from the flip-flop 4 is set by the set signal _S T to be HIGH, and is reset by a reset signal _R T to be LOW.

The horizontal synchronizing signal H _syn and the composite synchronizing signal C _sync obtained from the composite synchronizing signal C _sync by the horizontal synchronizing signal separation circuit 10 are input to the terminal B and the terminal A of the selector 5, respectively.

The selection signal SEL is input to the terminal S of the selector 5.

The selector 5 respectively outputs the composite synchronization signal C _sync as the horizontal synchronization signal HSYN when the selection signal SEL is HIGH, and outputs the separated horizontal synchronization signal H _syn when the selection signal SEL is LOW, respectively. The signal HSYN output from the selector 5 becomes the horizontal synchronizing signal finally used.

By using this horizontal synchronizing signal HSYN as an input to a PLL circuit as shown in FIG. 8, a sampling clock signal is obtained for a matrix type display device such as an LCD device.

Next, the operation of the embodiment is described with reference to FIG.

The period from the vertical synchronization signal 25 to the next vertical synchronization signal 25 is a scanning period of one field, but the display period is part of the scanning period as shown in FIG. 2 while the display is actually executed.

The display period starts after the period of time T _B elapses from the rising edge of the vertical synchronization signal 25 and is completed after the period of time T _E elapses.

The first predetermined time period is set slightly shorter than the period of time T _B , and the second predetermined time period is set slightly longer than the period of time T _E.

Therefore, the decoder 3 outputs the set signal T _S immediately before the start of the display period and outputs the reset signal T _R immediately after the completion of the display period.

As a result, the selection signal SEL goes high during the display period, and goes low during all rides, that is, during the vertical retrace interval.

Thus, the composite synchronizing signal C _sync is output from the selector 5 together with the horizontal synchronizing signal HSYN during the display period, and the separated horizontal synchronizing signal H _syn is output from the selector 5 together with the horizontal synchronizing signal HSYN during the vertical retrace interval. .

To illustrate the advantages obtained by this embodiment, an example of the horizontal synchronous signal separation circuit 10 will first be described with reference to FIG.

When the rising edge detection circuit 11 detects the rise of the composite synchronization signal C _sync , the pulse signal HED is supplied to one input terminal of the AND gate 12.

The counter 13 calculates the number of pulses in the clock signal CLK. The output of the counter 13 is supplied to the decoder 14.

Decoder 14 decodes the output of three timing signals t ₁ , t ₂ and t ₃ .

The timing signals t ₁ and t ₂ are input to the reset terminal R and the set terminal S of the RS flip-flop 15, respectively.

The output signal TPF of the RS flip-flop 15 is supplied to the other input terminal of the AND gate 12, and the pulse signal HED passes through the AND gate 12 while the signal TPF is HIGH.

That is, the signal TPF is a control signal of the AND gate 12, and this control signal TPF is generated by the RS flip-flop 15 and the decoder 14 based on the output of the counter 13.

The output of the AND gate (that is, the signal HED passing through the AND gate 12) is input to the clear terminal CL of the townman 13.

The timing signal t ₃ is supplied to the reset terminal R of the RS flip flop 16.

The output of the AND gate 12 is supplied to the set terminal S of the RS flip flop 16. The signal IH _syn output from the RS flip-flop 16 and the composite synchronous signal C _sync are respectively input to two input terminals of the AND gate 17.

The separated horizontal synchronization signal H _syn is output from the AND gate 17. The rise of the pulse in the separated horizontal synchronizing signal H _{syn corresponds} substantially to the path of the pulse signal HED through the RS flip-flop 16 and the AND gate 12.

3 and the operation of the horizontal synchronous signal separation circuit 10 and other configurations of the horizontal synchronous signal separation circuit 10 have been described in the above patent application. When the quality of the received video signal drops to a certain degree due to the deterioration of the propagation state, the pulses generated by the noise are mixed with the composite synchronous signal C _sync extracted to the composite video signal.

FIG. 4 shows the separated horizontal synchronizing signal H _syn signal IH _syn , the control signal TPF and the noise generated in the horizontal synchronizing signal separation circuit 10 (FIG. 9 third) when the composite synchronizing signal C _sync including rising is input. Displays the composite sync signal C _sync that contains.

In FIG. 4, the composite synchronizing signal C _sync also includes pulses 41, 42, 43 and 44 generated by noise in addition to the horizontal synchronizing signal 21.

Among these pulses, pulses 41 and 42 do not affect the separated horizontal synchronizing signal H _syn because they are eliminated by the control signal TPF.

However, since pulses 43 and 44 are generated during the period when the control signal TPF is HIGH, they do not affect the separated horizontal synchronizing signal H _syn .

In particular, since the pulse 43 loses many waveforms of the element planar synchronizing signal 21 in the complex synchronizing signal C _sync , the pulse 43 causes the separated horizontal synchronizing signal H _syn .

In the extreme case, the raw water level synchronizing signal 21 is completely null with the horizontal synchronizing signal H _syn separated due to the pulse generated by the noise.

In this case, the PLL circuit into which the separated horizontal synchronizing signal H _syn is input is greatly affected, resulting in a large shift in the phase of the clock signal output in the PLL circuit 100.

In the case where the level of response mixed in the composite video signal is lower than the threshold level of the separation circuit that separates the composite synchronous signal C _sync from the composite video signal, such a pulse is not mixed in the composite synchronous signal C _sync , and is good. The separated horizontal synchronization signal H _syn is obtained from the horizontal synchronization signal separation circuit 10.

However, when the noise level exceeds the threshold level of the separation circuit that separates the composite synchronization signal C _sync from the composite video signal, the pulses become mixed with the composite synchronization signal C _sync , thus, the quality of the separated horizontal synchronization signal H _syn. To be dropped below it of the original composite synchronization signal C _sync .

Since this deterioration in the quality of the separated horizontal synchronizing signal H _syn occurs at an instant, the noise level exceeds a certain level, and the image quality is extinguished and severely when the quality of the separated horizontal synchronizing signal H _syn is degraded. Degrades.

According to this embodiment, the horizontal synchronous signal obtained by the horizontal synchronous signal separation circuit 10, i.e., the horizontal synchronous signal H _syn obtained by removing the vertical synchronous signal and equalizing the pulses included in the composite synchronous signal is horizontal synchronous signal. It is output as the horizontal synchronization signal HSYN only during the vertical retrace interval while the waveform of the composite synchronization signal C _{sync in that} of the signal 21 is large.

In the display time during which the composite synchronizing signal C _sync includes only the horizontal sync signal 21, the composite sync signal C _sync is output as the horizontal synchronizing signal HSYN.

Thus, the quality of the horizontal synchronizing signal HSYN does not fall below that of the original composite synchronizing signal C _sync , and the resistance to noise in the case of the high noise level is improved.

5 includes a second embodiment of the present invention.

In FIG. 5, components similar to those of the first signal synchronizing signal selection circuit 1 are denoted by the same reference numerals as in FIG.

In this embodiment, the vertical simultaneous signal V _syn is input to the clear terminal CL of the counter 2 via the rising edge detection circuit 6.

The rising edge detection circuit 6 includes a resistor 651, a capacitor 652, a buffer 653, an inverter 654, and an AND gate 655. The counter 2 is a binary counter.

The outputs Q ₂ , Q ₅ and Q ₉ of the counter 2 are fed to decoder 3.

The output of the frequency divider 102 of the PLL circuit 100 similar to that of FIG. 8 is used as the signal HSYO input to the clock terminal difference of the counter 2.

The horizontal synchronizing signal HSYN at the selector 5 is input to the phase comparator 103 of the PLL circuit 100.

Since the separated horizontal synchronizing signal H _syn includes a pulse generated by the noise as described above, it is not preferable to use the separated horizontal synchronizing signal H _syn as the signal HSYO.

The decoder 3 includes a NAND gate 351 for outputting a set signal T _S , and an inverter 352 for outputting a reset signal T _R.

The outputs Q ₂ and Q ₅ of the counter 2 are input to the NAND gate 351.

Thus, the set signal T _S is output when the value of the output of the counter 2 becomes 256 (decimal).

The select signal SEL responds to the set signal T _S and goes high. The output Q ₉ of the counter 2 is supplied to the inverter 352.

Thus, the reset signal T _R is output when the value of the output of the counter 2 becomes 18 (decimal).

The selection signal SEL becomes LOW in response to the reset signal T _R.

6 shows a third embodiment of the present invention.

In FIG. 6, components similar to those of the synchronization signal selection circuit 1 in FIG. 1 are indicated by the same reference numerals as in FIG.

In this embodiment, the rising edge detection circuit 66 including the D-type flip flop 661, the AND gate 662, and the inverter 663 is used in place of the rising edge detection circuit 6 in FIG. do.

In the same manner as in FIG. 5, the signal HSYO obtained by the PLL circuit 100 is supplied to the clock terminal CK of the D-type flip-flop 661 via the inverter 663.

In this embodiment, the decoder 36 including the NAND gate 361 and the NOR gate 362 is used in place of the decoder 3 in FIG. NAND gate 361 functions in the same manner as NAND gate 351 of FIG.

The output Q ₉ of the counter 2 and the output of the rising edge detection circuit 66 are input to the NOR gate 362 which outputs the reset signal T _R.

By this adjustment, even if the next rising _edge of the vertical synchronizing signal V _syn is detected before the value of the output of the counter 2 reaches 256, the reset signal T _R is outputted and the selection signal SEL returns to LOW. Is secured.

If the regular NISC signal is not supplied to the television as a composite video signal as in the high-definition search of videotape, the next rising _edge of the vertical synchronization signal _Vsyn is detected before the output value of the counter 2 reaches 256. do.

This embodiment functions normally even in such a case.

FIG. 7 shows a combination of a composite synchronous signal C _{sync in} which spurious synchronous signals similar to those in FIG. 10 are mixed, and a combination of a horizontal synchronous signal separation circuit shown in FIG. 3 and a synchronization signal selection circuit shown in FIG. Displays the horizontal sync signal HSYN obtained from the _sync signal C _sync .

As shown in FIG. 7, the separated horizontal synchronizing signal H _syn output from the horizontal synchronizing signal separation circuit is output as the horizontal synchronizing signal HSYN during the vertical retrace interval.

During the display period, the composite synchronization signal C _sync is output as the horizontal synchronization signal HSYN.

According to the characteristics of the composite synchronization signal, the vertical synchronization signal and the equalization pulse are present in the composite synchronization signal, and the spurious synchronization signal is mixed with the composite synchronization signal only during the vertical blanking interval.

Therefore, the use of the composite synchronization signal C _sync during the display period according to the present invention depends on the characteristics of the composite synchronization signal.

11 shows a fourth embodiment of the present invention. The synchronization signal selecting circuit 1 of this embodiment includes a first pulse generating circuit PG ₁ and a second pulse generating circuit PG ₁ . The pulse generating circuits PG ₁ and PG ₂ generate pulses at the output Q in synchronization with the potential rise at their input B.

The vertical synchronizing signal V _{syn, which} is separated from the composite synchronizing signal C _sync , is input to the input B of the pulse generating circuits PG ₁ and PG ₂ .

The output pulse 1 of the first pulse generating circuit PG ₁ is connected to the first input terminal of the AND gate 702 via the inverter 701.

The output pulse 2 of the second pulse generating circuit PG ₂ is directly connected to the other input terminal of the AND gate 702.

The output of the AND gate 702 is input to the terminal S of the selector 5 as the selection signal SEL. The operation of this embodiment is described with reference to FIG.

As described above, the period from one vertical synchronous signal 25 to the next vertical synchronous signal 25 is a scanning period of one field, but the display period while the display is actually executed is a scanning as shown in FIG. It is part of the period.

The display period starts with the number of elapsed edges of the vertical synchronization signal 25 at the time T _B , and ends with the elapse of the period of the time T _E.

In this embodiment, the pulse pulsel is generated by the first pulse generating circuit PG ₁ so that its pulse width is approximately equal to the period of time T _B.

The pulse pule2 is generated by the second pulse generating circuit PG ₂ so that its pulse width is approximately equal to the period of time T _E.

Therefore, as shown in FIG. 12, the selection signal SEL output from the AND gate 702 becomes HIGH only during the display period in the scanning period of one field.

For this reason, the composite synchronization signal C _sync is selected and output as the output of the selector 5 during the display period, and during the period where the horizontal synchronization signal H _syn separated by the horizontal synchronization signal separation circuit 10 is different from the display period. Is selected and output.

FIG. 13 shows a circuit diagram of the configuration in which the first pulse generating circuit PG ₁ and the second pulse generating circuit PG ₂ in the embodiment of FIG. 11 are realized by two Monstable multivibrators 703 and 704. FIG.

In this case, the inverter 701 of FIG. 11 is not used, and pulse pulses are obtained directly at the output of the inverted logic output Q of the monotonous multiple oscillator 703.

In this example, the width of each pulse is determined by appropriately setting the time constants determined by capacitors C ₁ and C ₂ and resistors R ₁ and R ₂ .

In general, the error is large in the control of the pulse width determined by the time constants of C and R.

Since it is not necessary to strictly control the widths of the pulses pulses 1 and 2 as follows, even if the pulse widths are determined in advance by the time constants of C and R, there is no problem in the practical application.

14 shows a fifth embodiment of the present invention.

In this embodiment, the output of the first pulse generating circuit PG ₁ is input to the second pulse generating circuit PG ₂ via the inverter 705, and the output of the second pulse generating circuit PG ₂ is connected to the selector 5. It is entered in terminal S.

The operation of this embodiment will be described with reference to FIG.

In Fig. 15, T _B is the time period from the rise of the vertical synchronization signal V _syn to the start of the display period, and T _DIS is the display period.

The first pulse generating circuit PG ₁ generates a pulse pulsel of width T _B at the rise of the vertical synchronizing signal V _syn , and the second pulse generating circuit PG ₂ has a width T _DIS at the rising edge of the inverted signal pulsel of the pulse pulse. Generate pulse pulse 2 (ie the falling edge of pulse pulse 1).

This pulse 2 is supplied to the terminal S of the selector 5 as the selection signal SEL.

Thus, the composite signal C _sync is selected and output as the output of the selector 5 during the display period, and the horizontal synchronous signal H _syn separated by the horizontal synchronous signal separation circuit 10 is publicly selected for a period different from the display period. do.

In theory, it is preferable that the HIGH-level of the selection signal SEL shown in FIG. 12 and FIG. 15 coincides with the display period.

That is, it is preferable that the rising and falling positions of the selection signal SEL coincide with the start position and end position of the display period, respectively.

However, if the HIGH-level period of the selection signal SEL occupies a major part of the display period, there is no problem in practical application.

Thus, it is not necessary to strictly control the width of pulses pulse 1 and pulse 2.

FIG. 16 shows a circuit diagram of the configuration in which the first and second pulse generating circuits PG ₁ and PG ₂ in the embodiment of FIG. 14 are realized by the forging multiple oscillators 706 and 707. FIG.

In this case, FIG. 14 shows that the inverter 705 is not used, and pulse pulse 1 is obtained directly at the output of the inverted logic output Q of the monotonous multiple oscillator 706.

FIG. 17 shows the variation of the view in FIG. In the example shown in FIG. 17, the vertical synchronizing signal V _syn is input to the CLR input of the forging multiple oscillator 707 via the inverter 708.

Although the next rise of the vertical synchronizing signal V _syn occurs during the output of the forging multiple oscillator 707 (i.e., the selection signal SEL) for HIGH days, the forging multiplexer 707 is reset at this time.

Thus, the horizontal synchronizing signal H _syn is output from the selector 5 as the horizontal synchronizing signal HSYN until the next rise of the selection signal SEL at that time.

For this reason, it is possible to prevent the vertical synchronization signal included in the composite synchronization signal C _sync or the spurious synchronization signal shown in FIG. 10 from being output as the horizontal synchronization signal HSYN.

This occurs when another signal in the normal NTSC signal is input as a composite video signal as in the video tape special effect reproduction (high speed search, power, etc.), but this embodiment functions even under this condition normally.

According to the present invention, a synchronizing signal selection circuit which can obtain a good horizontal synchronizing signal from a composite synchronizing signal is characterized by using a horizontal synchronizing signal and a compound synchronizing signal in which pulses generated by noise and other signals are separated from the composite synchronizing signal, respectively. Even when mixed with a composite synchronization signal, it is provided.

By using the synchronization signal selection circuit of the present invention, a high resistance to noise can be achieved in a display device such as an LCD device in which it is necessary to obtain a sampling clock signal from the composite synchronization signal.

In the prior art, it was necessary to raise the spurious equalization pulse or the equalization pulse in the response characteristic of the PLL circuit, the composite synchronization signal C _sync in order to absorb the interference caused by the vertical synchronization signal, but this is the effect of the so-called water on the weak electric field (video image). Has oscillation from side to side).

In the prior art, it was not possible to solve this problem.

By combining the present invention with the horizontal synchronous signal separation circuit, this problem can be solved, and the ideal design can be freely implemented even with respect to the influence of water.

The present invention not only solves the problem of video reproduction, but also can greatly contribute to the display quality and improved performance of the LCD device.

It is understood that various modifications will be apparent to and can be readily made by them to those skilled in the art without departing from the scope and spirit of the invention.

Accordingly, the claims appended hereto are limited to those described herein, but rather the claims are patentable novelty present in the present invention, including all features which are equally treated by such persons familiar with the art to which this invention belongs. To understand all the characteristics of

Claims (12)

In response to the input of the vertical synchronizing signal extracted from the composite synchronizing signal, generating a control signal in a predetermined state for a predetermined period, the predetermined period starting when a first predetermined time elapses after the input of the vertical synchronizing signal; The control signal generating means is terminated when a second predetermined time elapses after the input of the vertical synchronization signal, and the compound synchronization signal is substantially different from the horizontal synchronization signal separated from the compound synchronization signal for a period other than the predetermined period. And; And input the composite synchronization signal, the separated horizontal synchronization signal and the control signal to output the composite synchronization signal when the control signal is in the predetermined state, and the control signal is in a state other than the predetermined state. And selecting means for outputting the separated horizontal synchronizing signal when the signal is present. The synchronization signal selecting circuit of claim 1, wherein the first predetermined time is shorter than the second predetermined time. 2. The apparatus of claim 1, wherein the control signal generating means comprises: counting means for inputting a periodic pulse string and counting a plurality of pulses included in the periodic pulse string; Connected to the output of the counting means, generating a set signal when the output of the counting means becomes a first predetermined value corresponding to the first predetermined time, and the output of the counting means corresponds to the second predetermined time Decoding means for generating a reset signal when the second predetermined value is obtained; And setting means connected to an output of the decoding means to set the control signal to the predetermined state in response to the set signal, and to set the control signal to a state other than the predetermined state in response to the reset signal. Synchronization signal selection circuit comprising a. 4. The synchronization signal selection circuit according to claim 3, wherein said counting means is reset by a rising edge of said vertical synchronization signal. The method of claim 1, wherein the control signal generating means generates a first pulse signal in response to the input of the vertical synchronous signal, the first pulse signal is the first predetermined time after the input of the vertical synchronous signal First pulse signal generating means for terminating when elapsed; Second pulse signal generating means for generating a second pulse signal in response to the input of the vertical synchronization signal, the second pulse signal ending when the second predetermined time elapses after the input of the vertical synchronization signal; And means for generating the control signal based on the first and second pulse signals. The method of claim 1, wherein the control signal generating means generates a first pulse signal in response to the input of the vertical synchronization signal, wherein the first predetermined time has elapsed after the input of the vertical synchronization signal. A first pulse signal generating means, which terminates when finished; Second pulse signal generating means for generating a first pulse signal in response to an end of the first pulse signal, wherein the second pulse signal ends when the second predetermined time elapses after the first pulse signal ends; And; And means for generating the control signal based on the first and second pulse signals. 2. The synchronization signal selection circuit according to claim 1, further comprising a phase-locked loop (PLL) means for inputting the output of said selection means and outputting a periodic pulse string as a clock signal to said control signal generating means. 8. The apparatus of claim 7, wherein the PLL means comprises: voltage controlled oscillation means for generating the clock signal; Frequency dividing means connected to said voltage controlled oscillation means for dividing said clock signal; Phase comparison means connected to said selection means and said frequency division means for generating a phase comparison signal in accordance with an output of said selection means and said divided clock signal; And low-pass filter means connected to said phase comparing means to filter said phase comparison signal and to output said filtered phase comparison signal to said voltage controlled oscillation means. Input the vertical synchronous signal and the periodic pulse string extracted from the composite synchronous signal, and count the number of pulses included in the periodic pulse string after the input of the vertical synchronous signal to output a count signal indicating the counted number of pulses. Counting means; Coupled to the output of the counting means, the counting signal being decoded to output a set signal and a reset signal defining a predetermined period, wherein the composite synchronization signal is separated from the composite synchronization signal during a period other than the predetermined period. Decoding means substantially different from the horizontal sync signal; A control signal is generated in accordance with the set signal and the reset signal, wherein the state of the control signal during the predetermined period is different from the state of the control signal during the period other than the predetermined period. Different from the generating means; A synchronization means including inputting the composite synchronization signal, the separated horizontal synchronization signal and the control signal, and selectively outputting any one of the composite synchronization signal or the separated horizontal synchronization signal according to the state of the control signal; Signal selection circuit. 10. The synchronization signal selection circuit according to claim 9, wherein said counting means is reset by a rising edge of said vertical synchronization signal. First pulse signal generating means for generating a first pulse signal in response to an input of a vertical synchronization signal extracted from the composite synchronization signal; Inverting means connected to an output of said first spread signal generating means for inverting said first pulse signal; A second pulse signal is generated in response to the input of the vertical synchronization signal, wherein the first and second pulse signals define a predetermined period, and the composite synchronization signal is separated from the composite synchronization signal for a period other than the predetermined period. Second pulse signal generating means, substantially different from the horizontal sync signal generated; A control signal is connected to an output of the inverting means and to an output of the second pulse signal generating means, wherein a control signal is generated according to the inverted first pulse signal and the second pulse signal. Generating means, wherein the state is substantially different from the state of the control signal during a period other than the predetermined period; A synchronization means including inputting the composite synchronization signal, the separated horizontal synchronization signal and the control signal, and selectively outputting any one of the composite synchronization signal or the separated horizontal synchronization signal according to the state of the control signal; Signal selection circuit. First pulse signal generating means for generating a first pulse signal in response to an input of a vertical synchronization signal extracted from the composite synchronization signal; Inverting means connected to an output of said first pulse signal generating means for inverting said first pulse signal; A control signal generated according to the inverted first pulse signal, wherein the state of the control signal for the predetermined period is equal to the state of the control signal for a period other than the predetermined period; Different generating means, wherein said composite synchronizing signal is substantially different from a horizontal synchronizing signal separated from said composite synchronizing signal for a period other than said predetermined period; A synchronization means including inputting the composite synchronization signal, the separated horizontal synchronization signal and the control signal, and selectively outputting any one of the composite synchronization signal or the separated horizontal synchronization signal according to the state of the control signal; Signal selection circuit.