JPH08235789A - Pll circuit - Google Patents

Abstract

PURPOSE: To obtain a PLL circuit in which the followupability for phase deviation of a horizontal synchronizing signal is good. CONSTITUTION: A PLL circuit 10 is constituted of a phase detecting circuit 1, a low pass filter 2, a voltage control oscillator 3, and a variable frequency dividing circuit 4. Position deviation of a horizontal synchronizing signal inputted to the phase detecting circuit 1 is detected by an AND gate 6, a frequency dividing ratio of the variable frequency dividing circuit 4 is changed by an output of this AND gate 6 and deviation of a phase of a horizontal synchronizing signal is absorbed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit which performs display control on a display device based on a video signal from a video tape recorder or the like.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 7, a video signal from a video tape recorder 31 is sent to a display device 33 under the control of a PLL circuit 32 and displayed on the screen of the display device 33.

The PLL circuit 32 will be described in detail below. FIG. 8 shows a PLL (Phas) used when displaying a television video signal on a display device 33 such as a liquid crystal display.
eLocked Loop) circuit 32, which is a horizontal synchronization signal H-sy input to one input terminal.
nc and the frequency division output signal fs /
A phase detection circuit 21 for detecting a phase difference from N, and a low pass filter 22 for taking in a phase difference signal detected by the phase detection circuit 21 to remove high frequency components and converting it into a DC voltage. , A voltage controlled oscillator (VCO: Voltage Co) that changes the oscillation frequency according to the voltage value of the DC voltage from the low-pass filter 22 to generate the sampling clock fs.
controlled oscillator 23 and the sampling clock fs from this voltage controlled oscillator 23, and divides it by 1 / N (N is an integer) to divide the frequency-divided output signal fs / N into the other input terminal of the phase detection circuit 21. And a frequency dividing circuit 24 for transmitting the

The operation of the PLL circuit 32 shown in FIG. 8 is shown in FIG.
This will be described below with reference to the timing chart shown in FIG.

The phase detection circuit 21 has a horizontal synchronizing signal H.
-Sync and the frequency division output signal fs / N from the frequency division circuit 24
And the phase difference (rising) of the two signals is compared, and the phase difference signal of both signals is sent to the low-pass filter 22. Low pass filter 22
Takes in the phase difference signal, removes the high frequency component, converts it into a DC voltage, and sends it to the voltage controlled oscillator 23. The voltage controlled oscillator 23 changes the oscillation frequency according to the voltage value of the DC voltage from the low pass filter 22 and generates the sampling clock fs. This sampling clock fs is divided into 1 / N by the frequency dividing circuit 24 and the divided output signal f
It is input to the phase detection circuit 21 as s / N. By such an operation, the sampling clock fs having a frequency N times the horizontal synchronizing signal H-sync can be taken out from the voltage controlled oscillator 23, and the horizontal synchronizing signal H-
A sampling clock fs, which is synchronized with sync and has a frequency N times, can be used to generate sampling data corresponding to each pixel of a dot matrix display device. The counter reset signal shown in FIG. 9 is a signal for resetting a counter (not shown) provided in the frequency dividing circuit 24.

[0006]

However, in the case of the above-mentioned PLL circuit 32, in a normal operation, as shown in FIG. 9, one horizontal scanning period (1) of the horizontal synchronizing signal H-sync is used.
H) (about 63.5 μs), divided output signal fs / N
However, for example, when the video tape recorder is repeatedly played back while the video tape recorder is heated to a high temperature, when switching the head of each field of the video head (indicated by a black triangle mark in FIG. 10). One horizontal scanning period of the horizontal synchronizing signal H-sync in (shown) becomes 1H + ΔH due to the deformation of the video tape, and becomes longer than the normal one horizontal scanning period (1H).

In this case, the PLL circuit 32 shown in FIG.
The phase of the frequency-divided output signal fs / N corresponds to the change of the horizontal synchronizing signal H-sync in one horizontal scanning period, and the horizontal synchronizing signal H-
Although it operates so as to reduce the oscillation frequency of the voltage controlled oscillator 2 in order to match the phase of sync, the response speed of the voltage controlled oscillator 2 is also limited due to the time constant of the feedback loop of this PLL circuit 32. , Divided output signal fs /
There is a problem that the image on the screen of the display device is distorted or the PLL circuit 32 malfunctions until N becomes in phase with the horizontal synchronizing signal H-sync.

Therefore, the present invention provides a PLL circuit capable of quickly absorbing the positional deviation of the timing signal and avoiding the occurrence of image distortion and malfunction of the image on the screen of the display device.

[0009]

According to the first aspect of the present invention,
In a PLL circuit composed of a phase detection circuit, a low-pass filter, a voltage controlled oscillator, and a variable frequency divider circuit, a detection circuit for detecting a positional deviation of a timing signal input to the phase detection circuit, and a detection output of this detection circuit. And a control circuit for changing the frequency division ratio of the variable frequency dividing circuit.

According to a second aspect of the invention, the PLL circuit according to the first aspect of the invention is connected to the video tape recorder and the dot matrix type display device, and the timing signal is a horizontal synchronizing signal supplied from the video tape recorder. The sampling clock of the dot matrix type display device is created from the output of the voltage controlled oscillator.

According to another aspect of the PLL circuit of the present invention, the position shift of the timing signal inputted to the phase detecting circuit is detected by the detecting circuit, and the control circuit detects the output of the detecting circuit to detect the output of the variable frequency dividing circuit. Since the frequency division ratio is changed, it is possible to send the frequency division output signal that follows the positional deviation of the input timing signal to the phase detection circuit, and quickly absorb the positional deviation of the timing signal. it can. That is, when the positional deviation of the timing signal is large, a frequency division output signal having a large frequency division ratio 1 / M is sent to the phase detection circuit. When the displacement of the timing signal is small, a frequency division output signal having a small frequency division ratio 1 / N is sent to the phase detection circuit.

According to the PLL circuit of the second aspect, the PLL circuit of the first aspect of the invention is connected to the video tape recorder and the dot matrix type display device, and the timing signal is supplied from the video tape recorder. Since it is a synchronizing signal, and the sampling clock of the dot matrix type display device is created from the output of the above voltage controlled oscillator, the frequency division output signal that follows the phase shift of the horizontal synchronizing signal when switching the video head detects the phase. By being sent to the circuit, it is possible to generate a sampling clock corresponding to the phase shift of the horizontal synchronizing signal, and it is possible to avoid the occurrence of distortion and malfunction of the image on the screen of the dot matrix type display device.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below.

FIG. 1 shows a PLL which is an embodiment of the present invention.
1 shows a circuit 10. The PLL circuit 10 is connected to a video tape recorder 8 and a dot matrix type display device 9 and receives a horizontal synchronizing signal H-sync which is a timing signal from the video tape recorder 8. Then, the sampling clock fs for the display device 9 is generated.

The PLL circuit 10 detects a phase difference between a horizontal synchronizing signal H-sync input to one input terminal and a frequency divided output signal fs / N or fs / M from a variable frequency dividing circuit 4 which will be described later. Phase detecting circuit 1 and the phase detecting circuit 1
A low-pass filter 2 that takes in the phase difference signal detected by the above, removes high frequency components, and converts it into a DC voltage;
A voltage-controlled oscillator 3 that changes the oscillation frequency according to the voltage value of the DC voltage from the low-pass filter 2 to generate a sampling clock fs, and a sampling clock fs from the voltage-controlled oscillator 3 are taken in to divide by N. 1 or 1 / M (N and M are integers: N <M) and the divided output signal fs / N or divided output signal fs / M is sent to the other input terminal of the phase detection circuit 1. A variable frequency dividing circuit 4 having a frequency dividing ratio switching control function for transmitting a gate signal according to the frequency dividing ratio, and the horizontal synchronizing signal H-sy.
nc and the gate signal from the variable frequency dividing circuit 4 are obtained to detect the phase shift of the horizontal synchronizing signal H-sync, and the detection result is sent to the variable frequency dividing circuit 4 by the AND gate 6. It has.

Next, the operation of the PLL circuit 10 will be described with reference to the timing charts shown in FIGS. 2 and 3 which show the signal generation timing of each part of the PLL circuit 10.

As shown in FIG. 2, the change amount ΔH1 in one horizontal scanning period (1H + ΔH1) when the video head of the video tape recorder is switched is relatively small, and the horizontal synchronization is within the time width within which the gate signal is generated. Signal H
If -sync occurs, the AND gate 6
Output signal becomes "1", at which time the frequency division ratio of the variable frequency dividing circuit 4 is set to 1 / N.
The frequency-divided output signal fs / N is sent to the phase detection circuit 1. In this case, the phase difference between the horizontal synchronizing signal H-sync and the frequency-divided output signal fs / N is small as shown in FIG. 2, so that the PLL circuit can easily follow the variation .DELTA.H1.

Next, as shown in FIG. 3, the change ΔH2 in one horizontal scanning period (1H + ΔH2) at the time of switching the video head of the video tape recorder becomes large, and the horizontal synchronizing signal H-sync produces the gate signal. If the output signal of the AND gate 6 is out of the range of the specified time width, the frequency dividing ratio of the variable frequency dividing circuit 4 is switched to 1 / M. The frequency division output signal fs / M from the frequency division circuit 4 is the phase detection circuit 1
Sent to As a result, one cycle of the divided output signal fs / M approaches the one horizontal scanning period (1H + ΔH2), and the phase difference between the horizontal synchronizing signal H-sync and the divided output signal fs / M is short and the PLL circuit is short. Absorbed by 10.

Next, details of the variable frequency dividing circuit 4 in the PLL circuit 10 shown in FIG. 1 will be described in detail with reference to FIG.

The variable frequency dividing circuit 4 shown in FIG. 4 takes in the sampling clock fs from the voltage controlled oscillator 3 and counts up, and decodes the count output by this counter 11 to divide into 1 / M. The corresponding divided signal a and the divided signal b corresponding to 1 / N division,
Gate signal Ga corresponding to 1 / M frequency division, gate signal Gb corresponding to 1 / N frequency division, reset signal Ra corresponding to 1 / M frequency division and reset signal corresponding to 1 / N frequency division Rb, a decoder 12 that outputs a 1/2 · H signal having a cycle that is a half cycle different from the horizontal synchronization signal H-sync,
Either the divided signal a or the divided signal b from the decoder 12 is selected and the divided output signal fs / M or the divided output signal f is selected.
The first selector 13a which is sent to the phase detection circuit 1 as s / N and the second selector 13a which selects either the gate signal Ga or the gate signal Gb from the decoder 12 and sends it to the AND gate 6 as a gate signal. Selector 13b
And a third selector 13c that selects either the reset signal Ra or the reset signal Rb from the decoder 12 and sends it to the reset terminal R of the counter 11 as a counter reset signal, and the output signal of the AND gate 6 to the reset terminal. In addition, the RS flip-flop 14 which inputs the 1 / 2.H signal from the decoder 12 to the set terminal and sends out the output signal having the waveform shown in FIG. The output signal of the S-flip-flop 14 is input to the input terminal D, and the output signal having the waveform shown in FIG. 5 or 6 is output from the output terminal Q to the first to third selectors 13.
and a D-flip-flop 15 for sending to each set terminal S of a to 13c. 1 from the decoder 12
The / 2 · H signal is also sent to the clock input terminal of the D-flip-flop 15.

The first selector 13a is a decoder 1
The divided signal a and the divided signal b from 2 are input terminals A and B, respectively.
From the D-flip-flop 15 and the output signal sent from the D-flip-flop 15 to the set terminal S is high (= 1), the frequency-divided signal a is sent as the frequency-divided output signal fs / M, and the D-flip-flop 15 sets When the output signal sent to the terminal S is low (= 0), the divided signal b is divided into the divided output signal f.
It is sent as s / N.

The second selector 13b is the decoder 1
When the output signal sent from the D-flip-flop 15 to the set terminal S is high (= 1), the gate signal Ga and the gate signal Gb from 2 are fetched from the input terminals A and B, respectively. When the output signal sent from the D-flip-flop 15 to the set terminal S is low (= 0), the gate signal Gb is sent as a gate signal.

The third selector 13c takes in the reset signal Ra and the reset signal Rb from the decoder 12 from the input terminals A and B, respectively, and the output signal sent from the D-flip-flop 15 to the set terminal S is high ( = 1), the reset signal Ra is sent to the counter 11 as a counter reset signal, and when the output signal sent from the D-flip-flop 15 to the set terminal S is low (= 0), the reset signal Rb is used as a counter reset signal. It is designed to be sent to the counter 11.

Next, the operation of the PLL circuit 10 using the variable frequency dividing circuit 4 shown in FIG. 4 will be described with reference to FIGS. In FIG. 5, the horizontal sync signal H-sync is correctly 1
FIG. 6 shows a timing chart of signals of respective parts of the variable frequency dividing circuit 4 when the signal is generated in the cycle of the horizontal synchronizing period (1H). FIG. 6 shows that the horizontal synchronizing signal H-sync is 1 when the video head of the video tape recorder is switched. 6 is a timing chart of signals of respective parts of the variable frequency dividing circuit 4 in the case of occurring in a cycle of (1H + ΔH) delayed from the horizontal synchronization period (1H).

As shown in FIG. 5, the horizontal synchronizing signal H-sy
When nc is correctly generated in a cycle of one horizontal synchronization period (1H), the sampling clock fs from the voltage controlled oscillator 3 is counted up by the counter 11,
The decoder 12 decodes the count output from the counter 11 and outputs a 1 / 2.H signal whose 1/2 cycle is shifted from the horizontal synchronizing signal H-sync to the RS flip-flop 14.
Sent to the set terminal of this RS flip-flop 1
The output signal of 4 is set (high) as shown in FIG.
Further, the RS flip-flop 14 is reset as shown in FIG. 5 when the logical product of the gate signal from the second selector 13b by the AND gate 6 and the horizontal synchronizing signal H-sync is high. To be done.

Such an RS flip-flop 14
The output signal of the D-flip-flop 15 is input to the D-flip-flop 15, but at the timing when the second 1 / 2.H signal shown in FIG. Since the output signal of 14 rises from low to high, the output signal of the D-flip-flop 15 is low.
When the output signal of the flip-flop 15 is low, the first selector 13a selects the frequency-divided signal b corresponding to the frequency division ratio of 1 / N and uses it as the frequency-divided output signal fs / N to detect the phase. To the circuit 1, the second selector 13b selects the gate signal Gb and sends it to the AND gate 6 as a gate signal, and the third selector 13c.
Selects the reset signal Rb and sends it to the counter 11 as a counter reset signal.

On the other hand, as shown in FIG. 6, the horizontal synchronizing signal H
-Sync is later than one horizontal synchronization period (1H) (1
(H + ΔH), the decoder 12 decodes the count output from the counter 11 and outputs a 1/2 · H signal that is a 1/2 cycle offset from the horizontal synchronizing signal H-sync to the RS flip-flop 14. The output signal of the RS flip-flop 14 is sent to the set terminal and set (high) as shown in FIG. 6, but the horizontal synchronizing signal H-sync with a phase delay is output from the second selector 13b. Since the phase of the gate signal is delayed, the logical product of the gate signal from the second selector 13b by the AND gate 6 and the horizontal synchronizing signal H-sync becomes low, and as a result, R-S- Flip flop 1
The output signal of 4 remains high and is input to the D-flip-flop 15. The D-flip-flop 15 takes in the output signal of the RS-flip-flop 14 and outputs a high output signal for a certain period as shown in FIG. 6 based on the 1 / 2.H signal input to the clock terminal. The signal is sent to each set terminal S of the first to third selectors 13a to 13c.

As a result, the first selector 13a
Selects a frequency-divided signal a corresponding to a frequency division ratio of 1 / M and sends it to the phase detection circuit 1 as a frequency-divided output signal fs / M. The second selector 13b causes the second selector 13b to output the gate signal Ga.
And select it as the gate signal
The third selector 13c selects the reset signal Ra and sends it to the counter 11 as a counter reset signal.

Since N and M have a relation of N <M, each cycle of the frequency-divided output signal fs / M, the gate signal, and the counter reset signal is longer than one horizontal scanning period (1H). As a result, the horizontal synchronization signal H-sync
6, the horizontal synchronizing signal H-sync becomes in phase with the gate signal as shown in FIG. 6, and the AND gate 6 resets the RS flip-flop 14 and the output of the D-flip-flop 15. The signal also changes to low, and the first to third selectors 13a to 13c output the frequency division output signal fs / N corresponding to the frequency division ratio of 1 / N, the gate signal, and the counter reset signal as in the case already described. Return to the sending state.

In the above-described embodiment, the frequency division ratio of the variable frequency dividing circuit 4 is switched only during one horizontal scanning period when the video head of the video tape recorder 8 is switched, but one horizontal scanning when the video head is switched. The same processing as that described above can be performed for several horizontal scanning periods following the period.

[0031]

According to the first aspect of the present invention, the frequency division output signal that follows the positional deviation of the input timing signal can be sent to the phase detection circuit, and the positional deviation of the timing signal can be accelerated. It is possible to provide a PLL circuit that can be absorbed by the above.

According to the second aspect of the invention, the frequency division output signal following the phase shift of the horizontal synchronizing signal supplied from the video tape recorder is sent to the phase detecting circuit, and the phase of the horizontal synchronizing signal is changed. It is possible to provide a PLL circuit capable of generating a sampling clock corresponding to the shift of the deviation and avoiding the occurrence of image distortion and malfunction of the image on the screen of the dot matrix type display device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a signal generation timing of each part in the PLL circuit according to the embodiment of the present invention.

FIG. 3 is a timing chart showing another example of signal generation timing of each part of the PLL circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a variable frequency dividing circuit in the PLL circuit according to the embodiment of the present invention.

FIG. 5 is a timing chart of signals at various parts during normal operation of the variable frequency divider circuit in the PLL circuit according to the embodiment of the present invention.

FIG. 6 is a timing chart of signals at various parts during phase delay operation of the variable frequency divider circuit in the PLL circuit according to the embodiment of the present invention.

FIG. 7 is a block diagram showing a general application example of a PLL circuit.

FIG. 8 is a block diagram showing a conventional PLL circuit.

FIG. 9 is a timing chart showing another example of signal generation timing of each part of the conventional PLL circuit.

FIG. 10 is a timing chart showing another example of signal generation timing of each part of the conventional PLL circuit.

[Explanation of symbols]

 1 Phase Detection Circuit 2 Low Pass Filter 3 Voltage Controlled Oscillator 4 Variable Divider Circuit 6 AND Gate 8 Video Tape Recorder 9 Display Device 10 PLL Circuit 11 Counter 12 Decoder 13a First Selector 13b Second Selector 13c Third Selector 14 R -S-flip-flop 15 D-flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04N 5/765 H04N 5/91 L

Claims (2)

[Claims] 1. A PLL circuit including a phase detection circuit, a low-pass filter, a voltage controlled oscillator, and a variable frequency divider circuit, and a detection circuit for detecting a positional deviation of a timing signal input to the phase detection circuit, And a control circuit for changing the frequency division ratio of the variable frequency dividing circuit according to the detection output of the detection circuit.
LL circuit. 2. A video tape recorder and a dot matrix type display device, wherein said timing signal is a horizontal synchronizing signal supplied from the video tape recorder, and sampling of the dot matrix type display device is performed from the output of said voltage controlled oscillator. The PLL circuit according to claim 1, wherein a clock is generated.