JP3199933B2 - Tuning circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuning circuit for a television or the like.

[0002]

2. Description of the Related Art Conventionally, in a channel selecting circuit of a TV or the like, a synchronous signal detecting circuit may provide a sampling point after a predetermined time from a leading edge of a horizontal blanking signal to determine the presence or absence of a horizontal synchronous signal. Many.

In order to display a selected channel, a method of displaying a reception channel number at a corner on a TV screen is often adopted. However, T for popular machines
In the case of V, in order to simplify the circuit, the selected channel is displayed by displaying a bar-shaped image for channel selection display on the TV screen.

FIG. 4 shows a state where a reception channel is displayed on a TV screen. In FIG. 4, reference numeral 19 denotes a TV screen. Reference numeral 20 denotes a bar-shaped image for channel selection display, and reference numeral 21 denotes a channel number, which is usually printed on a cabinet. The reception channel can be represented by the bar-shaped image 20 for channel selection display and the channel number 21. The bar-shaped image 20 for channel selection display moves right or left on the TV screen according to the channel to be received.

[0005] In addition, as the frequency of the system clock, only a single frequency is supported. For example, a clock having a constant frequency from a crystal oscillator, a ceramic oscillator, a CR oscillator, or another device is used as a system clock.

[0006]

However, in the conventional channel selection circuit, a sample point is provided after a fixed time fixed from the leading edge of the horizontal blanking signal to determine the presence or absence of the horizontal synchronization signal. Due to the fluctuation of the clock frequency and the characteristics of the sync separation circuit and horizontal AFC circuit,
Since the horizontal blanking signal varies with respect to the horizontal synchronization signal, there is a problem that an optimum sampling point cannot be selected. In addition, in the channel selection circuit for popular equipment, the reception channel is displayed by the positional relationship between the bar-shaped image for channel selection display and the channel number printed on the cabinet. The horizontal blanking signal fluctuates with respect to the horizontal synchronizing signal due to the characteristics of the sync separation circuit and the horizontal AFC circuit. There is a point.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has as its object to provide a channel selection circuit capable of selecting an optimum sampling point and accurately displaying a reception channel.

[0008]

In order to achieve the above object, the invention according to claim 1 provides a sampling point for detecting a horizontal synchronizing signal having a leading edge of a horizontal blanking signal as a reference point. It is made variable by a signal.

Specifically, a solution means taken by the invention of claim 1 is a counter for a channel selection circuit, which is reset at a leading edge of a horizontal blanking signal and counts a system clock, and a counter output from the counter. A synchronization signal sampling means for sampling a horizontal synchronization signal when an output value reaches a counter selection value selectively determined by an external sampling point selection signal; By changing the value, the timing at which the synchronization signal sampling means samples the horizontal synchronization signal can be changed.

[0010] Further, according to the invention of claim 2, the position of the channel selection display image on the TV screen is made variable by an external signal.

A second aspect of the present invention is the invention according to the first aspect of the present invention, wherein an up / down counter for counting the system clock and an up / down counter output from the up / down counter are provided. Digital value generation means for selectively generating a digital value based on a channel selection display position selection signal from the outside based on the value, and a counter output value output from the counter, wherein the digital value is generated by the digital value generation means. When the value reaches the value, comprising a channel selection display signal output means for outputting a channel selection display signal superimposed on the video signal, the digital value is changed by the channel selection position selection signal, A configuration is added in which the timing at which the tuning display signal output means outputs the tuning display signal can be changed. Is shall.

Furthermore, the configuration of the invention is claimed in claim 3, specifically, Oite the configuration of the invention of claim 2, wherein the sampling point selection signal and the tuning display position selection signal is the same signal As a result, the counter selection value is changed.
The digital value is changed and the counter selection value is
A change in the timing of sampling of the horizontal synchronization signal in the synchronization signal sampling means caused by the change ;
Also the in which the Ru can be interlocked with change of the timing of the output of the channel selection display signal in the channel selection display signal output means for the digital values occurs being changed.

According to a fourth aspect of the present invention, in the configuration of the first aspect, when the frequency of the system clock is changed, the counter selection value is changed by the sampling point selection signal. Accordingly, a configuration is provided in which the synchronization signal sampling means samples the horizontal synchronization signal at a predetermined timing.

According to a fifth aspect of the present invention, in the configuration of the second or third aspect, when the frequency of the system clock is changed, the counter selection value is set by the sampling point selection signal. Is changed so that the synchronization signal sampling means samples the horizontal synchronization signal at a predetermined timing, and the digital value is changed by the tuning display position selection signal, whereby the channel selection display is changed. A signal output means for outputting the channel selection display signal at a predetermined timing.

[0015]

According to the configuration of the first aspect of the present invention, when the counter is reset at the leading edge of the horizontal blanking signal and counting is started, and when the counter output value of the counter reaches the selectively selected counter value, the synchronization signal is output. The sampling means samples the horizontal synchronization signal. Here, by changing the counter selection value by an external sampling point selection signal, the timing at which the synchronization signal sampling means samples the horizontal synchronization signal can be changed. This makes it possible to arbitrarily select a sampling point for detecting a horizontal synchronization signal using the sampling point selection signal as a control signal.

Further, according to the configuration of the second aspect of the present invention, the digital value generation means selectively generates a digital value based on the output value of the up / down counter output from the up / down counter. The counter is reset at the leading edge of the horizontal blanking signal and starts counting,
When the counter output value of the counter reaches the digital value, the channel selection display signal output means outputs a channel selection display signal. Then, by superimposing the channel selection display signal on the video signal, for example, a bar-shaped image for channel selection display is displayed on the TV screen. Here, by changing the digital value generated by the digital value generation means with an external selection display position selection signal, the timing at which the selection display signal output means outputs the selection display signal is changed. be able to. This makes it possible to arbitrarily select the position on the TV screen of the bar-shaped image for tuning display corresponding to the tuning display signal using the tuning display position selection signal as a control signal.

[0017] In addition, when the Ru good to the configuration of the invention of claim 3,
The sampling point selection signal and the tuning display position selection signal are the same.
By changing to a single signal, the counter selection value can be changed.
Accordingly, the digital value generated by the digital value generation means changes.
Will be updated. The timing of the sampling of the horizontal synchronization signal in the synchronization signal sampling means and the timing of the output of the tuning display signal in the tuning display signal output means are both determined with reference to the leading edge of the horizontal blanking signal. Change the counter selection value
The sampling timing of the horizontal synchronizing signal in the synchronizing signal sampling means and the change in the counter selection value.
In addition, the channel display signal generated when the digital value is changed
This can be linked with a change in the output timing of the channel selection display signal in the signal output means . This makes it possible to link the sampling point for detecting the horizontal synchronization signal with the position of the bar-shaped image for channel selection display on the TV screen.

According to the fourth and fifth aspects of the invention, even when the frequency of the system clock is changed, the counter selection value is changed by the sampling point selection signal, and the digital value is changed by the channel selection position selection signal. By changing the timing, it is possible to select a timing at which an optimum sampling point is obtained, and it is possible to output a channel selection display signal at a timing at which an accurate reception channel can be displayed.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a channel selecting circuit according to an embodiment of the present invention.

FIG. 1 shows the configuration of the tuning circuit of the above embodiment. In FIG. 1, reference numeral 1 denotes a D flip-flop for synchronizing a horizontal blanking signal. Reference numeral 2 denotes a D flip-flop for further delaying the output of the D flip-flop 1 by one clock. An inverter 3 inverts the synchronized horizontal blanking signal. Reference numeral 4 denotes an AND circuit, which generates a reset signal to the counter 5. Comparator 6 as synchronization signal sampling means
Determines whether or not there is a horizontal synchronizing signal based on a counter value determined by a sample signal from an external terminal, and outputs the result.

The selector 7 selects a constant to be added by the adder 8 based on a sample signal from an external terminal. 9
Is an up / down counter that generates a tuning voltage,
The increment or decrement operation is performed only when the counter enable signal is at a high level, for example. The output of the up / down counter 9 is passed through the divider 10 to the adder 8.
Is added to the constant. Here, the selector 7, the adder 8, and the divider 10 constitute digital value generating means.

The comparator 11 compares the counter output of the counter 5 with the output of the adder 8 and outputs the result if they match. The output signal of the comparator 11 is shaped into a signal for tuning display by the waveform shaping circuit 12. Here, the comparator 11 and the waveform shaping circuit 12 constitute a channel selection display signal output unit.

In this example, a sample signal supplied from an external terminal is supplied to a synchronizing signal detecting section comprising a counter 5 and a comparator 6, and a channel selecting section comprising the counter 5, the digital value generating means and the channel selecting signal output means. It is shared with the display output unit.

FIG. 2 is a timing chart showing an example of the operation of the tuning circuit configured as described above. The clock shown in FIG. 2 is supplied to D flip-flops 1 and 2, a counter 5 and an up / down counter 9. At the leading edge of the horizontal blanking signal, the flip-flops 1 and 2, the inverter 3 and the AND circuit 4 generate a pulse of one clock width. With this pulse, the counter 5 is initialized, and the counter value is incremented by “+1” from “0”.
If the counter value determined by the sample signal from the external terminal is, for example, “4”, and the counter value output from the counter 5 becomes “4”, the comparator 6 determines whether or not there is a horizontal synchronization signal by comparison. At the timing shown in FIG. 2, the synchronization signal detection output goes high, and the horizontal synchronization signal is determined to be "present". If the counter value output from the counter 5 becomes "4", if there is no horizontal synchronizing signal, that is, if the horizontal synchronizing signal is at a low level, it is determined that the horizontal synchronizing signal is "absent", and the synchronizing signal detection output is It remains at low level.

The output of the counter 5 is also input to the comparator 11 for channel selection display at the same time, and the counter value of the up / down counter 9 is, for example, "512".
It is assumed that 0 is “1/128”, and “2” is a constant to be added by the selector 7 by a sample signal from an external terminal.
Is selected, the output of the adder 8 is "6", and the output of the channel selection display comparator 11 is at the high level for one clock at the timing shown in FIG. This output is shaped into a pulse having a width of, for example, 5 clocks by the following waveform shaping circuit 12. That is, a signal that is at a high level by a predetermined width from the timing when the counter value output from the counter 5 reset based on the leading edge of the horizontal blanking signal becomes “6” is output as a channel selection display output,
This channel display output is superimposed on the video signal and used for channel display.

FIG. 3 shows an example of the configuration of a system clock generating circuit for generating a system clock used in the channel selecting circuit of this embodiment. The system clock generation circuit includes a crystal oscillator or a ceramic oscillator and a 1/2 frequency divider. Although the frequency divider is a 1/2 frequency divider in this example, a 1 / N frequency divider (where N is a positive integer) may constitute a system clock generating circuit.

In FIG. 3, reference numeral 13 denotes an oscillation inverter. Reference numeral 14 denotes a feedback resistor, which includes a first oscillation terminal and a second oscillation terminal.
By connecting a crystal oscillator or a ceramic oscillator to the oscillation terminal of, it is possible to oscillate at a certain frequency. Reference numeral 15 denotes a buffer. The clock that has passed through the buffer 15 is supplied to a １ ／ frequency divider 16 and a selector 17. Then, a source oscillation clock or a clock after 1/2 frequency division is selected by a signal from an external terminal, and is supplied to the channel selection circuit as a system clock through the buffer 18. In this system clock generation circuit, a clock from an external device can be supplied to the first oscillation terminal.

A channel selection system can be configured by the system clock generation circuit configured as described above and the channel selection circuit of the present embodiment. As a specific example, by using a ceramic oscillator of 3.58 MHz for the system clock generating circuit, the system clock becomes 3.58 MHz.
A channel selection system having a frequency of z can be configured. In the same tuning system, for example, 6.4 MHz
By supplying a clock from another device to the system clock generating circuit, a clock having a frequency of 3.2 MHz can be supplied as a system clock to the tuning circuit through the 1/2 frequency divider 16. In the case of this example, since there is a difference of 0.38 MHz as the system clock as compared with the above example, in the conventional channel selection circuit, the sampling point for detecting the horizontal synchronization signal and the bar for channel selection display are provided. In such a case, the image in the form of a shift is shifted, so that a normal synchronization signal cannot be detected, or the channel selection display is shifted, so that a correct channel cannot be displayed. However, according to the channel selection circuit of the present embodiment, the sampling point for detecting the horizontal synchronization signal and the position of the bar-shaped image for channel selection display are corrected by the sample signal from the external terminal, so that the normal synchronization is achieved. A signal can be detected, and a bar-shaped image for channel selection display can also be displayed at a normal position.

[0029]

As described above, according to the tuning circuit according to the first aspect of the present invention, the timing of sampling the horizontal synchronizing signal can be changed by an external control signal. It is possible to arbitrarily select a sampling point for detection. Therefore,
Variations in the frequency of the system clock, synchronization separation circuit and A
It is possible to select an optimum sampling point with respect to a change in the characteristics of the FC circuit.

According to the channel selection circuit of the second aspect of the present invention, the output timing of the channel selection display signal can be changed by an external control signal. It is possible to arbitrarily select the position of the channel selection display image on the TV screen. Therefore,
Variations in the frequency of the system clock, synchronization separation circuit and A
It is possible to maintain an accurate display of the reception channel with respect to the variation in the characteristics of the FC circuit.

Further, according to the tuning circuit of the third aspect of the present invention, by controlling the same control signal, the change of the sampling timing of the horizontal synchronizing signal and the change of the output timing of the tuning display signal can be reduced. Can be linked, so that the sampling point and the TV
The position on the screen can be linked.

According to the channel selection circuit according to the fourth and fifth aspects of the present invention, even when the frequency of the system clock is changed,
An optimal sampling point can be selected by an external control signal, and an accurate reception channel can be displayed. Therefore, it is possible to correspond to various system clocks having different frequencies.

As described above, according to the present invention, it is possible to provide a channel selection circuit capable of selecting an optimum sampling point and accurately displaying a reception channel.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a tuning circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the tuning circuit according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a system clock generation circuit that generates a system clock used in the tuning circuit according to the embodiment.

FIG. 4 is a diagram showing a channel selection display on a TV screen.

[Explanation of symbols]

 1, 2 D flip-flop 3 inverter 4 AND circuit 5 counter 6, 11 comparator 7 selector 8 adder 9 up / down counter 10 divider 12 waveform shaping circuit

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Obayashi 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-64-25683 (JP, A) 64-44722 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/44 H03J 7/18 H04N 5/445

Claims (5)

(57) [Claims] 1. A counter which is reset at a leading edge of a horizontal blanking signal and counts a system clock, and a counter selection wherein a counter output value output from the counter is selectively determined by an external sampling point selection signal. A synchronization signal sampling means for sampling a horizontal synchronization signal when the value reaches a value, wherein the counter selection value is changed by the sampling point selection signal, whereby the synchronization signal sampling means samples the horizontal synchronization signal. A channel selection circuit characterized by being configured to be able to change timing. 2. An up / down counter for counting the system clock, and a digital value is selectively generated by an externally selected channel display position selection signal based on an up / down counter output value output from the up / down counter. Digital value generation means, and a selection for outputting a channel selection display signal superimposed on a video signal when a counter output value output from the counter reaches the digital value generated by the digital value generation means. Station display signal output means, wherein the digital value is changed by the tuning display position selection signal, thereby changing the timing at which the tuning display signal output means outputs the tuning display signal. The channel selection circuit according to claim 1, wherein the channel selection circuit is configured to be able to perform the operation. 3. Since the sampling point selection signal and the channel selection position selection signal are the same signal,
The digital value changes with the change of the counter selection value.
A change in the sampling timing of the horizontal synchronization signal in the synchronization signal sampling means caused by a change in the counter selection value, and a change in the digital value.
3. The channel selection according to claim 2, wherein the control unit is configured to be able to link a change in the output timing of the channel selection display signal in the channel selection display signal output unit that occurs with the change. circuit. 4. When the frequency of the system clock is changed, the counter selection value is changed by the sampling point selection signal, so that the synchronization signal sampling means samples a horizontal synchronization signal at a predetermined timing. The tuning circuit according to claim 1, wherein the tuning circuit is configured as follows. 5. When the frequency of the system clock is changed, the counter selection value is changed by the sampling point selection signal, so that the synchronization signal sampling means samples a horizontal synchronization signal at a predetermined timing. As described above, and the digital value is changed by the tuning display position selection signal, the tuning display signal output means is configured to output the tuning display signal at a predetermined timing. 4. The tuning circuit according to claim 2, wherein: