JP3519878B2 - Control circuit for vertical synchronous operation - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a vertical synchronization operation for controlling a vertical synchronization operation on a television screen, and more particularly to a control circuit for a vertical synchronization signal included in an input signal. And a non-standard mode for generating a vertical drive signal and a standard mode for generating a vertical drive signal based on the count result of its own counter. 2. Description of the Related Art In a television set, vertical and horizontal scanning on a screen is controlled in accordance with a received TV broadcast wave and a reproduction signal from a video deck. NT
According to the SC standard, one field is 262.5H (H is 1
(Meaning a horizontal line), and the NTSC standard television signal includes a vertical synchronization signal every 262.5H. Therefore, a vertical synchronization signal is detected from the input signal, and the vertical scanning on the display screen is controlled in synchronization with the vertical synchronization signal. Here, it is conceivable to always detect the vertical synchronizing signal from the input signal and control the scanning on the display screen based on this signal. However, such a system is very susceptible to noise and the like. . That is, when the vertical synchronization signal cannot be detected or when the vertical synchronization signal is erroneously detected, the effect immediately appears on the display screen,
Stable display is not possible. [0004] Therefore, when a vertical synchronizing signal included in an input signal is repeatedly detected, a system in which a vertical synchronizing signal is generated in its own circuit and scanning is controlled using this signal is generally used. Has been adopted. For example, a vertical synchronizing signal included in an input signal is detected, and one vertical synchronizing period is counted by a counter based on the detected vertical synchronizing signal. Then, it is determined whether or not a vertical synchronization signal is present at a position estimated from the count result. If the vertical synchronization signal is at a position at which the vertical synchronization signal is stably estimated, a vertical drive signal is generated based on the count value of the counter thereafter ( Hereinafter, it is referred to as a standard mode). On the other hand, when the synchronization signal is not detected at the estimated position, a vertical drive signal is generated according to the detected vertical synchronization signal (hereinafter referred to as a non-standard mode). In the standard mode in which the vertical drive signal is generated based on the result of the counter, it is determined whether or not the vertical sync signal is input at the timing of the vertical drive signal, and the vertical sync signal is not continuously input. In this case, the mode is returned to the non-standard mode in which a vertical drive signal is generated based on the input vertical synchronizing signal. According to such an apparatus, the standard mode and the non-standard mode are automatically switched according to the state of the input signal, and stable vertical synchronization is achieved when a standard television signal is input. It is possible,
Also, it can cope with a case where another signal is input. [0008] However, depending on the signal input to this system, when the vertical drive signal is generated in the standard mode, the input signal has been input up to that time. The signal may be switched to a television signal of the same type as the television signal, but with a slightly shifted phase. That is, the vertical synchronization period may be switched to a television signal which is the same but the phase is shifted by several Hs. For example, when the video deck is switched from the fast forward mode to the playback mode, there is a case where the video deck outputs a pseudo vertical synchronizing signal immediately before actually entering the playback mode. The pseudo vertical signal is almost the same as the vertical synchronization signal in the subsequent reproduction mode,
Often the phase is shifted by several H's. In such a case, the display position is slightly shifted in the vertical direction, but especially after fast-forwarding, and this is hardly recognized by the user. Therefore, even if such a situation occurs, there is no problem in normal display. [0011] However, in a closed caption system, this small shift becomes a problem. That is, in the closed caption system, character information is superimposed on 21H, and the system attempts to obtain character information from the 21H signal. And, as mentioned above,
If the vertical synchronizing signal is shifted by several H's, 21H recognized by the system is different from 21H in the input signal, and the system cannot obtain character information. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a control circuit for a vertical synchronization operation capable of suppressing a shift in a vertical drive signal in a standard mode. I do. According to the present invention, a count is started based on a vertical synchronizing signal included in an input signal, and a signal indicating a timing at which a vertical drive signal is to be generated is determined based on the count result. A non-standard mode that generates a vertical drive signal based on a vertical synchronization signal included in an input signal, and a standard mode that generates a vertical drive signal based on the count result of the counter And a first determining means for determining whether there is a vertical synchronization signal corresponding to a timing at which a vertical drive signal is to be generated in the non-standard mode, and In the standard mode, the timing corresponds to the timing of the vertical drive signal generation based on the count result of the counter. A second determining means for determining whether there is a vertical synchronization signal within the first range, and a shift from the non-standard mode to the standard mode based on a result of the first determining means;
A transition control unit for controlling transition from the standard mode to the non-standard mode based on a result of the determination by the second determination unit; and a second control unit corresponding to a vertical drive signal generation timing based on the count result of the counter in the standard mode. A third determining means for determining whether a vertical synchronization signal is present in a second range narrower than the first range ;
Synchronizes with this based on the horizontal sync signal included in the signal.
Horizontal drive signal generating means for generating a horizontal drive signal,
Generated based on the horizontal sync signal included in the input signal
When the horizontal drive signal is synchronized with the horizontal sync signal
Only when the vertical synchronization signal is not within the second range, the mode shifts from the standard mode to the non-standard mode according to the determination result of the third determination means . As described above, there are two determination means for shifting from the standard mode to the non-standard mode. Therefore, the horizontal determination is performed by the second determination means.
The input signal is too noisy
In the state, if the vertical
The mode shifts to the standard mode, and the vertical sync
If not, keep the standard mode
Screen disturbance can be minimized. Also, a third region having a relatively narrow range.
Detecting a vertical synchronizing error by the judging means
Can be. That is , in a state where horizontal synchronization is established, it is detected with high accuracy whether a vertical synchronization signal comes in at a predetermined timing. Therefore, the input signal is switched in the standard mode, and the vertical synchronizing signal is set to several Hs.
This can be detected even in the case of deviation. And
In this case, since the mode is temporarily switched to the non-standard mode, a correct vertical synchronization signal can be detected, and the mode can be shifted to the standard mode at the correct timing. Preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings. [Overall Configuration] FIG. 1 is a block diagram showing the overall configuration of the present embodiment. First, the input terminal 10
A television signal (referred to as a standard signal) including a vertical synchronizing signal having a period of 262.5H in accordance with the NTSC standard and various video signals (referred to as non-standard signals) at other timings are input. The input terminal 10 is connected to a sync separation circuit 12, where a vertical sync signal is separated from the video signal. Gate 1
4, the holding circuit 16 is connected. Gate 1
4 corresponds to a signal φ6 from a vertical countdown circuit 18 described later (a period “H” of 260.5 to 1.5H),
The signal is passed, and if a vertical synchronizing signal is present during that period, the holding circuit 16 holds it. Further, the value held by the holding circuit 16 is reset by φ3 which becomes “H” at 17H. Therefore, the holding circuit 16 holds “H” when the vertical synchronization signal corresponding to the count of the vertical countdown circuit 18 is separated by the synchronization separation circuit 12 (when input from the input terminal 10). Then, the output of the holding circuit 16 is input to the signal selection circuit 20.
Note that the signal φ1 (“H” from reset to 4H) from the vertical countdown circuit 18 is also supplied to the signal selection circuit 20. The sync separation circuit 12 has a gate 22
Is also input to the holding circuit 24 via the. Gate 22
Is opened by 224 to 296H or φ4 which becomes “H” at the time of reset, and the holding circuit 24 holds this value. The holding circuit 24 is supplied with a signal φ2 which becomes “H” at 261.5 to 262H, and is reset by this φ2. Therefore, the holding circuit 24 outputs “H” when the vertical synchronization signal is not separated by the synchronization separation circuit 12 according to the count value of the vertical countdown circuit 18.
Hold. An input selection circuit 26 is connected to the holding circuit 24. Φ2 from the vertical countdown circuit 18 is also input to the input selection circuit 26, and the input selection circuit 26 outputs either the output from the holding circuit 24 or φ2. This switching is performed in response to a switching signal, and outputs φ2 at the time of standard, and outputs a signal from the holding circuit 24 at the time of non-standard. The input selection circuit 26 is connected to a reset pulse generation circuit 28, which generates a reset pulse in accordance with the output of the input selection circuit 26 and supplies it to the reset input terminal R of the vertical countdown circuit 18. I do. Therefore, the vertical countdown circuit 18 outputs the vertical synchronization signal or φ2 obtained from the input signal held in the holding circuit 24.
Is reset by either of Note that the reset pulse generating circuit 28 is supplied with a 2fH signal having twice the frequency of the horizontal synchronization signal, and the width of the reset pulse is
(1/2) H. The signal φ2 from the vertical countdown circuit 18 is also supplied to a delay circuit 30. The 2fH signal is also supplied to the delay circuit 30, and the delay circuit 30 delays φ2 by 0.5H and outputs it. And
The output of the delay circuit 30 is supplied to the signal selection circuit 20. In response to the switching signal, the signal selection circuit 20 selects a set of the output of the holding circuit 16 and φ1 in the case of the standard, and a set of the reset pulse from the reset pulse generating circuit 28 and the signal of the delay circuit 30 in the case of the non-standard. Output. A phase comparison circuit 32 is connected to the signal selection circuit 20 and compares the phases of two outputs of the signal selection circuit 20. The comparison result is output to the switching signal setting circuit 3
4 is held. The switching signal setting circuit 34 includes two counters and one flip-flop.
That is, the non-standard signal is switched and held when three consecutive phase comparison result mismatches in the standard state are counted, and the standard signal is switched and held when seven phase comparison result matches in the non-standard state are counted continuously. . The switching signal is supplied to the signal selection circuit 2
0 is supplied to the input selection circuit 26. Note that the vertical countdown circuit 18
The fH signal is received at the clock input terminal C, and is reset by a reset pulse from the reset pulse generating circuit 28 to start counting, and sequentially counts 2fH. Then, the signal φ5 which becomes “H” for 8H from the reset pulse
Is output from the output terminal 36 as a vertical drive signal. [Operation] According to such a circuit, in the initial state, the switching signal setting circuit 34 is in a non-standard state, and the switching signal setting circuit 34 outputs a standard signal. Then, the vertical synchronization signal separated by the synchronization separation circuit 12 is supplied to the gate 22, the holding circuit 24,
The signal is supplied as a reset signal to the vertical countdown circuit 18 via the input selection circuit 26 and the reset pulse generation circuit 28. Then, the vertical countdown circuit 18
Count 2fH. Then, a vertical drive signal which becomes "H" for 8H from the reset of the vertical countdown circuit 18 is output from the output terminal 36. Thus, in the non-standard mode, according to the input vertical synchronization signal,
A vertical drive signal is output. In this non-standard mode, the signal selection circuit 20 sets the reset pulse from the reset pulse generation circuit 28 and φ2 from the delay circuit 30 to 0.5H.
The delayed signal is supplied to the phase comparison circuit 32. The reset pulse has a width of 0.5H, and when a standard signal is input, the vertical countdown circuit 18
Should repeat the count from 0 to 262H. Therefore, a signal which becomes “H” during a period of 0.5H from 262H delayed by 0.5H in the delay circuit 30 coincides with the reset pulse. Therefore, when a standard signal is being input, the phase comparison circuit 32 outputs a coincidence signal. When a coincidence signal is output seven times in succession, the switching signal setting circuit 34 outputs a signal indicating that the mode is the standard mode. That is, the switching signal is switched to the standard state. Thus, the phase comparison
When the path 32 is in the non-standard mode, the vertical drive signal
The vertical sync signal corresponding to the timing at which the
Function as a first determination unit for determining whether or not the data is correct. In the standard mode, the input selection circuit 26 supplies φ2 to the reset pulse generation circuit 28. Therefore, a reset pulse which becomes “H” for a 0.5 H period from the fall of φ2 is supplied to the vertical countdown circuit 18 and the count operation of 0 to 262 H is repeated, and a vertical drive signal that becomes “H” at 0 to 8 H is generated. Output terminal 3
6 is output. Therefore, in the standard mode, the count operation of the countdown circuit 18 causes
Even when the vertical drive signal is generated and the vertical synchronizing signal in the input signal cannot be separated accurately or includes noise, it is possible to eliminate these effects and maintain the synchronization. In the standard mode, the vertical synchronization signal separated by the synchronization separation circuit 12 is supplied to the holding circuit 16 via the gate 14. That is, in the count result in the vertical countdown circuit 18, 26
When the vertical synchronization signal is input between 0.5H and 1.5H, the holding circuit 16 holds "H". And
In this standard mode, the signal selection circuit 20 outputs the output of the holding circuit 16 and the vertical countdown circuit 1
8 is selected from the phase comparison circuit 32.
To supply. The phase comparison circuit 32 determines whether or not the signal from the holding circuit 16 is “H” when φ1 rises. The vertical synchronization signal is between 260.5H and 1.5H (first
) , The phase comparison circuit 3
2 detects a match. Then, the switching signal setting circuit 34
Keeps the standard mode as it is. On the other hand, the holding circuit 16
Since the signal is reset to H, when the vertical synchronization signal is not input during the above period, the holding circuit 16 holds "L". For this reason, in the standard mode,
When a vertical synchronization signal synchronized with the count of the vertical countdown circuit 18 is not input to the input signal due to channel switching or the like, the holding circuit 16
“L” is held. Therefore, in the phase comparison circuit 32, a mismatch is detected. Then, the switching signal setting circuit 3
No. 4 shifts to the non-standard mode when a mismatch is detected three consecutive times. That is, the switching signal is switched to the non-standard state. In this way,
Switching to the non-standard mode is performed. like this
In addition, when the phase comparison circuit 32 is in the standard mode,
Vertical drive signal generation based on the count result of the above counter
The vertical synchronization signal is within the first range corresponding to the timing of
It functions as a second determining means for determining whether there is any. Soshi
The switching signal setting circuit 34 determines the result of the first determination means.
From non-standard mode to standard mode
Mode and based on the determination result of the second determination means.
Transition from standard mode to non-standard mode
Function as transition control means for controlling the control of "Configuration of Synchronization Displacement Detection Circuit" Here, in this embodiment, the window comparator 4
0, a counter 42, and an AND gate 44. That is, the synchronization separation circuit 1
2 is supplied to the window comparator 40. The window comparator 40 calculates a value of 0.5 based on the count result of the vertical countdown circuit 18.
With the accuracy of H, it is detected whether an accurate vertical synchronizing signal is coming. The window comparator 40
If no vertical synchronizing signal is detected at the output of, the counter 42 counts this. The counter 42 is reset when the window comparator 40 detects a vertical synchronization signal. Therefore, it cant up by continuous non-detection. In this example,
H is output after three consecutive non-detections. The output of the counter 42 is an AND gate 4
4 is input. An H lock signal is also input to the AND gate 44. When the H lock signal is also “H”, “H” is output from the AND gate 44. The output of the AND gate 44 is supplied to a switching signal setting circuit 34.
Changes the switching signal to non-standard in response to the "H" signal from the AND gate 44. As a result, the input selection circuit 26 and the signal selection circuit 20 are switched to enter the non-standard mode. Thus, the out-of-sync detection
When the circuit 46 is in the standard mode, the counter
Of vertical drive signal generation based on count result
Perpendicular to a second range narrower than the first range corresponding to
Functions as third determination means for determining whether there is a synchronization signal
I do. As described above, according to the present embodiment, in a state where the synchronization such as the H lock is sufficiently established, it is detected with high accuracy whether the vertical synchronization signal comes in at a predetermined timing. . Therefore, the input signal is switched in the standard mode, and the vertical synchronizing signal is set to several Hs.
This can be detected even in the case of deviation. And
In this case, since the mode is temporarily switched to the non-standard mode, a correct vertical synchronization signal can be detected, and the mode can be shifted to the standard mode at the correct timing. Further, the vertical synchronizing signal in the input signal is also detected through a route via the gate 14 and the holding circuit 16. Therefore, the standard mode can be maintained even in a state where the noise of the input signal in which the H lock is not applied is large, and the disturbance of the screen can be minimized. [Detailed Configuration of Synchronization Displacement Detection Circuit] FIG. 2 shows a window comparator 40, a counter 42,
3 shows a configuration example of a synchronization shift detection circuit 46 including an AND gate 44. The window comparator 40 includes an inverter 50, an AND gate 52, flip-flops 54, 5
6, and an AND gate 58. Sync separation circuit 1
2 is supplied to the AND gate 52 via the inverter 50. The AND gate 52 is supplied with a φ2 signal that becomes “H” in 261.5H to 262H. Therefore, the AND gate 52 outputs “H” only when the vertical synchronization signal included in the input signal becomes “L” between 261.5H and 262H (within the second range) . The output of the AND gate 52 is input to the set terminal S of the flip-flop 54. The reset terminal R of the flip-flop 54 is supplied with a signal which becomes H in the vicinity of 18H to 36H. Note that the signal φ3 may be used. Therefore, when the AND gate 52 outputs “H”, the flip-flop 54 outputs almost 0H to 18H.
The “H” is maintained during the H period, and “L” is maintained during the other periods. When the AND gate 52 does not output “H”, “L” is maintained. The output terminal Q of the flip-flop 54 is connected to the set terminal S of the flip-flop 56. This flip-flop 5
The signal which becomes “H” near 224H to 225H is input to the reset terminal R of No. 6. Therefore, when the flip-flop 54 outputs “H”, the flip-flop 56 holds the signal until around 224H. Therefore, when the AND gate 52 outputs H, the output terminal Q of the flip-flop 56 outputs almost 0H to 224.
During the H period, “H” is held, and during the other periods, “L” is output. On the other hand, when the AND gate 52 does not output “H”, “L” is maintained. The inverted output terminal Q bar of the flip-flop 56 is input to an AND gate 58, to which a signal which becomes "H" at approximately 4H to 8H is supplied. Therefore, when the AND gate 52 does not output "H" from the AND gate 58, the AND gate 58 outputs "H" for a period of 4H to 8H, and
When 2 outputs “H”, it keeps outputting “L”. The counter 42 is composed of two flip-flops 60 and 62,
In both cases, the inverted output terminal Q is input to the input terminal D. Also, the inverting input terminal Q of the flip-flop 60
The output of the bar is the clock input terminal C of the flip-flop 62.
And both flip-flop output terminals Q are connected. The output of the AND gate 58 of the window comparator 40 is input to the clock input terminal C of the flip-flop 60, and the output terminal Q of the flip-flop 56 of the window comparator 40 is connected to the reset terminals R of both flip-flops 60 and 62. Have been. Therefore, the counter 42 outputs “H” when the AND gate 58 outputs “H” three times without outputting “H” to the output terminal Q of the flip-flop 56.
Is output. That is, for three consecutive vertical periods, 261.5
When the vertical synchronization signal is not input between H and 262H, the counter 42 outputs “H”. It should be noted that various signals which become "H" at a predetermined vertical position are all generated in the vertical countdown circuit 18. The H lock signal may be any signal as long as it detects that the internally generated horizontal drive signal is synchronized with the input horizontal synchronization signal. For example, the circuit requires a 2fH signal, and generates a signal synchronized with the input horizontal synchronizing signal.
L (phase locked loop). Therefore, whether the PLL is locked may be used as an H lock signal. Further, a flyback pulse is generated based on the horizontal drive signal, and thereby the flyback transformer is driven. Therefore, it is also preferable to generate the H lock signal based on a comparison between the flyback pulse and the timing of the input horizontal synchronization signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of an embodiment. FIG. 2 is a diagram illustrating a configuration of a window comparator and the like. [Description of Signs] 12 Sync separation circuit, 14, 22 gate, 16, 24
Holding circuit, 18 vertical countdown circuit, 20 signal selection circuit, 26 input selection circuit, 28 reset pulse generation circuit, 30 delay circuit, 32 phase comparison circuit, 3
4 Switching signal setting circuit, 40 window comparator, 42 counter, 44 AND gate, 46 Synchronization error detection circuit.

Claims (1)

(57) [Claim 1] Counting is started based on a vertical synchronizing signal included in an input signal, and based on the counting result,
A non-standard mode for generating a vertical drive signal based on a vertical synchronization signal included in the input signal, and a counter for generating a signal regarding a timing at which a vertical drive signal is to be generated; A standard mode for generating a vertical drive signal based on the
A vertical synchronization operation control circuit operating in the two modes, wherein in a non-standard mode, first determination means for determining whether there is a vertical synchronization signal corresponding to a timing at which a vertical drive signal should be generated, In the mode, a second determining means for determining whether or not a vertical synchronization signal exists within a first range corresponding to a timing of generating a vertical drive signal based on a count result of the counter, based on a result of the first determining means. A transition control means for controlling a transition from the non-standard mode to the standard mode and a transition from the standard mode to the non-standard mode based on the determination result of the second determination means; A second range narrower than the first range corresponding to the timing of vertical drive signal generation; A third determination means for determining whether there is a vertical synchronizing signal within the range of, are generated based on the horizontal synchronizing signal contained in the input signal
When the horizontal drive signal is synchronized with the horizontal sync signal
In addition, a control circuit for a vertical synchronization operation characterized in that the mode shifts from the standard mode to the non-standard mode even when the vertical synchronization signal is not within the second range according to the determination result of the third determination means .