JPS5981985A - Clock signal regeneration system - Google Patents

Abstract

PURPOSE:To regenerate a clock signal stably and securely by combining the output of a reference oscillator for signal regeneration roughly with a clock line signal transmitted intermittently in every vertical blanking period, and controlling a clock phase. CONSTITUTION:The clock line signal extracted and multiplied by a gate multiplying circuit 202 is detected by the peak detection of a peak detecting circuit 203. In this case, when the clock line signal is detected, the signal is supplied to a majority decision counter 205 through a gate circuit 204. Then, the counter 205 selects a spare clock pulse train consisting of the largest number of pulses in phase with the pulse train of the arrival clock line signal among 10 slightly out-of-phase spare clock pulses. Thus, the clock pulse train signal which is most in phase with the input clock line signal is took out as a regenerated clock signal 211.

Description

Detailed Description of the Invention Invention i: Television multiplex teletext broadcasting in which character information is multiplexed and transmitted in the form of a binary NRZ signal during the vertical retrace period of a television video signal, and reproduced and displayed on a home receiving terminal. Regarding the clock signal regeneration method used for decoding encoded information signals such as in This is what I did.

Conventionally, in order to obtain a recovered clock signal for decoding an encoded information signal, a clock run-in (ORI) consisting of a clock pulse train of 8 to 16 cycles is sent intermittently along with the encoded information signal. A flywheel oscillator that extracts the signal from the encoded information signal and installs it in the receiving terminal based on the extraction of the clock run-in signal, or an oscillator that has an automatic phase control (APO) circuit added to fully stabilize the oscillation frequency. The device was fully driven and regenerated a clock signal with a predetermined repetition frequency. However, in such conventional clock signal regeneration methods, if impulse noise or random noise is mixed in the input clock run-in signal for clock signal synchronous regeneration, phase disturbance will occur in the regenerated clock signal, so the code This method has the drawback that accurate decoding and signal identification of encoded information signals are impossible.

In addition, if such noise is mixed into the received signal of television multiplex teletext broadcasting, not only will it be impossible to accurately reproduce the lock signal as described above, but also the horizontal・The vertical synchronization signal becomes unstable, and the gate signal formed based on the horizontal and vertical synchronization signals makes it difficult to accurately extract the coded character information signal that is multiplexed and transmitted during the vertical retrace period. There was also the problem that it could not be done.

The purpose of the present invention is to completely eliminate the above-mentioned conventional drawbacks, and to perform automatic phase control and injection into a clock recovery oscillator based only on the clock run-in signal, which is transmitted only intermittently and is susceptible to noise contamination. It eliminates unstable intermittent control such as synchronization, and serves as the basis for setting the clock frequency.
A clock run-in signal is transmitted every horizontal retrace period,
The reference oscillator for clock signal regeneration is fully driven based on the color burst signal, which is transmitted virtually all the time, and the oscillator output is not connected to the clock run-in signal that is intermittently transmitted during each vertical retrace period. It is an object of the present invention to provide a clock signal reproducing method which controls the clock phase by coupling the clock signal to the clock signal, thereby making it possible to reliably reproduce the clock signal in a completely stable manner.

That is, the clock signal regeneration method of the present invention includes a clock synchronization detection means for detecting an intermittently incoming clock synchronization signal having the same predetermined frequency as the required clock (if), and a multiplication clock generating means for generating all multiplied clock signals having a frequency of and coincidence detecting means for comparing the phases of the integer number of preliminary clock signals with the clock synchronization signal to detect coincidence of the respective phases; The present invention is characterized in that a coincidence counting means is provided for counting each signal, and the preliminary clock signal for which the phase coincidence is detected the most is taken out as the required clock signal.

The present invention will be described in detail below with reference to the drawings.

1. Color subtitle 'Iji' in television multiplex teletext
- fC = integer multiple of 5-73 MHz, e.g.], o
An example of the configuration of a reference oscillator that generates a reference frequency signal of 10=57.8 MHz is shown in FIG. In the illustrated configuration, ], OO are input color video signals multiplexed with encoded character information signals, etc. during the vertical retrace period, and ]01 is a color subcarrier frequency of 3.58 in the input color video signal.
It is a band pass filter for extracting a signal component having Mn2 ffi, that is, a color subcarrier component including a color burster, and 102 separates a horizontal synchronization signal 114, which is used as a color burst extraction timing and a reference, from an input color video signal. Dust in the synchronization separation/separation circuit, 108,
Horizontal synchronization signal 114'! A burst flag generating circuit 104 generates a burst flag signal for gating a color burst i as an i-reference, and 104 is a color burst signal 112 in the color subcarrier frequency component extracted from the bandpass filter 101 by the burst flag signal. It is a color burst gate circuit that gates and extracts
105 is a peak detection circuit that detects the presence of a color burst as a gate output of the gate circuit 104 by full peak detection; 106 is a phase detection circuit that detects the color burst signal 112 from the gate circuit 1041;
8,58 MH2Q generated as described below
Phase detection is performed using the color subcarrier frequency signal 1]3. Further, 108 is a hold circuit that holds the phase detection output signal level of the phase detection circuit C16, 109 is a low-pass filter that extracts only the phase change component in the signal level held by the hold circuit 108, and 110 is the above-mentioned It is a voltage controlled oscillator (VCO) that oscillates at a reference frequency of 57.8 MHz, and 107.
7.8'MHz color subcarrier frequency 3.58 MH2K
8 to form the color subcarrier frequency signal described above.

6 In the reference oscillator configured as described above, the color burst signal 112 extracted from the input color video signal 100
and a color subcarrier frequency signal 113 formed by frequency stepping down from the oscillation output of a voltage controlled oscillator (VaO) 1]0 by a phase detection circuit 1o6 to detect the phase difference between them, and then generate a color burst. The bold circuit 108 holds the DC component corresponding to the phase difference only during the period when the signal 11.2 is detected, and the low-pass filter 109 has a sufficiently low cutoff frequency of several hundred Hz.
The cell controls the oscillation frequency of the voltage controlled oscillator (VOO) 110 by extracting only the DC component corresponding to the slowly changing phase difference, and maintains the reference oscillation frequency. In addition, the phase detection circuit 1
06'', [When configured by flip-frog, color burst signal 112 and color subcarrier frequency signal 1
If the phase difference between the voltage controlled oscillator (VOO) 110 and the voltage controlled oscillator (VOO) 110 is 180° and the phases are opposite to each other, the oscillation frequency of the voltage controlled oscillator (VOO) 110 is configured to be 57.8 MHz.

The 57.8 MHz reference frequency signal 111 generated as described above is generated by a voltage controlled oscillator (VAO).
As mentioned above, compared to the conventional clock run-in signal, the color burst signal 112 that is used as a reference for the oscillation frequency control of the '110 is substantially constantly input, and therefore the internally generated color subcarrier Since the phase difference with the frequency signal 11.3 changes extremely slowly, a low-pass filter 1.0 inserted in the voltage controlled oscillator (VCO) control system is used.
Since the cutoff frequency of 9 can be set sufficiently low, the reproduction of the clock signal becomes sufficiently stable.

Next, based on the reference frequency signal 111 of 57.8 MHz generated as described above and the input color video signal 100, a required reproduction clock signal with a repetition frequency of 5.73 Ml (z) is generated. FIG. 2 shows an example of the overall configuration of a clock signal regeneration circuit according to the invention method.

In the illustrated overall configuration, 200 has a frequency of 5.78M
In order to extract the clock run-in (GRI) signal in the form of ``1010 ...'' in which logic levels N111 and 0'' appear alternately at Hz, the passband center frequency is set to 2. .86 MHz, and 201 is similar to the burst flag generation circuit 108 in the configuration shown in FIG. A gate signal generation circuit 202 generates a gate signal for gating all the clock run-in (ORI) signals, and 202 is a gate signal generating circuit that generates 2,
86 Clock run-in (CRI) in MH7 frequency component
) is a gate multiplier circuit which extracts the entire signal and multiplies its frequency 'i2 to extract a 5.78 MHz frequency component. 203 is a peak detection circuit in the configuration shown in FIG. This is a peak detection circuit that detects the presence of a clock run-in (ORI) signal as an output by peak detection and outputs a clock run-in (ORI) flag signal 210, and 204 is the clock run-in (GRI) flag signal 2]. In response to the application of 0, the clock run-in (ORI) from the gate multiplier circuit 202
) is a gate circuit that allows all signals to pass through, and 205 is a majority counter, which, as will be described later with reference to FIG. 206 selects the clock signal that
stomach. The counter must count down the 57% lMHz reference frequency signal 111'r generated by the configuration shown in Figure 1 and convert it into a 4-bit binary code decimal number (B(3
D) All signals (0) to (9) are generated, and 20
Reference numeral 7 denotes a front and rear impotence counter, which checks all the states before and after the reproduced clock signal selected by the majority counter 205 as will be described later in FIG. 5, so that a reproduced clock signal with an appropriate phase can be obtained. .

In the television multiplex teletext broadcast, a clock run-in (ORI) signal added to the encoded character information signal for reproduction clock synchronization is transmitted with a signal configuration as shown in FIG. That is, in the illustrated signal configuration, between the horizontal synchronizing signals 300 during the vertical retrace period of the television video signal, the color burst signal 5o1vc is followed by a 16-bit signal in the form of "10]0/song 1o". A clock run-in (CRI) signal 802i consisting of a pulse train is transmitted, and subsequently a data packet 308 containing a coded character information signal is transmitted.

In the overall configuration shown in FIG. 2, the clock run-in (ORI) extracted and multiplied by the gate multiplier circuit 202
) signal is detected by peak detection by the peak detection circuit 20B, and when a clock run-in (ORI) signal is detected, the clock run-in (ORI) signal is detected by the peak detection circuit 20B.
) No. 1i passes through the gate circuit 204 and is supplied to the majority counter 205, but at that time, the clock run-in (ORI) signal, which originally had a 16-bit configuration, is
N due to delay in gate timing in o path 208, etc.
It has been reduced to about an o-bit configuration. Majority vote Kara Nta 2
In 05, 57 was generated by the configuration shown in the first figure.
．． 8 II (Z reference frequency signal] 1) 10 sets of frequencies whose phases are slightly shifted sequentially, extracted every 9 pulses from the pulse train of 5.73 MIH2, are input. The clock run-in that came (
(ERI) A preliminary clock pulse train having the largest number of pulses whose phase matches that of the pulse train of the signal is selected. In this way, the majority counter 205 supplies the reset pulse protection counter 207 to the reset pulse protection counter 207 at a timing corresponding to the preliminary clock pulse train signal of the specific phase selected by the majority counter 205 to confirm the reproduced clock signal. The phase of the binary code decimal signal corresponds to that particular phase, and eventually the input clock run-in (QR
I) Frequency 5.78MH that best matches the phase of the signal
The second clock pulse train signal is extracted as the reproduced clock signal 211. Note that this reproduced clock signal 211° is generated by input clock run-in (
It is output only when it is confirmed that the phase matches perfectly with the '0RI) signal.

Next, FIG. 4 shows an example of a detailed configuration of the majority counter 205 mentioned above. In the configuration shown, 4,00i
l, ] is a 0-base counter with a 4-bit configuration.
Outputs base code decimal (BOD) signal 428,
1 is a 4-bit decoder that decodes a binary code decimal (BOD) signal 428 at different frequencies of 5.78 M
All Hz preliminary clock pulse train signals 402 to 411 are output, and 412 to 421 are reset by the horizontal synchronization signal 1.14+vc, and their respective gates are opened only during the application period of the preliminary clock pulse train signals 402 to 411 mentioned above, and the clock run is started. p, 423 is a 4-bit counter that counts the number of passing pulses in the in (CRI) signal 422, and selects the maximum count value from among the count outputs of each of the 4-bit counters 412 to 421, and calculates the maximum count value. This is a selection circuit that outputs all the optimal phase signals 424 at the timing corresponding to the value, and 425 is a selection circuit that outputs all the optimal phase signals 424 at the timing corresponding to the value.
passing the optimum phase signal 424 under the control of a search mode signal 426 provided as described below in the figure;
This is the gate circuit that supplies the above-mentioned.

In the majority counter having the above-mentioned configuration, the configuration shown in the first diagram is different from the frequency 8 in the input color video signal]00.
．． Television multiplex teletext clock frequency 5.78 frequency locked to 58MHz color burst
Frequency 57.8 MHz K, equivalent to 10 times MHz
The reference frequency signal 111 generated by the decimal counter 4
Counting down by 00, the binary code consists of 4+ bits.

The BCD signal 428 is converted into a signal 4+28 and supplied to all decoders 401, and the clock frequency is 5.78MHz.
IIC 10 types of pulse trains/signals 402 with equal repetition frequency and clock period out-of-phase pulse widths
~4] Form 1. Those Norms train signals 402~
4]]'i4 bit counters 412 to 42], and in each counter 4112 to 421, it is cleared by the commonly applied horizontal synchronizing signal 114, and each pulse train Φ]2 to 421/
Clock run-in signal 422 that came in during the pulse width period
The number of clock run-in pulses that are superimposed and incoming in almost the same phase as the pulses in each pulse train 412 to 42 is counted, and the counted values are sent to the total selection circuit 428. supply The selection circuit 423
, the trailing edge of the clock run-in flag signal 4210 formed by the peak detection circuit 203 is driven,
The count values from each counter 412 to 4121 are compared with each other, and the clock run-in signal 42 is supplied from the 4-bit decoder 401 via the counter that outputs the maximum count value.
The clock cycle pulse signal whose phase most closely matches each of the pulses in 2 is outputted as the appropriate phase recovery clock signal 424, and the forward and rear protection force/counter 207 described above is output as the clock signal 424.
It is also supplied to the gate circuit 425.

In the gate circuit 425, as will be described later with reference to FIG. 5, the front and rear protection counter 207 generates a signal to prevent genlock loss, that is, vertical synchronization loss, of a television video signal for multiplex transmission of, for example, a character information code signal. The search mode signal 426 representing the search mode signal 426 is used to control the genlock, and the normal lock run-in signal 422 cannot be obtained. Reset pulse 4 to reset counter 206i
27 is extracted as its gate output signal. Note that the number of pulses whose pulse phases match each other in the clock cycle pulse train signals 412 to 42] and the clock run-in signal 422 is extremely small for each clock pulse train.
Even when the maximum output count value of the counters 412 to 421 described above is approximately 1 or 2, it is assumed that the genlock is substantially lost and the reset pulse 427 is output.

Therefore, among the 10 types of BOD signals from the reset pulse 427, the B (ED=
The phase of the BCD signal with a clock frequency corresponding to 0 is the average phase of each pulse in the clock run-in signal 422 obtained during genlock.

Next, an example of the detailed configuration of the front and rear protection counter 207 in the overall configuration shown in FIG. 2 is shown in FIG. 502 and 503 are BOD=9, respectively, when the values of the binary code decimal (B (ED) signal 500 are 9, 1 and 0, respectively)
7130 is a BOD detection circuit that detects D=1 and B(ED=0'!l[-, and 504 is a BOD detection circuit that detects their BOD detection output signal and clock run-in (ORI) signal 42
A lock sensor 505 and 506 are lock sensors that output a search mode signal 426 by discriminating between a genlock state and an out-of-genlock state based on the lock discrimination result. 507 is a search mode signal output as a result of the lock discrimination, and is a search mode signal 4 supplied to the majority counter 205 shown in FIG.
It becomes 26. Also, 508, 509, 520, 521 and 523 are AND gate circuits.
24 is a negative circuit, 511 and 525 are counter clock input signals, 512, 518, 526 and 527 are counter reset signals, 514 is a forward protection counter, and 515 and 529 are respective comparison signals. This is a comparator that has a built-in reference value and compares it with the input value. 516 is a genlock pulse that indicates the genlock state, %p, 51.7 is a flip-flop f)5.
518 is a lock percentage signal, 519 is a regenerated clock signal with a clock frequency of 5.78 MHz, and 52
8 is a rear protection counter, and 530 is a genlock release signal indicating the state of genlock release.

Front and rear protection counter 207 with the above-described configuration
Binary code decimal (BGD) signal from 6 to 500'
1B (supplied to ED detection circuits 501 and 502, EC
Clock phase corresponding to D=9 and BOD=1, respectively, i.e. clock run-in (ORI) signal 4 during genlock set by reset pulse 427
22 gate pulses are respectively taken out to set the average phase. Similarly, the binary code JO base number (BOD) signal 5
The BOD detection circuit 508 that supplied 00 detects the BOD signal 0 having the same phase as the average phase of the clock run-in (ORI) signal 422 at the time of genlock, which is represented by the reset pulse 427 that resets the 1o base counter 206. Then, the 7 shift lock signal 519i to be taken out at the time of genlock is outputted and supplied to the AND gate circuit 528.

On the other hand, in the lock h7 sensor 504 to which the above-mentioned gate pulses of the BCD detection circuits 501 and 502 are supplied, there is a peak within the gate width of the above-mentioned clock run cycle during genlock determined by these gate pulses. It discriminates whether the clock run-in flag signal 210 from the wave detector 20.3 is input or not, and outputs a pulse of either the lock-in signal 505 or the lock-out signal 506 according to the result of the discrimination, and the AND gate circuits 508 and 509 as well as 520 and 52], respectively. A, ND gate circuits 50B and 50
9 is a search mode signal 507 indicating that the genlock is off.
are also supplied from the lock sensor 504, and therefore, these AND gate circuits 508 and 509 supply the lock sensor 5 only in the search mode when the genlock is removed.
A lock-in signal 505 and a lock-out signal 506' from 04 are passed through and provided to the forward protection counter 5]4 as a counter tallock input signal 5]1 and a counter reset signal 513, respectively. Since the forward protection counter 514 does not need to operate in the genlock mode, the inversion amount calicent signal 51.2 from the inverting circuit 510 that supplied the search mode signal 507 is also supplied, and this The front membrane retention counter 514 is reset. Note that this forward protection counter 514 is for fully confirming that the genlock state is established before outputting all of the reproduced clock signals, so it is sufficient to have a counter of at most 2 bits. That is, for example, the lock-in signal 51 .
1, it can be determined that the phase of the reproduced clock signal approximately matches the average phase of the sunset clock in (CRI) signal 422 at the time of genlock. The comparator 515 that supplies the counter output with such a 2-bit configuration compares the counter output value with a built-in reference value, and when the count output 16 of the front membrane counter 514 matches the reference value, a set pulse is generated. 5] 6 to set the flip-flop 5] 7, output the lock mode signal, and output the AND gate circuit 52.
After confirming that it is in the genlock state, the f11 raw tarlock signal 519 is passed.

After confirming the genlock state as described above, the backward protection counter 52ε is operated so that the clock phase of the regenerated tarlock signal 519 is continuous with respect to the average phase of the input clock run-in (ORI) signal 422. The reproduction clock signal 5]9 continues to be output in the above-mentioned state as long as the phase difference does not occur multiple times. Therefore, this rear protection counter 528 receives a lockout signal 506 and a lockin signal 50 from the lock sensor 504.
A counter tarlock input signal consisting of a lockout signal 525 at the time of genlock and a lockout signal at the time of genlock are received from the AND gate circuits 520 and 521 which respectively supplied the lock mode signal 518 from the flip-flop 517 and the lock mode signal 518 at the time of genlock. A counter reset signal consisting of an in signal 527 and a counter reset signal 526 corresponding to a search mode signal when the genlock is released are supplied, respectively, to monitor the genlock state after the start of output of the reproduced clock signal. In general, the number of lockout pulses counted in the rear protection counter is set to be larger than the number of lock impulses counted in the front protection counter, so that it is difficult to treat the genlock as being out of genlock due to noise interference, etc. For example, set the number to 8”,
The genlock is not determined to be off unless the lockout signal is received 8 times in a row. The count output of the backward protection counter 528, which has an 8-bit configuration, for example, is supplied to the comparator 529 for comparison with a built-in reference value, and the count output value is, for example, the above-mentioned; I'm ``8''.
Genlock release signal 530 when it matches the reference value.
The pulse is outputted and supplied to the flip-flop 517. Therefore, the flip-flop 517 enters the search mode in response to the arrival of the genlocked No. 4i 530, and corresponds to the reference value determined for the count output value of the forward protection counter 5]4, for example, the aforementioned '2''. Then, in the case where the lock-in signal 505 is output from the lock sensor 504 twice in succession, the genlock mode is not entered again, and the output of the reproduced clock signals 5 and 9 is stopped during that time.

As described above, the reproduced 70 clock signal 519 is taken out as the reproduced output clock signal 2]1 through the AND gate circuit 523 only at the time of generation, but this reproduced output clock signal 211 is input as in the conventional case. It is not formed by performing automatic phase control (APO) based on the clock run-in signal, but is a color burst signal obtained every horizontal scanning period, so it is much more powerful than the conventional clock run-in signal every vertical scanning period. Out of, for example, 10 different clock phases obtained by dividing the multiplied clock oscillation output whose phase is frequently and almost continuously controlled, the clock phase closest to the average phase of the input clock run-in (ORI) signal is selected and reproduced. Because it forms the clock signal,
Even if a dropout of the input clock run-in (ORI) signal occurs, as long as it does not last for a particularly long time, a stable and reliable reproduced clock signal can be obtained irrespective of the dropout.

In the above example, the reference oscillation frequency used as the reference for clock signal reproduction is selected to be 57.8 MHz, which is 10 times the clock frequency of 5.73 MHz, and 10 types of clock phases differing in lock period are used. The reproduced clock signal with the optimum phase is selected from among them, and the phase matching range is set to BOD = 9. However, this phase matching range can be set arbitrarily as necessary, and it is easy to use and economical. In order to completely reduce the number of stages of the 4-bit counter in the majority counter, taking into account all aspects of the clock phase, in the above example as well, there are no more than 10 types of clock phases, e.g., a regenerated clock signal with an optimal phase among the 5 types of clock phases. Even if the mode is selected, the accuracy of maintaining the genlock mode will only be halved, and no particular problem will occur. Note that, of course, the clock phase can be further subdivided to improve the time required to maintain the genlock mode by 1111 k, if necessary.

In the above explanation, the aspects of clock signal regeneration and forward and backward capture according to the method of the present invention have been described in detail. In terms of stability, the same forward and backward protection as in clock signal reproduction, for example, separation of vertical and horizontal synchronizing signals, as well as clock signal reproduction, will further increase stability.

FIG. 6 shows an example of a configuration in which front and rear protection is provided for separate reproduction of vertical and horizontal synchronizing signals as described above. In the illustrated configuration, 600 is a forward and backward protection circuit for horizontal synchronizing signals, 601 is a reproduced horizontal synchronizing signal, 602 is a genlock mode signal indicating that the reproduced horizontal synchronizing signal 600 is in genlock mode, and 603 is a genlock mode signal indicating that the reproduced horizontal synchronizing signal 600 is in genlock mode. 604 is a horizontal synchronizing signal for signal extraction, 605 is a separated output vertical synchronizing signal from the synchronization separation circuit, and 60 is a selector;
6f″s, a forward and backward protection circuit for vertical synchronization signals;
07 is a reproduction vertical synchronization signal.

In the above configuration, the reproduced clock signal 211 having an accurate or locked phase obtained in the previous stage and the separated output horizontal synchronization signal 114 obtained in the synchronization separation circuit are supplied to the horizontal synchronization signal front and rear protection circuit 000. However, in the same manner as described above for clock signal reproduction, it is possible to obtain a reproduced interhorizontal/auxiliary signal 601 having a stable phase. From the horizontal synchronization signal forward and backward protection circuit 600, the above-mentioned reproduced horizontal synchronization key signal 601 and input horizontal synchronization signal 1]
4 to all selectors 603, and also to the horizontal synchronization genlock mode signal 602 to the selector 60.
3, and at the time of genlock, the playback horizontal synchronization signal 601
Also, when the genlock is removed, the input horizontal synchronization signal 11
4 are extracted as horizontal synchronizing signals 604 for signal extraction.

Note that when using the separate output horizontal synchronization signal for signal extraction timing in the overall configuration shown in FIG. 2 (No. 8 114) as the horizontal synchronization signal 604 for signal extraction in the configuration shown in FIG. In addition, the vertical synchronization signal forward and rear protection circuit 606 in the configuration shown in FIG. The forward and backward protection circuits 606 and 600 for the vertical synchronization signal and the horizontal synchronization signal must output the vertical JIJI signal 607, respectively. It can be realized in the same manner with the same configuration as the rear protection counter.

As is clear from the above description, according to the present invention, the tarokk signal required for demodulating the encoded information signal multiplexed and transmitted during the vertical blanking period of the television video signal in, for example, television multiplex teletext broadcasting, etc. The regeneration can be performed much more stably than in the past, and the regeneration of this extremely stable lock signal is essentially constantly transmitted as a control input to maintain the original tarock reproducing oscillator in the genlock state. The input clock run-in signal is used to detect the average phase of the input clock run-in signal, and the reproduced clock signal formed by dividing all phases of the original oscillation output is reliably connected to the input clock run-in (ig signal) by loosely coupling it to the input clock run-in signal. Therefore, it is significantly different from the conventional method of clock signal regeneration, which is performed by closely coupling directly to the input clock run-in signal. Even if the clock run-in signal that comes intermittently is disturbed by impulse noise or internal equipment noise due to a drop in the received electric field, it is possible to regenerate the lock signal in a stable and reliable manner.Furthermore, If this mode of clock signal reproduction is applied to the reproduction of horizontal and vertical image synchronization signals of a television video signal that transmits encoded information signals in a fully multiplexed manner, it is possible to separate and extract the television multiplexed encoded information signal and reproduce the clock signal for demodulation. The stability and reliability can be further increased.

That is, in clock signal regeneration according to the present invention,
The color burst signal and clock run-in signal are separated and extracted based on the timing of the horizontal synchronization signal, and then used to reproduce the clock signal. Therefore, during genlock, the reproduced horizontal synchronization signal with forward and backward protection is all referenced. This ensures that each signal can be separated and extracted.

As described above, the clock signal reciprocation method of the present invention [in particular, the clock signal for television multiplex teletext has a constant frequency relationship f with the color subcarrier. = −/so'
It takes advantage of the fact that i= has a clock frequency f that has a different relationship to the color subcarrier frequency fsc than described above. Of course, even in the case where the clock signal is reproduced in the same manner as described above, the clock signal can be reproduced stably and reliably in the same manner as described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a reference multiplied frequency oscillator used for clock signal regeneration according to the method of the present invention, FIG. 2 is a block diagram showing an example of the overall configuration of the clock signal regeneration circuit, and FIG. 8 4 is a signal waveform diagram showing an example of the configuration of a television multiplex teletext signal to be used for reproducing the clock signal, FIG. 4 is a block diagram showing an example of the configuration of a majority counter used for reproducing the clock signal, and FIG. 6 is a block diagram showing an example of the configuration of the front and rear protection counter used for reproducing the clock signal, and FIG. 6 is a block diagram showing an example of the overall configuration of the front and rear protection circuit used for reproducing the horizontal and vertical synchronization signals. It is a line diagram. 100...Input color television video signal, 101
... band pass filter, 102 ... synchronization separation circuit, ]08 ... burst flag generation circuit, 104'...
Gate circuit, ]05...Peak detection circuit, ]06...
・Phase detection circuit, 107...1 Otsu. Counter, ]08
...Hall)"Do path, 109...Low pass filter, ]]0... Voltage controlled oscillator (VaO), 11
1... Reference frequency signal, 112... Color burst signal, 113... Color subcarrier frequency signal, 1]4...
・Horizontal synchronization signal, 200...Band pass filter, 201...Gate signal generation circuit, 202...Gate multiplier circuit, 203...
...Peak detection circuit, 204...Gate circuit, 205
1". ] ... Majority counter, 206 ... - counter, 0 207 ... Front and rear protection counter, 300 ... Horizontal synchronization signal, 301 ... Color burst signal, s 02 ... Clock run In (ORI)
Signal, 308... Data packet, 400... Decimal counter, 401... 4-bit counter (coder, 402-41)... Reserve clock pulse train signal, 412-4+21... 4-bit counter,
422...Clock run-in (ORI) signal, 428
... selection circuit, 424 ... optimal phase clock signal,
425 ”...Gate circuit, 426...Search mode signal, 427...Reset pulse, 500...Binary code decimal number (BCD) signal, 501
~503...BOD detection circuit, 504...Lock sensor, 505...Lock-in signal, 506...B1 draw-out signal, 507...Search mode signal, 50
8.509,520,521,528...AND gate circuit, 5LO,524...NOT circuit, 511゜52
4...Counter clock input signal, 5]2゜513
, 526, 527... Counter reset signal I. No., 514... Forward protection counter, 515,529.
...Comparator, 51 a...Genlock pulse, 517
...Flip-flop, 518-mount rotary mode signal,
519...Regenerated clock signal, 528...Backward protection counter, 530...Genlock out signal, 600...
・Forward and backward protection circuit for horizontal synchronization signal, 1601・
... Reproduction horizontal synchronization signal, 602 ... Horizontal synchronization genlock mode signal, 603 ... Selector, (i04+...
Horizontal synchronizing signal for signal extraction, 605...Separated output vertical synchronizing signal, 606...Front and rear retaining 5-pupil circuit for vertical synchronizing signal, 607...Reproducing vertical synchronizing signal. Patent applicant: Japan Broadcasting Corporation

Claims (1)

[Claims] L. Clock synchronization detection means for detecting an intermittently received clock synchronization signal having the same predetermined frequency as a desired clock signal, and a multiplication clock for generating a multiplication clock signal having a frequency that is an integral multiple of the predetermined frequency. generating means; clock dividing means for dividing the multiplied clock signal to form the integer number of preliminary clock signals, each of which has the predetermined frequency and each having a different phase; Coincidence detecting means for comparing the phases with the clock synchronization signal to detect all coincidences of the respective phases, and coincidence counting means for counting the number of times of detection of the phase coincidence for each of the integer number of preliminary clock signals, A clock signal regeneration method characterized in that the preliminary clock signal with the largest number of detected phase coincidences is extracted as the required clock signal.