JPH0526857Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a field discrimination circuit that discriminates between an even number field and an odd number field.

(b) Prior Art Electronic still cameras are described, for example, on pages 80 to 85 of the July 2, 1984 issue of the magazine "Nikkei Electronics" published by Nikkei McGraw-Hill.

In this electronic still camera, storing the video signal in the field or frame memory is
JP-A-59-79691 (first classification H04N5/783)
and Japanese Patent Application No. 61-195927 (G11B5/027).

By the way, when writing a frame-recorded signal from the magnetic disk of this electronic still camera into two field memories, one field at a time, one of these two field memories is used for odd-numbered fields, and the other is used for even-numbered fields. It is possible that

In this case, whether the input signal is an odd field signal or
A field discrimination circuit is required to discriminate whether the signal is an even field signal.

This field discrimination is generally performed by detecting a difference in phase difference between a horizontal synchronizing signal and a vertical synchronizing signal between an even field and an odd field. Such a field discrimination circuit is disclosed in Japanese Patent Publication No. 57-56269 (first classification H04N7/
08) or Special Publication No. 16833 (first classification)
H04N5/08).

In addition, vertical synchronization signal and duty cycle 50
A discriminating circuit which obtains a discriminating output by applying horizontal pulses of 100% to the clock and data terminals of a D flip-flop, respectively, is described in Japanese Utility Model Application Laid-open No. 14524/1983.

An example of a discrimination circuit using such a D flip-flop is shown in FIGS. 1 and 2.

In FIG. 1, 10 is an input terminal to which the synchronous separation signal a is applied. 11 is an inverter.

Reference numeral 12 denotes a horizontal synchronization separation circuit which extracts the horizontal synchronization signal and extracts equivalent pulses of the horizontal synchronization signal period and outputs first pulse signals c and d of the horizontal synchronization period. That is, when an even field signal is input, the first pulse signal shown in FIG. 2d is outputted, and when an odd numbered field signal is inputted, the first pulse signal shown in FIG. 2c is outputted. This horizontal synchronization separation circuit 12 is composed of a retrigger double single shot multi-pipulator 14 (product number: CMOS No. 4538). When a rising signal is input to the A terminal while the B terminal is in a high level state, this monostable multi 14 outputs a high level signal from the Q terminal for a time determined by the resistor R1 and the capacitor C1.
Further, when a falling signal is input to the B terminal while the A terminal is in a low level state, a high level signal is output from the Q terminal. The pulse width of this pulse signal (first pulse signal) from the Q terminal is set to be longer than 1/2H (H is the horizontal scanning period). Therefore, once a rising signal is input to the A terminal, from this point on, the B terminal becomes a low level state and ignores the rising signal to the A terminal. That is, equivalent pulses that are not in the horizontal synchronization period are deleted and first pulse signals c and d in the horizontal synchronization period are output.

A pulse width conversion circuit 16 converts the first pulse signals c and d into second pulse signals e and f having a pulse width of approximately 1/2H. This pulse width conversion circuit 16 is composed of a monostable multi-channel circuit including a capacitor C2 and a resistor R2 for making the pulse width approximately 1/2H.

18 is a vertical synchronization signal detection circuit that detects a vertical synchronization signal and outputs a vertical synchronization detection signal b. 2
0 is an integrating circuit consisting of a resistor R3 and a capacitor C3. 22 is a waveform shaping circuit consisting of a hysteresis comparator.

24 is a D flip-flop, to which the second pulse signals e and f are input to the D terminal, and the vertical synchronization detection signal b is input to the T terminal. This D flip-flop 24 outputs field discrimination signals g and h from its Q terminal.

The above operation will be explained. Horizontal synchronization separation circuit 12
is the first period of the horizontal synchronization signal from the synchronization separation signal a.
Outputs pulse signals c and d. The pulse width conversion circuit 16 creates second pulse signals e, f having a pulse width of approximately 1/2H from the first pulse signals c, d. The second pulse signals e and f have different phases with respect to the vertical synchronizing signal in an even number field and in an odd number field. Vertical synchronization signal detection circuit 18
detects the vertical synchronization signal and outputs the vertical synchronization detection signal b
Output. Note that this vertical synchronization detection signal is detected approximately 1/3H later than the actual vertical synchronization due to the time delay of the integrating circuit 20. Therefore, in the circuit shown in FIG. 1, the phase difference between the vertical synchronization detection signal b and the second pulse signals e and f is -1/3H in odd fields and 1/6H in even fields. Therefore, in odd fields, the second pulse signal e is always at a low level when the vertical synchronization detection signal b rises. Also, in an even field, at the rise of the vertical synchronization detection signal b, the second pulse signal f
is always at a high level. Therefore, the output of the output terminal Q of the D flip-flop circuit 24 is at a low level in odd fields (FIG. 2g), and at a high level in even fields (FIG. 2h).

(c) Problems to be solved by the invention However, the above discrimination circuit requires a pulse width conversion circuit to create a horizontal pulse with a pulse width of about 1/2H from the horizontal synchronization signal, making the circuit configuration complicated.

The present invention eliminates this drawback and provides a field discrimination circuit with a simple circuit configuration.

(d) Means for solving the problem The present invention includes a horizontal synchronization separation circuit that outputs a first pulse signal with a horizontal synchronization period from an input video signal, and a horizontal synchronization separation circuit that outputs a first pulse signal with a horizontal synchronization period from an input video signal. (H is a horizontal scanning period); a vertical synchronization signal detection circuit that detects a vertical synchronization signal and outputs a vertical synchronization detection signal; and the second pulse signal is connected to a D terminal. and a D flip-flop circuit which receives the vertical synchronization detection signal at a T terminal and outputs a field discrimination signal, wherein the pulse width conversion circuit converts the first pulse signal into the first pulse signal. A counter that is reset by a synchronized signal, counts the oscillation signal from the reference oscillation circuit, and outputs N-bit address data used to specify the address in the horizontal scanning direction of the memory that stores the video signal. A field discriminating circuit comprising: a circuit; and branching means for extracting the second pulse signal from a signal line that transmits the highest digit of the N bits.

(e) Effect The present invention has the above-mentioned configuration, and the pulse width is 1/2H.
The second pulse signal is taken out from the signal line that transmits the highest digit of the counter circuit that specifies the horizontal address of the memory. Then, the second pulse signal and the vertical synchronization detection signal are phase-shifted and compared by the D flip-flop, and a field discrimination signal is output.

(F) An embodiment of the present invention will now be described with reference to the drawings. Fig. 3 is a circuit diagram of the circuit of this embodiment, which is characterized in that the counter circuit 30 that determines the address in the horizontal scanning direction is also used as a pulse width conversion circuit. In Fig. 3, the same parts as in Fig. 1 are given the same reference numerals and duplicated explanations will be omitted.
In the figure, 32 is a video signal input terminal, 29 is a sync separation circuit, and 34 is an A/D converter. 36 is a frame memory equipped with two field memories. The field memories in this frame memory 36 are selectively written in by a field discrimination signal. 38 is a PLL oscillation circuit which oscillates at a frequency which is an integer multiple of the horizontal sync period in synchronization with the first pulse signal. The output of this oscillation circuit 38 may be divided to set the frequency to, for example, the color subcarrier frequency of about 3.58 MHz. In this manner, a clock signal is generated by this oscillation circuit 38. 30 is the first pulse signal c,
d or a count circuit which is reset by a signal synchronized with the first pulse signal and which designates a memory address in the horizontal scanning direction.
outputs 8-bit address data. In other words, 256 addresses can be specified in the horizontal scanning direction. However, if the sampling frequency is 3.58 MHz, for example, 227 (=
Since only a sampling of 3.58×10 ⁶ /525×30 is possible, address data from 227 to 256 is not used.
When it counts up to 128 (128/227H), it outputs a "1" signal (high level signal). 40 is a branch point for extracting the signal from this output terminal A7.

(g) Effects of the invention As described above, according to the invention, since the counter circuit for horizontal addressing of the memory can also be used to obtain the second pulse signal with a pulse width of 1/2H, a separate pulse width conversion circuit is required. Field discrimination can be performed with a simple configuration without the need for

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional field discrimination circuit.
FIG. 2 is a waveform diagram thereof. FIG. 3 is a circuit diagram of a field discrimination circuit in one embodiment of the present invention. a...Synchronization separation signal, c, d...First pulse signal, 12...Horizontal synchronization separation circuit, e, f...Second
Pulse signal, 16... Pulse width conversion circuit, b...
Vertical synchronization detection signal, 18...Vertical synchronization signal detection circuit, g, h...Field discrimination signal, 24...D
Flip-flop circuit, 38... oscillation circuit (reference oscillation circuit), 36... frame memory (memory),
30... Count circuit, 40... Branch point (branching means).

Claims (1)

[Claims for Utility Model Registration] A horizontal synchronization separation circuit that outputs a first pulse signal with a horizontal synchronization period from an input video signal, and a pulse width of this first pulse signal is approximately 1/2H (H is the horizontal scanning period). a pulse width conversion circuit that converts the second pulse signal into a second pulse signal; a vertical synchronization signal detection circuit that detects the vertical synchronization signal and outputs a vertical synchronization detection signal; A field discrimination circuit includes a D flip-flop circuit which receives a vertical synchronization detection signal at a T terminal and outputs a field discrimination signal, wherein the pulse width conversion circuit is reset by a signal synchronized with the first pulse signal. and a counter circuit that counts oscillation signals from the reference oscillation circuit and outputs N-bit address data used for specifying an address in the horizontal scanning direction of a memory that stores a video signal; A field discriminating circuit comprising branching means for extracting the second pulse signal from a signal line that transmits the highest digit.