JPS5896461A - Signal generator - Google Patents

Abstract

PURPOSE:To obtain a vertical synchronizing signal similar to a horizontal synchronizing signal even being lacked in it, by converting the counted value of a counter into a data of an arbitrary bit number with a decoder, and picking up each bit of data as a timing signal in parallel. CONSTITUTION:A video signal applied to an input terminal 1 is applied to a separation circuit 2, where the signal is separated into horizontal and vertical synchronizing signals. A clock generating circuit 5 generates a clock signal having a shorter period than that of the horizontal synchronizing signal and a counter 6 counts it. The count output is converted into a data having an arbitrary bit number at decoders 7, 8, and each bit of the data is outputted as each timing signal in parallel. The timing signal is true only when the count value is slightly larger than the number of clock signals generated in the maximum period of the horizontal synchronizing signal, and the signal after a prescribed time from the initializing timing is picked up as the vertical synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention can be used as a timing signal source for control when, for example, sampling and temporarily storing a video signal conforming to the NTSO standard, or reproducing the stored video signal as an image. The present invention relates to a signal generating device suitable for use.

For example, if you want to obtain a still image of a desired scene from an image captured by a video camera or an image received by a television receiver, a video corresponding to one screen of the desired scene may be obtained. The signal may be sampled and stored at a predetermined period, and then the stored video signal may be continuously displayed on a television receiver. In such a case, the sampling signal for performing the sampling is activated in complete synchronization with the horizontal synchronization signal in the video signal, and is always generated at the same constant cycle within all horizontal synchronization periods. A signal is required.

Conventionally, such sampling signals have been generated by signal generators using phase-lock technology, but the period of the sampling signal generated using 7-axis lock technology changes as the period of the horizontal synchronization signal fluctuates. The problem was that it fluctuated. For example, Jl! shown as pulse a&1 in (a) of FIG. dM'l['
When a sampling signal SM MP with a cycle indicated as pulses b0, bx, . When T fluctuates by T, 6 or T〆 as shown by pulse tLo, J□ or pulse &O% &21, the period of the sampling signal 13AMP which is 7A-locked to this horizontal synchronizing signal H8YN also becomes:
Pulse b b1□..., b□ゎ or pulse bO'
b21'..., one as shown by b8n! It changes rapidly. This conclusion
In the United States, when a video signal sampled and stored using such a sampling signal SAMP is reproduced, there is a problem in that the image becomes distorted.

In addition, signal generators using phase-lock technology had complicated circuit configurations, and it was rare to find circuit modifications that could be made at a membership fee.

In addition, this signal generator is capable of displaying stored video signals even when video (g-11) is not supplied.
It is necessary to generate each 櫨 timing tsukuji etc. which are rHJ M to the W1 period signal and these synchronization signals to start the song.

The present invention has been made in view of the above circumstances, and its purpose is to provide a second synchronization signal that is completely synchronized with the supplied first synchronization signal, and a second synchronization signal that is completely synchronized with the first synchronization signal that is supplied. It generates a timing signal of l [li or more, which is started synchronously and whose period or timing pattern within each synchronization period does not change at all, and which
If the synchronization signal is not supplied, a second synchronization signal having a period approximately equal to the period of the first synchronization signal is generated, and the synchronization signal is synchronized with the timing signal that starts to be generated at intervals of the second synchronization signal. An object of the present invention is to provide a signal generating device capable of generating a timing signal of. In order to achieve this object, the signal generating device according to the present invention is provided with a clock generating circuit, counts the clock signal generated by the clock generating circuit with a counter, and converts the counted value outputted by the counter into an arbitrary number of bits by a decoder. , and each bit of these data is uniformly outputted as a timing signal, and the timing signal corresponding to the significant bit of the data is particularly important when the count value of the counter is the first one. The signal is set to be true only when the number of clock signals that can be generated within the maximum period of the synchronization signal is set to be a true signal, and the counter is controlled by this timing signal and the first synchronization signal. After initialization, a signal having a predetermined time width from this initialization timing is extracted as a second synchronization signal.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment in which the present invention is applied to a synchronization signal generation device for video signals conforming to the NT80 standard. Below are two examples shown in this figure.
To explain using the value logic signals 11''' and @0'', 1
is an input terminal, and this input terminal 1 has an NT signal sent from, for example, a video camera or a TV receiver.
IO is supplied from a video signal V conforming to the SO standard. , I from the video signal V supplied to this input terminal 1
CO is supplied to the synchronous separation circuit 2.
11 circuit 2 receives the horizontal synchronizing signal H8Ylil (the first Q synchronizing signal is a pulse signal of @1" in this case) and the vertical synchronizing signal V8YNl (also 'I''' pulse signal) and separately outputs these synchronizing signals H8YMl and 'V8YJl.The horizontal synchronizing signal H8Yllrl output from this synchronizing separation circuit 2 is sent to the first OR gate (initialization circuit) 3. The vertical synchronizing signal V8YNl is supplied to one input terminal of the second OR gate 4.

Reference numeral 5 denotes a clock generation circuit that always generates a clock signal cboox of a constant period. The period of the clock signal Off, +OOK generated by the clock generating circuit 5 is set to be sufficiently shorter than the period of the horizontal synchronizing signal -jlli8YMl. This clock Confucian No. 1 cr,,o
ox is supplied to the clock input terminal OK of the counter 6. The counter 6 is the IPI of the permanent synchronization signal H8YNI.
An N1-bit counter (for example, an I (inary counter)) with sufficient counting capacity to count the clock signal 0'L00K that may occur within period a.
is zero-cleared (initialized) when the 11'' signal is supplied from the output terminal of the OR gate 3 to the clear input terminal OL, counts the clock signal 0LOOK supplied to the clock input electronic CTC, and outputs the counting result. Terminal group 0
8. Output from 0□. In this case, the output terminal group OK
From then on, the N8-bit code signal 0 corresponding to the lower N of the N1-bit count value obtained by the counter 6
11'l'l is output, and the output terminal group 0□0NT2
is output. The code signal 0NTI is supplied to the decoder 7, and the code signal 0NT2 is supplied to the decoder 8. The decoder 7 converts the code signal 0NT1 into N bit data and outputs each bit of these data in parallel as a timing signal. Its detailed configuration is shown in FIG. 3, for example. It comes to show.

In FIG. 3, the decoder 7 includes, for example, a read-only memory (hereinafter abbreviated as ROM) 7 &
The code signal 0M is input to the address input terminals A1 to MN□ of h bits in this ROM7m.
Tl is supplied.

Predetermined N4-bit binary data is stored in each of the addresses O1I to (M, -1) that are accessed by the code signal 01J'l'l. D1 to DN are data output terminals to which data of the code signal (address accessed by 7NT1) among addresses 011 to (ia, -z) is output, and these data output terminals Di-DM4 output timing signals. Signals T81 to 'r8N4 are respectively taken out.In this decoder 7, the code signal 0MTl changes, and each address of the ROM 7m changes from address 01)→address 1→...→( N5-1) If access is made sequentially like Ifjtllll→0chiji→..., each data output terminal Di-DI44 outputs, for example, according to each bit of data stored at each address of ROM7m. N4fli type timing signal T81-T shown in FIG.
AN, is output, and these timing signals TSL-TA
N4 is sent out from the output terminal group 9 shown in FIG. 2 via a buffer (not shown) or the like. Next, the decoder 8 converts the code signal C11T2 into parallel data of M bits, and outputs each bit of these data in parallel as a timing signal.
As shown in the figure, it becomes K. In FIG. 5, the decoder 8 is
For example, ; - code signal 01iT2 - code signal 0JT2 is supplied, and addresses 0 to (M) are supplied.

-1) Predetermined N bits of data are stored at each address of i. In this case, the first bit in each of these data is 11" only in the 0 to nh addresses, and is 10" in all other addresses. Also, l11 in each of these data. The th bit is the code signal cN'zz at the point in time when the counted value of the counter 6 becomes falsely larger than the number of p-switch signals 0LOOK that can occur in the maximum cycle of the horizontal synchronizing signal H8YNl.
(If this address is accessed by (M,
-2) Address) is set to ``1'', and other addresses are set to 10''.
The data output terminal Di of is connected to w via a buffer (not shown).
, is connected to the output terminal 10 shown in FIG.
data output terminal DN.

is connected to the other input terminal of the OR gate 3.

In the above part, if ICO is now being supplied from the video signal V, and therefore the horizontal synchronization signal m as shown in 0) in FIG. 6 is output from the synchronization separation circuit 2, then The counter 6 is initialized by this horizontal synchronizing signal H8YNl, and the code signal ONT1q (lIT2) becomes zero. At this time, the O1!- ground is accessed in the ROMga of the decoder 8, and the A timing signal TSSI as shown in Fig. 6 (←) is output (this timing signal TS81 is used as the second horizontal synchronization signal H8Ylil).Then, the counter 6 sequentially counts the clock signal CshiOOX. and,
The values indicated by the code signals 0NTI and om'rz increase sequentially from zero at regular intervals (in this case, the code 01iT
The increasing speed of l is more lucky than the increasing speed of OMT:Z). Therefore, during this period, output terminal group 1 outputs a timing signal TSL-18 as shown in FIG.
11, is output, and from the output terminal group 11, for example, the counting operation of the timing counter 6 as shown in FIG. , thereafter, the same operation as in the case described above is repeated. Therefore, in this case, (a) in Figure 6, ←
), a second synchronization signal H8YN2 that is completely synchronized with the first horizontal synchronization signal H8YNI is generated (rWJ
The pulses indicated by broken lines in (A) and (→ in the figure) are the horizontal synchronization signal H.
8YNI-), and within each period of these synchronization signals H8YIIl and H8YN2, the synchronization signal! l! It is activated in complete synchronization with fH8YNl, and the clock signal 0LOO! Various timings that are determined only by the 10 cycles, how the code signals ON'I'l and 0NT2 are output from the counter 6, and the data stored in each address of ROMT& and 8&, and which do not change at all. Signal TSI-TSN4, TS82~T
8 S ()I, -1) can be extracted.

In addition, in the above part, if the video signal V (I) ICO is not supplied, the counter 6
Although it is not initialized by 8YNI, when the counter 6 continues counting for a period slightly longer than the maximum period of the horizontal synchronizing signal H8YNl, the value indicated by the code signal ON'J'2 becomes (M, -2) in the ROM 8m. The value for accessing the address is reached, and at this time the timing signal T8811° is output as shown in Figure 6).
The counter 6 is initialized by this timing signal TssJc. Therefore, in this case, I
The second horizontal synchronizing signal H8YN2 is output at a slightly longer fixed period than when the CO signal is supplied. In this case, is it a timing signal? Sl~TSN4
．． ? 8B! VT8B (N, -1) is vzpx.

(Generated according to the same behavior as when [4 is supplied.

Next, the counter 12 is an H6-bit counter with sufficient counting capacity to count the number of horizontal synchronization signals within the vertical synchronization signal 01 period, and the clock input terminal OK of this counter 12 is connected to the second Horizontal synchronization signal asyN
i is supplied, and the clear input terminal a'L is connected to the output terminal of the OR gate 4. Further, the decoder 13 is
It converts the M〆knot count value of the counter 12 outputted from the output terminal group Q*@h of the caulking 12 into N bit data, and outputs each bit of these data in parallel as a timing signal. , similar to the decoder 7.8 above, K
It is composed of ROM. In this case, this decoder 1
The 1st bit of the ROM in 3 is @11' only in the 0-ny11 location, and the field bit is @11' at the time when the counter 12 counts the number of horizontal synchronization signals to be received within one vertical interval. The only address that is accessed is @1'', and arbitrary data is set at each address related to the other bits.

Then, the data output of the first bit of the ROM in this decoder 13 is sent to an output terminal 1 via a buffer 7 (not shown), etc.
The N7th bit data output of the ROM is supplied to the other input terminal of the OR gate 4, and the data output of the N7th bit of the ROM is supplied to the other input terminal of the OR gate 4.
The data outputs of the other bits of M are respectively supplied to the output terminal group 15 via buffers and the like.

According to these counter 12, decoder 13, and OR gate 4, when the video signal (1) is supplied, a second vertical synchronization signal VSYN2 that is completely synchronized with the first vertical synchronization signal VSYNI is output. Various timing signals can be taken out from the terminal 14, and can be activated in synchronization with each vertical synchronizing signal VSYNl and can be set in advance in the decoder 13. Furthermore, even when the video signal VEClll0 is not supplied, the second vertical synchronizing signal VBYM2 is output every time the second horizontal synchronizing signal H9YN2 is counted a predetermined number of times,
Also, within each cycle of these vertical synchronizing signals VBYH2, the ICO signal is supplied from V, and various timing signals similar to those of the famous bathhouses can be taken out.

As is clear from the above description, the signal generation device according to the present invention includes a clock generation circuit, a counter, a decoder, and an initialization circuit, and counts clock signals generated by the clock generation circuit with a counter. The count value output by this counter is converted into data of an arbitrary number of bits by a decoder, and each bit of these data is taken out in parallel as a timing signal, and the timing signal corresponding to a specific bit of the data is used to calculate the count value of the counter. The logical sum of this timing signal and the first 1-period signal is made such that the value becomes much larger than the number of clock signals that can occur within the maximum period of the first synchronization signal. The counter is initialized by the signal, and a signal having a predetermined time width from this initialization timing is taken out as the second synchronization signal.
First synchronization signal (a completely synchronized second synchronization signal can be extracted, and within each period of these synchronization signals, it is activated by the synchronization signal of '1lIJ1, and a predetermined cycle or timing pattern It is possible to obtain various timing signals that have the following characteristics and whose periods or timing patterns do not vary at all. Further, according to the present invention, even if the first synchronization signal is not supplied, it is possible to generate a second synchronization signal having a constant period approximately four times the same as that of the first synchronization signal, and Within each cycle of these second synchronization signals, various timing signals can be obtained that start generating at the same time as the second synchronization signal and whose cycles or timing patterns do not change at all.

Furthermore, according to the present invention, even if the first synchronization signal occasionally drops out, it is possible to obtain a second synchronization signal that does not drop out at all.

[Brief explanation of drawings]

Figure 1 is a time chart for explaining the operation of a conventional signal generator using phase lock technology, and Figure 2 is a time chart for explaining the operation of a conventional signal generator using phase lock technology.
3 is a circuit diagram showing a detailed structure of a decoder 70 in the same example; FIG. 4 is a time chart for explaining the operation of the decoder 7; FIG. FIG. 5 is a circuit diagram showing the detailed configuration of the decoder 8 in the embodiment, and FIG. 6 is a time chart illustrating the operation of the decoder 8. 3.4... Initialization circuit (OR gate), 5...
...Clock generation circuit, 6.12...Counter,
7.8.13...Decoder. Applicant: Nippon Musical Instruments Co., Ltd. CNTl Figure 4 Figure 6 400-

Claims (1)

[Claims] ■ A clock generation circuit that generates a clock signal with a sufficiently shorter period than the first synchronization signal supplied from the external S, ■ A counter that counts the clock signal, and ■ The count output of the counter as data of an arbitrary number of bits. and output each bit of these data in parallel as a timing signal, and a specific bit in the data is determined by the clock that the count value of the counter can be generated within each cycle of the first synchronization signal. an initialization circuit that supplies the counter as an initialization signal whose corresponding timing signal becomes true only when the number of signals is slightly larger than the number of signals; A signal generator whose main feature is to extract a time width signal as a second synchronization signal.