JPH02215280A - Synchronizing signal discriminator - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by counting the interval of a synchronizing signal in a master clock unit, preparing new mean data based on counted counting data and mean data, generating a window pulse on a time base through the use of it and discriminatingly extracting only the synchronizing signal at the correct interval. CONSTITUTION:The synchronizing signal inputted from an input terminal 1 is sent to a timing control circuit 2, and a rest signal A, a clock C and a mean synchronizing signal interval data set signal E are generated. A synchronizing signal interval counting circuit 3 is reset by the signal A, a count-up is executed for each master clock, the interval of the synchronizing signal is counted, and counted counting data B are outputted to a mean synchronizing signal interval data preparing circuit 4. Here, the circuit 4 is composed of a comparing circuit 8 to compare the counting data B with means data D and a mean data preparing circuit 9 to prepare the new mean data D by the timing of the clock C based on a deciding signal G. Thereafter, the new mean data D are outputted to a window generating circuit 5, extracted by a gate circuit 6 and outputted from an output terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization signal discriminating device used in a video signal recording/reproducing device such as a video tape recorder.

BACKGROUND OF THE INVENTION Various configurations have been considered in the prior art for obtaining precisely spaced synchronization signals from video signals. For example, between a sync signal and the next sync signal, a triangular wave is generated by charging a capacitor with a constant current and resetting it with the first sync signal, and by holding a sample slightly before the sync signal, it corresponds to the sync signal interval. A synchronization signal discriminator circuit generates a voltage that corresponds to the average synchronization signal interval, averages this voltage, creates a voltage corresponding to the average synchronization signal interval, creates a window around this voltage, and discriminates and extracts only synchronization signals with the correct interval. was there.

Problems to be Solved by the Invention However, the conventional configuration described above requires a triangular wave generation circuit, a sample hold circuit, a voltage generation circuit corresponding to the average synchronization signal interval, a window generation circuit, etc.
Since analog signal processing is performed, the number of components used increases, and the area for mounting the components also increases.

SUMMARY OF THE INVENTION The present invention addresses this problem and provides a synchronization signal discrimination circuit which has a simple configuration and discriminates and outputs only synchronization signals at correct intervals.

Means for Solving the Problems In order to solve the above problems, the present invention provides a counting means for counting the intervals of synchronization signals using a master clock and creating counting data, and increasing the average data by a predetermined value based on the counting data and the average data. or average data creation means for creating new average data by decreasing the average data; and window pulse creation means for generating a window pulse in a region where the next synchronization signal is generated from the synchronization signal 1H before, based on the average data. , extraction means for determining and extracting only synchronization signals at correct intervals based on the window pulses.

Effects of the present invention Due to the above-described configuration, there is no need to convert the synchronization signal interval time to voltage once, so the circuit configuration can be simplified compared to the conventional one, and the circuit can be configured with digital gate elements, making it suitable for LSI implementation. .

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a synchronization signal discriminator in one embodiment of the present invention. In the figure, 1 is an input terminal into which a synchronization signal extracted from a video signal reproduced from a recording medium is input, and 2 is a reset signal to a synchronization signal interval counting circuit 3 based on the synchronization signal, and an average synchronization signal interval. Average synchronization signal interval data acquisition clock C to data creation circuit 4
(hereinafter referred to as clock C) and a timing control circuit that creates an average synchronization signal interval data setting signal E to the window generation circuit 6; 6 extracts a synchronization signal based on the window pulse F output from the window generation circuit 6; death,
This is a gate circuit that outputs to the output terminal 7.

The synchronization signal discriminator of this embodiment configured as described above will be explained.

First, the synchronization signal input from the input terminal 1 is used to generate a reset signal and a clock C9 average synchronization signal interval data setting signal X in the timing control circuit 2, as shown in FIG. The synchronization signal interval counting circuit 3 is reset by the reset signal M, counts up the synchronization signal interval by counting up every master clock, and outputs the counted count data B to the average synchronization signal interval data creation circuit 4. .

FIG. 2 shows the configuration of the average synchronization signal interval data creation circuit 4, which includes a comparison circuit 8 that compares count data B and average data D, and a clock C New average data D at the timing of
It consists of an average data creation circuit 9 that creates the average data. If the count data B is larger than the average data D by this average data creation circuit 9B1 judgment signal G, change the average data D to the current value and create new average data D at the timing of the clock C. do.

Further, when the count data B is smaller than the average data D, the average data D is made smaller by a certain value than the current value, new average data D is created, and outputted to the window generation circuit 6.

In the window generation circuit 6, the average data D, which is a digital signal of predetermined bits, is input, and its complement is set at the timing of the average synchronization signal interval data setting signal X. After that, the master clock is counted and the window pulse F is correct. In order to extract the synchronization signal, it is generated a little earlier than the next synchronization signal. That is, the window pulse F is generated in the area where the next synchronization signal is generated from the synchronization signal 1H before, and the signal generated from the next synchronization signal is used for resetting. Also, the synchronization signal interval is window pulse F
If it is longer than the width of , it is reset at a certain count value before the primary synchronization signal.

If the window pulse F is generated a little earlier than the next synchronization signal, the gate circuit 6 extracts the synchronization signal and outputs it to the output terminal 7. If the window pulse F is not generated, the gate circuit 6 extracts the synchronization signal and outputs it to the output terminal 7. , the synchronization signal is not extracted.

As described above, according to the present embodiment, new average data is created by increasing or decreasing average data indicating the average interval of synchronizing signals by a predetermined value according to a change in the interval of synchronizing signals, and this new average data Based on this, only the synchronization signal with the correct interval is extracted over the entire window pulse, so there is no need to convert the interval of the synchronization signal into voltage, and the correct interval can be extracted from the reproduced synchronization signal with a simple configuration. It is possible to distinguish and extract only the synchronization signal.

Effects of the Invention As described above, according to the present invention, the interval between synchronization signals is counted in master clock units, new average data is created based on the counted count data and average data, and this average data is used to calculate the time axis. By generating window pulses on the
Since there is no need to convert the interval between synchronization signals into a voltage, there is no need to use components such as capacitors, resistors, and operational amplifiers as in the past, and the single circuit configuration can be simplified because everything can be constructed using only digital gate elements. , also LS
It exhibits excellent effects such as being suitable for I conversion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchronization signal discriminator according to a second embodiment of the present invention, FIG. 2 is a block diagram of the average synchronization signal interval data creation circuit, and FIG. 3 is a waveform diagram showing the operation of each part. It is. 2...-timing control circuit, 3... synchronization signal interval counting circuit, 4... average synchronization signal interval data creation circuit, 6... window generation circuit,
6...Gate circuit, End...Comparison circuit,
8...Average data creation circuit. Name of agent: Patent attorney Shigetaka Awano and 1 other person 2
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Claims (1)

[Claims] Counting means that counts the interval of synchronization signals using a master clock to create count data; and average data creation means that increases or decreases the average data by a predetermined value based on the counted count data and average data to create new average data. and a window pulse generating means for generating a window pulse in a region where the next synchronization signal is generated from the synchronization signal 1H before, based on the average data, and only synchronization signals at correct intervals based on the window pulses. and extraction means for determining and extracting a synchronous signal.