JPS594333Y2 - Light pen field of view position detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting the center of the field of view of a light pen used as an interactive type in a cathode ray tube display device of the Dorato scanning type.

As is well known, a light pen uses a charging conversion element to detect display light from a scanning beam on the screen of a cathode ray tube that is manually inputted through a light receiving window provided at the tip of the light pen, and this detected signal is sent to an amplifier, comparator, etc. The light pen circuit formed allows the TTL of multiple pulse trains to be
It is configured to extract it as a level signal.

Then, by using the pulse train signal extracted by placing the light pen on an arbitrary position on the screen, and by knowing the address of the well-known fresh memory at the time of this detection, The position of the object can be detected.

In other words, the scanning beam of the cathode ray tube detected by the light pen's light receiving window.In other words, the raster light passes several times within the field of view of the light pen's light receiving window. must find the center position of this field of view.

Therefore, conventionally, this type of circuit detects a plurality of pulses of a pulse train signal generated by raster light passing through the field of view, and calculates the number of pulses to determine the position.

However, as shown in Figure 1A, when this detected pulse is detected, the peak value of the pulse near the center of the light pen field of view is high and stable, but it becomes unstable as it approaches the periphery of the field of view. Detected as a pulse with a low peak value.

The pulse width of this pulse also changes depending on the brightness of the raster light, and tends to widen as the brightness increases.

Since the light pen is applied to the screen by the user's hand, the angle at which it is applied is not stable.

Therefore, the brightness detected by the light receiving window was not constant and stable.

Further, in the case of a color cathode ray tube, the afterglow time varies depending on the phosphor of the cathode ray tube, and the level of the above-mentioned detection pulse changes.

Therefore, the number of pulses and their level corresponding to the raster light detected by the photoelectric conversion element of the light pen circuit differ as shown in Figure 1A and B, and the number and level of pulses corresponding to the raster light detected by the photoelectric conversion element of the light pen circuit differ as shown in Figure 1C. In order to convert the amplified detection pulse to a TTL level, a comparator etc. is used to slice it at the level shown by the dashed line.The output waveform of the comparator etc. is as shown in Figures 1 and E.
It is detected as a pulse train signal with different pulse widths and pulse numbers.

As a result, the rise and fall times of the pulse train signals differ.

Normally, this pulse train signal is used based on the rise of a comparator etc. due to the stability of the pulse, but as mentioned above, when the rise time changes depending on the brightness of the cathode ray tube screen and the background color, when the light pen is applied to the same place. Even though the detection position is changed, an error occurs.

This proposal was made in view of this point, and its purpose is to detect even if the number of pulses in the pulse train signal detected by the light pen changes due to changes in brightness or afterglow characteristics of the phosphor. An object of the present invention is to provide a field-of-view position detection device for a light pen that has a circuit that always creates and outputs a pulse that rises at the center position of a plurality of detected pulses of a pulse train signal even if the detected pulse width changes. It is something to do.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a circuit configuration diagram showing an embodiment of the present invention, in which 1 is a light pen circuit, 2 is a pulse extraction circuit, 3 is a digital-to-analog converter (hereinafter referred to as a D/A converter),
4 is a monostable multivibrator (hereinafter simply referred to as monomulti), 5 is a first latch circuit, 6 is a counter circuit that outputs address data of a refresh memory (not shown), and 7 is a second latch circuit. be.

As described above, the light pen circuit 1 is constituted by a well-known photoelectric conversion element, an amplifier, a comparator, etc., and outputs a pulse train signal as shown in the first diagram or E.

This pulse train signal is input to the AND gate 21 of the pulse extraction circuit 2.

The pulse sampling circuit 2 is configured as follows.

First, 22 is a synchronization signal input terminal into which a vertical synchronization signal VD is input, 23 is a first counter constituted by a well-known binary up counter, and 24 is a second counter, in which a count value n is input from the first counter 23. This is a well-known down counter that counts down from n and outputs a borrow signal when the count value n reaches zero.

25 is a first flip-flop, 26 is a second flip-flop constituted by a T-type so-called toggle flip-flop, and 27 is a third flip-flop.

Further, 281, 282 and 291.292 are well-known inverters, and the first and third flip-flops 25.2
In order to make each output pulse of 7 a narrow pulse,
A clear pulse is applied to each clear terminal CLR with an appropriate delay from the rise of each output pulse.

The operation of the embodiment circuit shown in FIG. 2 will be explained below with reference to FIG. 3.

First, when the vertical synchronizing signal VD shown in FIG. 3 is input to the first flip-flop 25, at the same time as this VD rises, the vertical synchronizing signal VD shown in FIG. A load signal like this is output from the Q terminal.

As mentioned above, this load signal is cleared by the output from the first flip-flop 25 via the inverters 281 and 282, so it becomes a narrow pulse as shown in FIG.

On the other hand, the output of the Q terminal having the opposite polarity to the load signal of the 0 terminal is inputted to the clock input terminal CK of the second flip-flop 26 at the next stage.

The second flip-flop 26 has this clock input terminal CK.
The output is inverted every time the signal input to the input signal, that is, the signal of the opposite polarity shown in FIG. 3, falls, and a frame signal that is inverted every one field period as shown in FIG. 3 is output.

Therefore, this frame signal is output as an output of one frame period of the same polarity every odd or even field.
It will be output from the flip-flop 26.

Such a frame signal at the Q terminal of the second flip-flop 26 is input to the clock input terminal CK of the third flip-flop 27 at the next stage.

As shown in the third diagram, the third flip-flop 27 creates a narrow pulse every time the frame signal rises, and outputs it from its 0 terminal.

Therefore, the pulse outputted from this Q terminal is inputted to the clear terminal CLR of the first counter 23 as a pulse signal outputted every frame period.

As a result, the count value of the first counter 23, which will be described later, is cleared by this pulse signal.

Incidentally, the above-mentioned frame signal is branched from the output of the Q terminal of the second flip-flop 26 and is also applied to the gate input terminal of the AND gate 21.

As a result, the gate of this AND gate 21 is opened and closed every frame period during one field period.

Therefore, the pulse train signals ■, ■ as shown in FIG. 3A detected by the light pen input from the signal input terminal 1
is applied to the clock input terminal CK of the first counter 23 as a pulse train signal detected during one field period of the same field, either odd or even.

As a result, the first counter 23 counts the number of pulses of such a pulse train signal, for example, a signal such as ■ every frame period.

In other words, if the number of pulse train signals is now // 5 // as shown in Figure 3 A, the output waveform of the first counter 23 at this time will be as shown in Figure 3. .

By the way, the output terminals QA and QB of this first counter 23
, Qc, and QD, the QA terminal is open 1, the QB terminal is connected to the A terminal of the input of the second counter 24, the Qo terminal is connected to the B terminal, and the QD terminal is connected to the C terminal.

Therefore, when the number of pulses of the above-mentioned pulse train signal is 2n or 2n+1, the first counter 2 that counts this
When inputting the count value of 3 to the second counter 24, it is always input as the count value n.

Here, the D terminal of the input of the second counter 24 is grounded so that it is always zero.

As a result, in the case of the above-mentioned pulse number "5", the count value n input to the second counter 24 becomes 2".

As described above, the timing at which such a count value n is transferred to the second counter 24 is when a load signal as shown in FIG. 3 is applied to the load terminal LOAD of the second counter 24.

Therefore, the second counter 24 is loaded every field period and holds the count value n output from the first counter 23.

On the other hand, the output of the AND gate 21, that is, the pulse train signal is branched and input to the clock input terminal CK of the second counter 24.

Therefore, the second counter 24 counts down the held count value n each time one pulse of the pulse train signal is input.

At this time, the pulse train signal that causes the second counter 24 to count down is a signal detected in the same field, either odd or even. Unlike the pulse train signal (2) in a frame period, the pulse train signal (2) detected in the same field period in the next frame period, for example, is a pulse train signal (2) in FIG.

Therefore, the second counter 24 counts down such a pulse train signal (2) as a clock signal input, and outputs a signal having a waveform as shown in FIG.
, output from QD.

Further, the second counter 24 stores the count value n held in this way.
When the count value reaches zero, terminal B
A borrow signal is output from ORROW.

Therefore, in the case of the above-mentioned count value "2", as shown in FIG.
2'', 1'', 0'' are counted, and a borrow signal is output at the same position as this third pulse.

This results in the pulse train signal being located at the center of the pulse train signal ■ detected in the previous frame period.

That is, the borrow signal output from the second counter 24 is output every 11 frames at the same timing as the pulse closest to the center of the field of view of the light pen among the plurality of pulses of the pulse train signal detected by the light pen. It is something that will be done.

By the way, each output terminal QA of the first counter 23.

The outputs of QB, Qo, and QD are branched to the first latch circuit 5.
input terminals ID, 2D, 3D, and 4D respectively.

Therefore, the first latch circuit 5 receives the count value 2n or 2n+1 from the first counter 23.

On the other hand, this first latch circuit 5 is connected to the first flip-flop 2.
The output of the Q terminal of No. 5 is branched and input to the clock input terminal CK.

As a result, the first latch circuit 5 outputs the count value 2n or 2n+ at the same timing as the output inversion of the second flip-flop 26, that is, at the rising edge of the vertical synchronizing signal VD.
Latch 1.

This latched count value corresponds to the number of pulses of the detected pulse train signal.

The count value latched by the first latch circuit 5 is input to the D/A converter 3.

The D/A converter 3 includes a decoder 31. Inverter 321-3
2m (m is any positive integer), variable resistors 331 to 33
m, and diodes 341 to 34m for preventing flow.

This D/A converter 3 decodes the count value inputted from the first latch circuit 5 using a decoder 31, and outputs a variable resistor 331 to 33m corresponding to the input count value.
The voltage set by is outputted via the diodes 341 to 34m.

The voltage output from this D/A converter 3 is monomulti 4
is applied to the DC voltage application terminal 41 of.

As is well known, this terminal 41 is connected to a time constant circuit formed by a resistor 42 and a capacitor 43 that determines the time constant of the monomulti 4. The pulse shown in FIG.

Therefore, the monomulti 4 is set by the leading edge of the pulse input to the T terminal, and is reset after the elapse of the time constant determined by the above-mentioned time constant circuit to invert the output of its 0 terminal.

By the way, as is well known, in the monomulti 4, when the DC voltage applied to the terminal 41 changes, the time constant changes even if the constant of the time constant circuit, that is, the values of the resistor 42 and the capacitor 43 are kept constant.

In this proposal, depending on the voltage output from the D/A converter 3,
The time constant of this monomulti 4 can be varied.

In other words, in this case, when the brightness of the cathode ray tube screen is high, the output pulse width of the Q terminal becomes longer, and when the brightness is low, or when the phosphor with a long afterglow time is exposed to the phosphor, the rusk light is Figure 1C by being guessed
As shown in FIG. 2, when the output level of the light pen circuit 1 is low, the time constant is varied so that the output pulse width of the 0 terminal changes in the direction of becoming shorter.

This operation will be explained below.

First, the pulse shown in Figure 3, which is input to the T terminal of the monomulti 4, has its leading edge position different depending on the change in the level detected by the charging element, as shown in Figure 1 and enlarged in E. .

Therefore, if position detection is performed using this as a reference, an error will occur.

Therefore, a period of 1/2 of the width of the pulse input to this T terminal is calculated in advance for each pulse number of the pulse train signal output from the light pen circuit 1, and the time constant of the monomulti 4 is determined according to the number of pulses. The output voltage of the D/A converter 3 is set by the variable resistors 331 to 33m so as to match each of the above-mentioned 1/2 periods.

As a result, when the number of pulses of the pulse train signal, that is, the count value of the first latch circuit 5 is "1" as shown in FIG. The width t of this pulse is set by the leading edge of the pulse shown
It is reset after the elapse of a time constant t2 that coincides with a period of 1/2.

Therefore, a signal as shown in FIG. 1G is output to the 0 terminal of the monomulti 4.

Further, as shown in the first diagram, when the number of pulses of the pulse train signal, that is, the count value of the first latch circuit 5 is "5", the monomulti 4 outputs the signal H input to the T terminal in FIG. Set by the leading edge of the pulse shown.

On the other hand, the D/A converter 3 applies a voltage corresponding to this count value "5" to the terminal 41 of the monomulti 4.

As a result, the monomulti 4 has a pulse width t shown in FIG.
It is reset after the elapse of the time constant t4, which coincides with a period of 1/2 of 3, and outputs a signal as shown in Figure 1 to the 0 terminal.

In this way, the time constant of the monomulti 4, that is, the metastable period is the count value 2n or 2n latched in the first latch circuit 5.
It is varied by the applied voltage from the D/A converter 3, which is set in advance according to +1.

As a result, the trailing edge of the signal output from the monomulti 4, that is, the start of the stable period, always maintains the pulse width center of the central pulse among the plurality of pulses of the pulse train signal.

In the present invention, the stable period signal outputted from the 0 terminal of the monomulti 4 is used as a latch pulse for horizontal and vertical address data.

A counter circuit 6 and a second latch circuit 7 shown in FIG. 2 are an embodiment circuit for latching a horizontal address counter using a signal output from the monomulti 4, and the same applies when latching vertical address data. Therefore, only this embodiment will be described below.

In the counter circuit 6, 61 is a start-stop oscillator, 62 is a monomulti, 63 is a flip-flop, 64 is an inverter, and 65 is an address counter.

First, the start/stop oscillator 61 generates clock pulses for displaying data in the horizontal direction of the screen read out from the well-known fresh memory corresponding to picture elements on the screen on the cathode ray tube.

This clock pulse is oscillated in synchronization with the horizontal synchronization signal HD.

The monomulti 62 is triggered at the leading edge of the horizontal synchronization signal and inverts the output of the 0 terminal after a predetermined time constant has elapsed.

This output is input to the clock input terminal CK of the next-stage flip-flop 63.

The flip-flop 63 is set by the rising edge of this inverted output from the monomulti 62, and releases the clear state of the address counter 65 in the next stage.

When the address counter 65 is released from the clear state, it starts counting clock pulses manually input from the start-stop oscillator, and when a predetermined count value is reached, it creates and outputs a carry signal.

This carry signal is formed by a single pulse and is applied to the clear terminal CLR of the above-mentioned flip-flop 63 via the inverter 64.

Therefore, the flip-flop 61 is reset by the carry signal, and the address counter 65 receives its output and enters the clear state.

As a result, the address counter 65 counts a predetermined number of clock pulses in one horizontal scanning period.

The count value of this address counter 65 is sequentially counted by the second stage of the next stage.
It is output to the latch circuit 7.

The second latch circuit 7 receives a signal output from the 0 terminal of the monomulti 4 described above to its clock input terminal CK, and outputs the signal from the address counter 65 described above at the rising timing of the input signal. Hold the numerical value.

As described above, the count value of the output of the address counter 65 indicating the position on the screen at the beginning of the stable period signal output from the monomulti 4, that is, the address data is held.

Therefore, as mentioned above, the starting edge of the stable period signal is the center of the pulse when the rusk light closest to the center of the light pen's field of view is detected, so the above address data held in the second latch circuit 7 is This data indicates the position closest to the center of the light pen field of view.

As described above, the present invention always detects the most stable pulse center position close to the center of the field of view of the light pen, even if the brightness of picture elements on the screen changes.

As a result, according to the present invention, the pulse train signal output from the light pen circuit is unstable due to changes in the brightness of the entire cathode ray tube screen, and when it is unstable due to changes in the brightness of the display data itself within the field of view of the light pen. Therefore, it is possible to realize a detection device that is less susceptible to the effects of the present invention.

Note that the display timing of the data read from the memory on the screen and the latch timing of the address data corresponding to the memory data display position differ depending on the memory access time, etc. In the case of a circuit that uses a processing device, it is corrected by software, or if such software is not used, it is corrected by installing an arithmetic circuit that adds or subtracts a fixed value to the determined position data. .

Since this does not affect the gist of the case, the details will be omitted.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram for explaining the device according to the present invention;
The figure is a wiring diagram showing the circuit of the first embodiment of the present invention, and FIG. 3 is a waveform diagram showing the operation of the main part of the circuit of FIG. 2. 6...Address counter, 1...Light pen circuit, 2...Pulse sampling circuit, 3...
...Digital analog converter, 4...Mono multivibrator, 7...Latch circuit.

Claims (1)

[Claims for Utility Model Registration] By counting clock pulses that are synchronized with horizontal or vertical synchronizing signals and dividing one scanning period into equal intervals, addresses in fresh memory can be determined that correspond to the positions of picture elements on the cathode ray tube screen. In a cathode ray tube display device equipped with an address counter that outputs data, a light pen circuit outputs a pulse train signal corresponding to the number of raster lights that pass within the field of view of a light pen applied to the screen of the cathode ray tube. , a pulse extraction circuit that extracts and outputs only the pulse located at the center of the pulse train signal; a digital-to-analog converter that counts the number of pulses of the pulse train signal and outputs a voltage according to the counted value; The metastable period is varied according to the voltage output from the digital-to-analog converter, is set by the leading edge of the pulse extracted by the pulse extraction circuit, and is set by the elapsed period of 1/2 of the width of the extracted pulse. A monostable multivibrator that outputs a signal that is always reset later, and a latch circuit that latches the address data output from the address counter as light pen position detection data by the signal output from the monostable multivibrator. Light pen visual field position detection device.