JPS6358513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention can be used as a timing signal source for control when, for example, sampling and temporarily storing a video signal conforming to the NTSC standard, or reproducing the stored video signal as an image. The present invention relates to a signal generating device suitable for use.

For example, images captured with a video camera,
Alternatively, if you want to obtain a still image of a desired scene from images received by a television receiver, a video signal corresponding to one screen of the desired scene is sampled at a predetermined period and stored. , and then the stored video signal may be continuously displayed on a television receiver. In such a case, the sampling signal for performing the sampling is activated in complete synchronization with the horizontal synchronization signal in the video signal, and is always generated at the same constant cycle within all horizontal synchronization periods. A signal is required.

Conventionally, such sampling signals have been generated by signal generators using phase-lock technology, but the period of the sampling signal generated using phase-lock technology varies as the period of the horizontal synchronization signal changes. I had a problem with putting it away. In other words, phase lock technology cannot track frequency and period in real time,
Since the frequency always reaches its original value with a time delay, the sampling frequency also deviates from its original value during that time, resulting in temporal distortion of the sampling time. If such temporal distortion occurs, wow and flutter may occur when an image signal is generated, distorting the image, or in severe cases, causing the synchronization signal to skip. For example, pulse A in Figure 1
Horizontal synchronization signal HSYN with period T denoted as a ₀ , a ₁
On the other hand, when a sampling signal SAMP with a period T/n shown as pulses b ₀ , b ₁ , _... , bo in b of the figure is generated, the period T of the horizontal synchronizing signal HSYN is equal to the pulse a ₀ , a ₁₁ or pulses a _{0 and} a ₂₁ , the period T/ _n of the sampling signal SAMP phase-locked to this horizontal synchronizing signal HSYN also changes to the pulse
b ₀ , b ₁₁ , ..., b _1o or pulse b ₀ , b ₂₁ , ...
..., it fluctuates to T ₁ /n or T ₂ /n as shown by b _2o . As a result, when a video signal sampled and stored using such a sampling signal SAMP is reproduced, a problem arises in that the image becomes distorted. Further, the signal generating device using the phase lock technology not only has a complicated circuit configuration, but also has the problem of requiring adjustment of the circuit.

In addition, this type of signal generator uses a horizontal synchronizing signal,
It is necessary to generate a vertical synchronization signal and various timing signals that start generating in synchronization with these synchronization signals.

This invention was made in view of the above circumstances, and its purpose is to
a second synchronization signal that is completely synchronized with the synchronization signal of the synchronization signal; and one or more types of timing that are activated in synchronization with the first periodic signal and whose period or timing pattern does not vary at all within each synchronization period. If the first synchronization signal is not supplied, a second synchronization signal having a period approximately equal to the period of the first synchronization signal is generated, and the second synchronization signal is generated in synchronization with the second synchronization signal. It is an object of the present invention to provide a signal generator capable of generating a timing signal similar to the timing signal to be started. In order to achieve this object, the signal generating device according to the present invention is provided with a clock generating circuit, and counts the clock signals generated by the clock generating circuit with a counter.
The count value output by this counter is converted into data with an arbitrary number of bits by a decoder, and each bit of this data is output in parallel as a timing signal, and a timing signal corresponding to a specific bit of the data is output. In particular, the timing signal is made to become a true signal only when the count value of the counter becomes slightly larger than the number of the clock signals that can occur within the maximum period of the first synchronization signal. and the first synchronization signal, the counter is initialized, and a signal having a predetermined time width is extracted from this initialization timing as a second synchronization signal.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment in which the present invention is applied to a synchronization signal generator for video signals conforming to the NTSC standard. The embodiment shown in this figure will be explained below using binary logic signals "1" and "0." 1 is an input terminal, and input terminal 1 is used to transmit signals from, for example, a video camera or a television receiver. A video signal VIDEO that complies with the NTSC standard is supplied. The video signal VIDEO supplied to this input terminal 1 is supplied to a synchronization separation circuit 2. The synchronous separation circuit 2 is
Horizontal synchronization signal SYN1 from the video signal VIDEO
(first synchronization signal, in this case a pulse signal of "1") and vertical synchronization signal VSYN1 (also a pulse signal of "1"), and separate these synchronization signals HSYN1 and VSYN1, respectively. This is what is output to. The horizontal synchronization signal HSYN1 output from the synchronization separation circuit 2 is supplied to one input terminal of the first OR gate (initialization circuit) 3, and the vertical synchronization signal VSYN1 is supplied to one input terminal of the second OR gate 4. has been done. Reference numeral 5 denotes a clock generating circuit that always generates a clock signal CLOCK with a constant period. The period of the clock signal CLOCK generated by this clock generation circuit 5 is equal to the period of the horizontal synchronization signal
It is set sufficiently shorter than the period of HSYN1. This clock signal CLOCK is supplied to the clock input terminal CK of the counter 6. The counter 6 is
It is an N1 _- bit counter (for example, a binary counter) having a counting capacity sufficient to count the clock signal CLOCK that may be generated within one period of the horizontal synchronizing signal HSYN1. This counter 6 is
When a "1" signal is supplied from the output terminal of the OR gate 3 to the clear input terminal CL, it is cleared to zero (initialized), the clock signal CLOCK supplied to the clock input terminal CK is counted, and the counting result is output to the output terminal. Output from groups O ₁ and O ₂ . in this case,
The output terminal group _O1 outputs an N2 _- bit code signal CNT1 corresponding to the lower _N2 bits of the N1-bit count value obtained by _the counter 6;
The output terminal group _O2 corresponds to the upper N ₃ bits of the count value obtained by the counter 6.
An N3 _- bit code signal CNT2 is output. The code signal CNT1 is supplied to the decoder 7, and the code signal CNT2 is supplied to the decoder 8.
The decoder 7 converts the code signal CNT1 into N4 _- bit data and outputs each bit of this data in parallel as a timing signal. Its detailed configuration is shown in FIG. 3, for example. Become. In this FIG. 3, the decoder 7
consists of a read-only memory (hereinafter abbreviated as ROM) 7a having M ₁ addresses that can be accessed by, for example, the code signal CNT1,
The code signal CNT1 is supplied to the N2 _- bit address input terminals A1 to _AN2 in the ROM 7a. Predetermined _N4- bit binary data is stored in each address from address 0 to address ( _M1-1 ) accessed by this code signal CNT1. D1 to DN ₄ are the code signals from addresses 0 to (M ₁ -1)
This is a data output terminal to which data at the address accessed by CNT1 is output, and timing signals TS1 to TSN ₄ are output from these data output terminals D1 to DN ₄ .
are being taken out individually. However, in this decoder 7, the code signal
CNT1 changes and each address of ROM7a becomes address 0 →
Address 1→……→(M ₁ -1) Address→Address 0→……
If the data output terminals D1 to _DN4 are sequentially accessed as shown in FIG.
N ₄ types of timing signals TS1~ as shown in the figure
TSN ₄ is output and these timing signals TS1~
The TSN ₄ is sent out from the output terminal group 9 shown in FIG. 2 via a buffer (not shown) or the like. Next, the decoder 8 converts the code signal CNT2 into N5 _- bit parallel data, and outputs each bit of this data in parallel as a timing signal. Its configuration is shown in FIG. It comes to show. In FIG. 5, the decoder 8 is composed of a ROM 8a having M addresses that can be accessed by the code signal CNT2, for example.
The code signal CNT2 is supplied to the address input terminals A1 to _AN3 in 8a, and the code signal CNT2 is supplied to the address input terminals A1 to AN3 at address 0 to ( _M2
-1) Predetermined _N5 bits of data are stored at each address. In this case, the first bit in each of these data is "1" only at addresses 0 to _nh , and "0" at all other addresses.
It is becoming. Also, N ₅ in each of these data
The th bit is the address accessed by the code signal CNT2 (this address For example, the address (M ₂ -2)) is "1", and the other addresses are "0". And ROM8a
The data output terminal D1 of is connected to the output terminal 10 shown in FIG. 2 via a buffer (not shown), etc.
The data output terminals D ₂ to D (N ₅ -1) of the ROM 8a are connected to the output terminal group 11 via a buffer (not shown), and the data output terminal DN ₅ of the ROM 8a
is connected to the other input terminal of the OR gate 3.

In the above part, now the video signal VIDEO
Therefore, the horizontal synchronization signal HSYN1 as shown in FIG.
is output, this horizontal synchronization signal HYSN1
The counter 6 is initialized by the code signal
CNT1 and CNT2 begin to show zero. At this time, address 0 is accessed in the ROM 8a of the decoder 8, and the timing signal TSS1 as shown in FIG.
used as HSYN2). From then on, counter 6
sequentially counts the clock signal CLOCK,
The values indicated by the code signals CNT1 and CNT2 increase sequentially from zero at regular intervals (in this case, the values indicated by the code signals
The increase speed of CNT1 is faster than the increase speed of CNT2). Therefore, during this period, the output terminal group 9 outputs timing signals TS1 to TSN ₄ as shown in FIG. 4, for example, and the output terminal group 11 outputs a timing signal TSS2 as shown in FIG. 6C, for example. and other timing signals
TSS3 to TSS (N ₅ −1) are output. In this way, the counting operation of the counter 6 progresses, and when the next horizontal synchronization signal HSYN1 is output from the synchronization separation circuit 2, the counter 6 is initialized again at this point, and from then on, the operation is exactly the same as in the case described above. Repeated. Therefore, in this case,
As shown in (B), a second synchronization signal HSYN2 that is completely synchronized with the first horizontal synchronization signal HSYN1 is generated (the pulses indicated by the broken lines in A and B in the figure indicate the case where the period of the horizontal synchronization signal HSYN1 fluctuates). ), and within each period of these synchronizing signals HSYN1 and HSYN2, they are activated in complete synchronization with the synchronizing signal HSYN1, and the period of the clock signal CLOCK and the code signals CNT1 and CNT2 from the counter 6 are activated.
The various timing signals TS1 to TS1, which are determined only by the way the data is retrieved and the data stored in each address of ROM7a and ROM8a, do not change at all.
TSN ₄ and TSS2 to TSS (N ₅ −1) can be extracted.

In addition, in the above part, the video signal VIDEO
is not supplied, the counter 6 is not initialized by the horizontal synchronizing signal HSYN1, but if the counter 6 continues counting for a period slightly longer than the maximum period of the horizontal synchronizing signal HSYN, the code signal CNT2 The value indicated by (M ₂ −
2) The value accessing the address is reached, and at this time the 6th
Since the timing signal TSSN ₅ will be output as shown in Figure D, this timing signal
Counter 6 will be initialized by TSSN ₅ . Therefore, in this case, the second horizontal synchronization signal HSYN2 is output at a slightly longer fixed period than when the VIDEO signal is supplied. That is, by the above operation, the timing signal TSSN5 is forcibly sent out at a predetermined time, so that the counter is always initialized. Therefore, for example, even if HSYN1 is not generated from the synchronization separation circuit 2 for some reason, the timing signal used as the horizontal synchronization signal is output from the decoder 8 at the time when the horizontal synchronization signal of the video signal VIDEO is generated. TSS1 (HSYN2) is always generated, and the counter 6 is initialized by the timing signal TSSN5 after the timing signal TSS1 is generated. As described above, an accurate horizontal synchronization signal can be reliably obtained, and no disturbance occurs in the image. In this case, the timing signal TS1~
TSN ₄ and TSS2 to TSS (N ₅ -1) are generated according to the same operation as when the VIDEO signal is supplied.

Next, the counter 12 is a N6 _- bit counter having a counting capacity sufficient to count the number of horizontal synchronizing signals within one cycle of the vertical synchronizing signal, and the clock input terminal CK of this counter 12 is connected to the clock input terminal CK. The clear input terminal CL is connected to the output terminal of the OR gate 4. Further, the decoder 13
The same counter 1 output from output terminal group O ₁ of 2
2 to N _6- bit data, and outputs each bit of this data in parallel as a timing signal, similar to the decoders 7 and 8.
Consists of ROM. In this case, the first bit of the ROM in this decoder 13 is O~n _v
Only the address is “1”, and the _7th bit of N is
Only the address accessed when the counter 12 counts the number of horizontal synchronization signals that should be present within one vertical synchronization period is "1", and arbitrary data is set in each address related to other bits. .
The data output of the 1st bit of the ROM in the decoder 13 is supplied to the output terminal 14 via a buffer (not shown), and the data output of the _N7th bit of the ROM is supplied to the other input terminal of the OR gate 4. The data output of the ROM and other bits is supplied to the output terminal group 15 via a buffer or the like.

Therefore, these, counter 12, decoder 1
3. According to ORGATE 4, the video signal VIDEO
is supplied, the first vertical synchronization signal
Second vertical sync signal fully synchronized to VSYN1
VSYN2 can be taken out from the output terminal 14, and various timing signals that are activated in synchronization with each vertical synchronization signal VSYN1 and can be set in advance in the decoder 13 can be taken out. Furthermore, even when the video signal VIDEO is not supplied, the second vertical synchronizing signal HSYN2 is activated every time the second horizontal synchronizing signal HSYN2 is counted a predetermined number of times.
VSYN2 is output and these vertical synchronization signals
A timing signal similar to that when the VIDEO signal is supplied can be extracted within each cycle of VSYN2.

As is clear from the above description, the signal generator according to the present invention includes a clock generation circuit, a counter, a decoder, and an initialization circuit, and counts the clock signals generated by the clock generation circuit with the counter. The count value output by this counter is converted into data of an arbitrary number of bits by a decoder, each bit of this data is taken out in parallel as a timing signal, and the timing signal corresponding to a specific bit of the data is sent to the counter. is true only when the count value of is slightly larger than the number of clock signals that can occur within the maximum period of the first synchronization signal, and the OR signal of this timing signal and the first synchronization signal The counter is initialized by a second signal having a predetermined time width from this initialization timing.
Since I tried to extract it as a synchronization signal of
It is possible to extract a second synchronization signal that is completely synchronized with the synchronization signal of It is possible to obtain various timing signals that have the following characteristics and whose periods or timing patterns do not vary at all. Further, according to the present invention, even if the first synchronization signal is not supplied, it is possible to generate a second synchronization signal having a constant period substantially similar to that of the first synchronization signal, and also Within each cycle of the second synchronization signal, it is possible to obtain various timing signals that start generating at the same time as the second synchronization signal and whose cycles or timing patterns do not change at all. Further, according to the present invention, even if the first synchronization signal occasionally drops out, it is possible to obtain a second synchronization signal that does not drop out at all.

[Brief explanation of drawings]

Fig. 1 is a time chart for explaining the operation of a conventional signal generator using phase lock technology, Fig. 2 is a circuit diagram showing the configuration of an embodiment of the present invention, and Fig. 3 is a circuit diagram showing the configuration of an embodiment of the present invention. A circuit diagram showing the detailed configuration of the decoder 7, FIG.
FIG. 5 is a circuit diagram showing the detailed configuration of the decoder 8 in the embodiment, and FIG. 6 is a time chart for explaining the operation of the decoder 8. 3, 4...Initialization circuit (OR gate), 5...
Clock generation circuit, 6, 12... Counter, 7,
8, 13...decoder.

Claims (1)

[Claims] 1. A clock generation circuit that generates a clock signal with a sufficiently shorter period than a first synchronization signal supplied from the outside, a counter that counts the clock signal, and a counter that converts the count output of the counter into data of an arbitrary number of bits. , each bit of these data is output in parallel as a timing signal, and a specific bit in the data is such that the count value of the counter is the number of the clock signals that can be generated within each cycle of the first synchronization signal. a decoder configured so that a corresponding timing signal becomes true only when the bit becomes slightly larger; and a decoder configured to supply the first synchronization signal and a timing signal corresponding to the specific bit as an initialization signal to the counter. 1. An initialization circuit, wherein a signal having a constant time width from the time when the initialization signal is generated is extracted as a second synchronization signal.