SU1104689A1 - Digital storage for processing television signals reproducer from video tape recorder - Google Patents

Abstract

DIGITAL STORAGE DEVICE FOR PROCESSING TELEVISION signals reproduced from a VCR, comprising series-connected two unit memory An information input of the first of which is a first input device for recording the address input connected to the output of the first record write address counter, the clock input is combined with the clock .zapisi the input of the first write address counter, and the read address input is connected to the read output of the first read address counter, the read clock input of the combination En with the clock input of the first read address counter, with the clock input of the second write address counter and with the write input of the second memory block, whose address input is connected to the output of the first key, the first information input of which is connected to the output of the second write address counter, and the second the information input is about the output of the second read address counter, the clock input of which is combined with the clock input input of the second memory block, as well as the sync selector whose input is the second input of devices a, the clock output is connected to the input of the first clock pulse generator j, the first control output to the control input of the first horizontal sync pulse generator, a synchronous generator, the first control output of which is connected to the second input of the horizontal sync pulse generator, the second control output from the control input of the first key , a clock output - with the input of the second clock pulse generator, the output of which is connected to the clock inputs of the first and second horizontal sync pulse formers, o t and a nd o f e that. in order to extend the functionality by ensuring the processing of digital television. signal at varying speed of the input digital stream, appearing at non-nominal speeds 9 - 00 of tape movement in playback modes from a video recorder, the first, second and third gating pulse shapers, the first, second and third shapers of the beginning counting sync pulses, horizontal sync pulse counter, the first and second KajEtrpv sync pullers, the second, third and fourth keys and the third horizontal sync pulse maker, the information input of the first formate l gating pulse connected to the information output

Description

the first counter of the write address, the control input to the output of the first driver of the start of counting of the lower-case synchronous signals, and the output to the control input of the second key, the output of which is connected to the clock input of the first memory block, and the clock input is combined with the clock inputs of the first driver start counting lowercase sync pulses and the third horizontal sync pulse generator and is connected to the output of the first clock generator, the first control output of the sync selector is connected to the control input of the third the horizontal lower pulse sync generator, the output of which is connected to the setup inputs of the first horizontal synch pulse count generator and the first write address counter, and the second control output of the sync selector is connected to the input of the first sync pulse generator, and the second pulse generator has been configured for the sync pulse for the sync pulse generator. the read address, the control input to the output of the second driver of the start of counting of the horizontal sync pulses, and the output to the control input of the third key, the output of which is connected to the read input of the first memory block, and the clock input is combined with the clock inputs of the first and second HR sync drivers, with the clock input of the second shaper of the counting pulse of the horizontal sync pulses and connected to the output of the second clock pulse, the output of the first horizontal sync pulse generator is connected to the setup inputs of the second horizontal pulse generator of the lower sync pulse count and the first address counter with In this case, the output of the second horizontal sync pulse generator is connected to the setup inputs of the third initializer of the horizontal sync pulse count and the horizontal sync pulse counter, the information output of which is connected to the information input of the third gating pulse generator, the control input of which is connected to the third output of the start drawing card. to the control input of the fourth key, the clock input of the fourth key is combined with the clock input of the third photo The universalizer started counting the horizontal sync pulses and is connected to the output of the second clock clock, and the output is connected to the clock input of the horizontal sync pulse counter and to the read clock input of the second memory block, and the third control output of the sync generator is connected to the input of the second sync pulse generator that was connected to the second sync pulse generator input. connected to the installation input of the second read address counter, the output of the first HR sync pulse generator is connected to the installation input of the second with etchika write address.

The invention relates to radio engineering and can be used in digital devices for processing a reproduced television signal, and in particular in digital time distortion correctors.

A digital storage device for processing television signals reproduced from a video recorder, containing vi groups of digital shift registers, m digital registers each, whose inputs through the first selector are connected to the first input of the device, the outputs are connected to the input of the second selector, the output of which is output devices, and clock inputs with the output of the third and fourth selectors, the clock inputs of which are connected respectively via the first clock generator and the sync selector with the second input of the device and through the second clock generator with the synchrogenerator, and the control inputs of the selector with the corresponding outputs of the register switch, the inputs of which are connected to the control outputs of the sync selector and the synchro generator 1. The disadvantage of the device is its information redundancy exceeding that required for the specified range correction of temporal; distortion. Aligning the speed of the digital stream with the speed of the microcircuits — the shift registers brings its own design difficulties. In addition, a significant drawback of the device is the low reliability due to the sequential nature of the construction. The closest to the proposed is a digital storage device for processing television signals reproduced from a video recorder containing serially connected first memory block, the information input of which is the first input of the device , the second memory block, the output of which is the output of the device, the write address of the first memory block is connected to the write output of the first address counter, read address input — with the read output of the first read address counter, the write clock input and the clock input of the write address counter through the first clock pulse generator and sync selector — with the second input of the device, the read clock input and clock inputs of the second memory block, the first read address counter of which and clock inputs of the first gating pulse shaper, second write and read address counters, first and second horizontal sync pulse shapers, h the second clock generator is cut with a synchronizing generator; the address input of the second memory block is connected via a switch to the outputs of the second write and read address counters, the control inputs of which are connected respectively through the first horizontal sync pulse generator to the control input of the sync selector and through the second horizontal synter generator pulse from the first control output of the clock generator, while the second control output of the clock generator is connected to the control input of the key, and the first counter The write and read addresses are interconnected by zj. A disadvantage of the known device is that it is not designed to correct significant time errors that occur during non-nominal motion speeds of a video tape (in freeze, accelerated and slow motion modes in forward and reverse directions x). The purpose of the invention is the expansion of functionality through. ensuring the processing of a digital television signal with a varying speed of the input digital stream, which occurs at non-nominal speeds of tape movement in playback modes from a video recorder. To achieve this goal, a digital storage device for processing television signals reproduced from a VCR, containing two memory units connected in series, the information input of the first of which is the first input of the device, the write address input is connected to the write output of the first recording address counter, clock input the record is integrated with the clock input of the first write address counter, and the read address input is connected to the output of the first read address counter, the beat The new read input is combined with the clock input of the first read address counter, with the clock input of the second write address counter and with the clock input of the second memory block whose address input is connected to the output of the first key. The first information input is connected to the output of the second write address counter, and the second information input to the output of the second read address counter, the clock input of which is combined with the read input of the second memory block, as well as the sync selector, the input of which is the second input of the device, the clock output is connected to the input of the first clock pulse generator, the first pack. the equal output to the control input of the first horizontal sync pulse generator, the synchro generator, the first control output of which is connected to the input of the second horizontal sync pulse generator, the second control output from the control input of the first key, and the clock output to the input of the second key generator clock pulses, the output of which is connected to the clock inputs of the first and second horizontal sync pulse shapers, the first, second and third gating pulse shapers, the first second and the third shaper start counting lowercase sync pulses, counting lowercase sync pulses, first and second framers of personnel sync pulses the second and third keys and the third shaper horizontal sync pulses, while the information input of the first gate strobe pulse connected to the information output of the first count of the address pulse, connected to the information output of the first address gate of the device, connected to the information output of the first address gate of the strobe pulse, connected to the information output of the first gate address pulse generator connected to the information output of the first gate address pulse generator, connected to the information output of the first gate address pulse generator - to the output of the first driver of the start of counting of the lower-case sync pulses, and the output, to the control input of the second key 5 whose output is connected to the cycles The m input is the recording of the first memory block, and the clock input is combined with the clock inputs of the first shaper started counting the horizontal sync pulses and the third shaper of the horizontal sync pulses and connected to the output of the first shaper of the clock pulses. The first control output of the sync selector is connected to the control input of the third shaper. horizontal sync pulses, the output of which is connected to the setup inputs of the first driver for counting the horizontal sync pulses and the first counter of the write address, the second controller The main output of the sync selector is connected to the input of the first HR sync pulse generator, the information input of the second gate generator is connected to the information output of the first read address counter, the control input is connected to the output of the second horizontal count generator of the sync pulse, and the jmpa-sync pulse output connector to the output of the horizontal sync pulses, and the jmpa-sync driver pin output to the output of the horizontal sync pulse, and the jmpa-sync driver output to the output of the horizontal sync pulse, and the jmpa-sync driver output to the output of the horizontal sync pulses, and the jmpa-sync driver output to the output of the horizontal sync pulses keys, the output of which is connected to the clock input of the readout of the first memory block, and the clock input is combined with the clock inputs of the first and second personnel syn Pulses, with a clock input of the second shaper of the start of counting the lowercase sync pulses and connected to the output of the second shaper of clock pulses, the output of the first shaper of the lowercase sync pulses is connected to the setup inputs of the second shaper of the beginning of the counting of lowercase sync pulses and the first read address counter, the output of the shunt of the synchromesh pulse, the output of the synchromes of the synchromesh pulse sync pulses, the output of the second shunt of the synchromesh pulse sync pulses the third shaper of the start of counting of lowercase sync pulses and the counter of lowercase sync pulses, inform The output of which is connected to the information input of the third gating pulse shaper, the control input of which is connected to the output of the third shaper of the start of counting of horizontal sync pulses, and the output to the control input of the fourth key, the t-th input of the fourth key is combined with the clock input of the third shaper start counting lowercase sync pulses and is connected to the output of the second pulse clock pulse generator, and the output is connected to the clock input of the horizontal sync pulse counter and to the clock course of reading the second storage unit, wherein the third control output connected to the clock input of the second vertical sync shaper whose output is connected to the input of the second mounting read address counter and the output of the first vertical sync shaper is connected to the mounting write address input of the second counter. The drawing shows the electrical circuitry of a digital storage device for processing television signals reproduced from a VCR. A digital storage device for processing television signals reproduced from a video recorder contains the first memory block 1, the information input of which has a digital signal from the first input of the device, the write address input and at the same time the first gate pulse 2 from the first recording address counter 3, to the address input of the readout and at the same time to the second form of the Ipoprovider 4 of the gating pulse from the first counter of the 5 readout addresses, to the clock input of the first block 1 of the memory and at the same time and the clock input of the first counter 3 write addresses is from the second key 6, to the read clock input of the first memory block 1 and simultaneously to the clock input of the first counter of the 5 read addresses, as well as to the clock input input of the second memory block 7 and clock input of the second counter 8 write addresses - from the third key 9, the first driver 10 for counting the lowercase sync pulses, to the setup input of which and simultaneously to the setup input of the first counter of the 3 write addresses a signal is sent from the third imager 11 lowering sync pulses , to the clock input and simultaneously to the clock inputs of the second key 6 and the driver of the 11 horizontal sync pulses - from the first driver of the 12 clock pulses, and from the output of the first counter 3 write addresses through the first driver 2. of the strobe pulse to the control input of the second key 6, a sync selector 13, the input of which is the second input of the device, the clock output is connected to the inputs of the first shaper 12 clock pulses, the first control output is connected to the inputs of the first and third shaper 1A and 11 horizontal sync pulses and the second control output is connected to the inputs of the first shaper of 15 frame sync pulses and the second shaper 16 of the counting start of the lowercase sync pulses, at the installation input of which and simultaneously at the set input of the first counter 5 read address is fed from the output of the first shaper of 14 horizontal clock pulses to the clock input and at the same time the clock inputs of the third key 9, the first shapers 14 and 15 lowercase and frame sync pulses, the second shaper 17 frame sync pulses, the second shaper 18 third sync pulse 19, the start of counting the horizontal sync pulses and the fourth key 20 - from the output of the second generator of 21 clock pulses, and from the output of the first counter 5 of the read address, the signal is removed through

the gate pulse generator 4 to the control input of the third key 9, the third gate pulse generator 22, to the information input of which a signal is output from the counter of 23 horizontal sync pulses, to the control input from the third driver. 19 of the start of counting of the horizontal sync pulses, and from the output is taken to the control input of the fourth key 20, the synchronous generator 24, from the clock output of which the signal is fed to the input of the second driver 21 takti5 pulses, from the first control output through the second driver 18 horizontal sync pulses to the setting the inputs of the third shaper 19 start counting lowercase

0 sync pulses and a 23-line sync pulse counter, from the second control input - to the control input of the first key 25, from the third control input - to the input of the second driver 17 frame sync pulses, second memory block 7, to the information input of which a digital signal was fed from the first memory block 1, to the address input - from the output of the first key 25, to the two information inputs of which signals from the outputs of the second counters 8 and 26 of the write and read addresses are sent, to the clock input of the readout and one 5 times to the clock inputs of the sc tchika 23 horizontal sync pulses and a second counter 26, a read address - the fourth key output 20 and is removed from the output to the output device, the installation on

0 the input of the second counter 8 addresses of the recording signal is fed from the output of the first shaper 15 frame sync pulses, and the installation input of the second counter 26 of the read address 5 from the output of the second shaper 17 frame sync pulses.

The device works as follows.

in a way.

The television signal reproduced at a certain speed of the video tape in the form of a digital molasses parallelized into m channels enters the input of the first memory block 1, which decides the duration of the reproduced active line up to its nominal value due to the distortion of the time interval of quenching while maintaining the total duration of the reproduced tv line. In this case, in order for the active part of the active line H, the active line H, to be reproduced, the strobe recording pulse T is formed. This formation is carried out by the first shaper pulse generator (SI) 2, and this is done so that the reference time 0c coincides with the front front of the reproduced horizontal sync pulse. To do this, the control input of the first shaper of the beginning of the counting of lowercase sync pulses (FID) from the third shaper 11 of the FID comes preliminarily phased with a reproducible clock sequence of pulses of the reproducible horizontal pulse, thus opening an auxiliary counter located in the first shaper of 10 The start of the FID, which counts the number of reproducible clock pulses, ranging from the time O to the beginning of the active line. When the NSH-1 is reached at that moment, the first SI driver 10 starts to generate a pulse that triggers the first SI driver 2, which opens the second key 6, which allows you to record the first and subsequent bits that carry information about the active playable line to the first block 1 memory. The first counter is 3 write addresses, the preset of which is available at the moment He is during the blocking of the recording process, counts the number of reproducible clock pulses necessary to record the active line. If the active line information is carried by MK samples following the frequency ij in each of the W parallel channels, the duration of the recorded active line being recorded is equal. When the last bit of the active line arrives in the first memory block 1, the decoder located in the first driver. 2 SI, after receiving the corresponding code combination of 1 SCHI from the first counter of 3 write addresses 9, generates a pulse, terminating the action of the write write pulse. The second key 6 is closed, which makes it impossible to write to the first memory block 1 before the start of the next active line of the television signal. A read strobe from the first memory block 1, generated similarly to a write strobe pulse, is 0c also associated with the leading edge of the reproduced row pulse, however, the readout of the recorded information occurs at the reference clock frequency i corresponding to the nominal speed of the tape. As a result, the duration of the active line being read is equal to the value written to and differs by 1 JL ,,, 4i i. which in turn affects the duration of the read gating pulse from the first memory block 1 & T Hj. - H (iQ. At the same time, the reproduced line pulse is phased into the first driver 14 FID, the reference clock sequence of impulses received from the second generator of 21 clocks, and the auxiliary counter located in the second generator 16 of the start of the FID account to perform an average read start delay, in addition to the number of reference clock pulses, placed from the moment 0ts to the beginning of the active line, counts the number of pulses, adequate to half the information capacity of the first block of 1 memory in each of m parallel channels. This solution provides for the correction of the active line duration when the reproducible clock frequency deviates to both sides from the nominal value. The length of the distorted parts of the lines is corrected in the second block 7 of the band which, due to its large information capacity, allows to restore the nominal SH of the durations in the reproduced TV signal. The order of alternation of the processes of recording and sharing is controlled by the first key 25 according to the commands received from the sync generator 24. Since, in accordance with the accepted processing algorithm, the read gating pulses from the first memory block 1 and the write gating pulses to the second memory block 2 must match in all parameters, the read gating pulse generated in the second CI shaper 4 opening the third key 9, thereby allowing the readout of the information read from the first memory block 1 to the second memory block 7, the information is recorded using the second counter 8 of the write address, which has a sufficient size for referring to any cell of the second memory unit 7. The preset of the second counter of the address of the record is produced by frames with a reproducible pulse, which selects one of the line reproduced pulses as a quality, located in the interval of the frame damping H pulse. After phasing in the first shaper 15 frame sync pulses (XI) reference clock sequence received from the second shaper 21 clock pulses, it arrives at the set input of the second counter 8 write addresses, and this is done, as before, at the moment of time He (in the period blocking the recording in the second memory block). The information recorded in the second memory block 7 is read at the same recording as the reference clock frequency ip, however, the 0c read gate pulse from the second memory block 7 binds to the leading edges of the reference horizontal pulses following the HQ period. Therefore, the active lines are read out from the second memory block 7 without changing the time scale, and the lengths of the pauses are aligned to the nominal values To. The formation of a read gating pulse in the third SI generator 22 begins in that the control input of the third driver 19 for counting the FID from the second generator 18 FID enters a pre-phased horizontal lower pulse, which opens the third imaging unit 19 is the start of the FID account, which counts the number of reference clock pulses from the time Oj to the beginning of the active line. When this point is reached in the third start driver 19, the FID account produces a pulse that triggers the third SI driver 22, which opens the fourth key 20, which allows reading the first and subsequent bits carrying information about the active line from the second memory block 7. The second counter 26 of the address has a number of states, providing access to any cell of the second block 7. memory. However, this number significantly (for example, ten or more times) exceeds the number of bits in the active string. Therefore, to eliminate ambiguity in determining the end of the read gating pulse, the device uses a 23-line sync counter, the number of bits of which is matched with the number of bits in the active line. The presetting of the FID counter 23 is performed at time 0 (during the blocking period from the second memory block 7) with a phased reference clock sequence with a reference horizontal pulse. When reading information from the second memory block 7, the FID counter 23 counts the number of reference clock pulses needed to read the active line. The decoder, located in the third SI generator 22, on receipt of a code combination corresponding to the last bit of the active line from the 23 SRI counter, generates a pulse that stops the effect of the read gating pulse. The fourth key 20 is closed, which does not permit reading from the second memory block 7 until it is time to read the first and subsequent bits of the next active row. The preset of the second read address counter 26 is made by a frame reference pulse, which is selected from one of the line reference pulses (the same number as the line reproducing pulse, chosen as the frame replay pulse), which is within the frame dimming pulse. After phasing in the second 17 XSI driver, the reference clock pulse sequence follows from the second driver 21 clock. impulses, it arrives in the period. The possibility of correcting significant temporal distortions contained in a television signal reproduced under non-nominal modes of operation of a VCR is determined by the presence of blanking intervals in the signal that do not need to be processed in memory blocks (i.e. their recording and reading), since they can be uniquely regenerated in the future. At the same time, not only is saving;

HftofTc 914 locks the read process from the second memory block 7 to the installation input of the second read address counter 26. Thus, the proposed device provides processing of a reproduced television signal, aimed at correcting temporal distortions caused by changes in the speed of movement of a video tape with non-nominal modes of operation of a video recorder, and is implemented in accordance with the following algorithm: about 15% of the information storage capacity of memory devices, but also due to the time reserve formed, the time scale of the reproduced television signal is corrected. The hardware selection of the so-called active lines, during the operation of which the signal of the television image itself is transmitted, is carried out with the help of specially formed gates.

Claims (1)

DIGITAL REMEMBERING DEVICE FOR PROCESSING TELEVISION PLAYS PLAYABLE FROM VIDEO RECORDER, containing two memory blocks connected in series, the information input of the first of which is the first input of the device, the address input of the record is connected to the record output from the first record the input of the first counter of write addresses, and the address input of the read is connected to the read output of the first counter of read addresses, the clock input of the read is combined with that the input of the first counter of read addresses, with the clock input of the second counter of write addresses and with the clock input of the second memory block, the address input of which is connected to the output of the first key, the first information input of which is connected to the output of the second counter of write addresses, and the second information input - about the output of the second counter of read addresses, the clock input of which is combined with the clock input of the read of the second memory block, as well as the clock selector, whose input is the second input of the device, the clock in the stroke is connected to the input of the first driver of clock pulses, the first control output to the control input of the first driver of lowercase clocks, a clock, the first control output of which is connected to the input of the second driver of lowercase clocks, the second control output to the control input of the first key, and the clock output to the input the second clock shaper, the output of which is connected to the clock inputs of the first and second line shaper pulses, about τη and more. what. in order to expand functionality by providing digital television processing. signal at a varying input digital stream velocity occurring at non-nominal tape speeds in the playback modes from the VCR, the first, second · and third gate drivers are introduced, the first, second and third drivers of the start of the counter of horizontal sync pulses, the counter of horizontal sync pulses, the first and second shaper of frame sync pulses, the second, third and fourth keys and the third shaper of horizontal sync pulses, 'at that ₍ the information input of the first shaper For gating impulse: connected to the information output of the first counter of recording addresses, the control input to the output of the first driver of the beginning of the account of lowercase clock pulses, and the output to the control input of the second key, the output of which is connected to the clock input of the recording of the first memory block, and the clock input is combined with the clock inputs of the first driver the beginning of the counting of the horizontal sync pulses and the third shaper of the horizontal sync pulses and connected to the output of the first clock shaper, the first control output of the clock selector it is connected to the control input of the third horizontal sync pulse generator, the output of which is connected to the installation inputs of the first horizontal sync pulse start generator and the first recording address counter, and the second sync selector control output is connected to the input, the first frame sync driver, the information input of the second gating pulse generator information output of the first counter of read addresses, the control input is to the output of the second former full-time clock, and the output is to the control input of the third key, the output of which is connected to the clock input, read the first memory block, and the clock input is combined with the clock inputs of the first and second shaper of the clock pulses, with the clock input of the second shaper of the beginning of the counting of the lowercase pulses and connected to the output of the second driver of clock pulses, the output of the first driver of lowercase clock is connected to the installation inputs of the second driver of the beginning of the count! horizontal clock and the first counter of read addresses, the output of the second driver of the horizontal clock is connected to the installation inputs of the third driver for counting the horizontal clock and the counter of the horizontal clock, the information output of which is connected to the information input of the third driver of the strobe pulse, the control input of which is connected to the output of the third driver of the start of the account horizontal sync pulses, and the output is to the control input of the fourth key, the clock input is four of the second key is combined with the clock input of the third driver of the beginning of counting of the horizontal clock pulses and connected to the output of the second driver of the clock pulses, and the output is connected to the clock input of the counter of the horizontal clocks and to the clock input of the reading of the second memory block, and the third control output of the clock is connected to the input of the second driver frame sync pulses, the output of which is connected to the installation input of the second counter of read addresses, and the output of the first frame sync driver Pulse input is connected to the mounting of the second write address counter. —------- f—— “. 12