JP2661110B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described in the following order. A Industrial Field of Use B Outline of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving the Problems F Function G Embodiment H Effects of the Invention A [Field of Industrial Use] The present invention relates to a video signal processing device that processes a composite color video signal using a digital memory. B [Summary of the Invention] In the present invention, digital processing of a color video signal is performed using a memory, and writing of the digital video signal to the memory is performed for each sample of a subcarrier frequency unit and one horizontal The writing address is controlled in synchronization with the horizontal synchronizing signal for each line, and a V-end marker is written at the end position of one field. In particular, one image is connected with video signals from a plurality of frames. When applied in the case of forming together, the continuity of the subcarriers is maintained even at the joint, and the occurrence of skew can be prevented. C (Prior Art) When high-speed reproduction is performed by a rotary head type helical scan VTR, the rotary head scans over a plurality of recording tracks. In this case, in the case of a two-head type VTR using a so-called azimuth recording method, a so-called noise bar is generated on a playback screen because a playback signal cannot be obtained from tracks having different azimuth angles. In particular, when a guard band is formed between adjacent tracks in the short play mode in which the recording time is short, the noise bar becomes thick and becomes unsightly. Therefore, conventionally, two auxiliary heads were separately provided in addition to the two heads for recording and reproduction, and a reproduction screen with few noise bars was obtained by using the two heads. However, this has increased the number of heads. At the same time, the number of signal processing systems increases accordingly, resulting in an increase in cost. For this reason, a method has been considered in which the number of rotary heads is not increased, and the noise bar is made as thin as possible by signal processing using a digital memory so as to be inconspicuous. This is because, for example, when a tape is fed at an even-numbered speed during normal reproduction, the scanning phase of the plus azimuth head and the minus azimuth head is shifted with respect to the recording track on the tape, and noise bars are generated for each other. In this method, two fields of video signals from two heads are alternately spliced by using signals at image positions that are not present, thereby forming an image for one field. Fig. 5 shows an example of high-frequency output during high-speed reproduction of a plus azimuth head HA and a minus azimuth head HB. As shown in the figure, the high-frequency output has an abacus ball-shaped envelope. Will generate a noise bar where is zero. For this reason, head HA 1
The reproduced image obtained during the field scanning period is shown in FIG.
A noise bar appears at the position shown in
In the reproduction screen during the scanning period of one field of HB, a noise bar is generated at a position as shown in FIG. 6B.
Therefore, the images of the portions without noise bars on the screens of FIGS. 6A and 6B are taken into the memory and joined alternately as shown in FIG. 6C, thereby forming an image in which the noise bars are thinned and inconspicuous. be able to. As described above, when two images are spliced to form one screen, continuity and skew of subcarriers at seams of the images become problems. That is, if the continuity of the subcarriers is lost, the image may not be colored depending on the television receiver. In addition, when skew occurs, image curving occurs on the screen. Therefore, it is important for signal processing to prevent the continuity of the subcarriers and the occurrence of skew.However, in the case of a composite color video signal, since the horizontal synchronization signal is not synchronized with the burst signal, the subcarriers are continuous. When the screens are connected in such a manner, the deviation of the horizontal synchronization signal cannot be corrected, and skew occurs. Conversely, if the skew is prevented from occurring by adjusting the horizontal synchronization signal, the subcarriers may be discontinuous and the color may not be cast. Therefore, when a color video signal is written to a memory as a digital signal, a method for eliminating the above problem as a component signal of a luminance signal Y, red and blue color difference signals RY and BY instead of a composite signal is proposed. (Television Technology, January 1987, P35-P42). FIG. 7 shows an example of this component type signal processing device. A composite color video signal through an input terminal 1 is supplied to a Y / C separation circuit 2 and a luminance signal Y
And the carrier chrominance signal C. The luminance signal Y is supplied to the A / D converter 3 and converted into a digital signal. The digital signal is supplied to the serial-parallel converter 4 to be converted into parallel data and written into the memory 5. On the other hand, the carrier chrominance signal C from the Y / C separation circuit 2 is demodulated by a decoder 6 into a red chrominance signal RY and a blue chrominance signal BY, and these chrominance signals RY and BY are multiplexed. At 7, the digital signal is converted into a digital signal by an A / D converter 8, and the digital signal is written to the memory 5. Writing and reading of the memory 5 are performed by a control signal from the memory control circuit 9. Y / for writing
The luminance signal from the C separation circuit 2 is supplied to the synchronization separation circuit 10 to separate the synchronization signal. Based on the synchronization signal in the input composite color video signal, a write address signal is given to the memory 5 from the memory control circuit 9. Can be On the other hand, at the time of reading, a read address signal is formed from a subcarrier frequency signal and a synchronization signal obtained from a reference oscillator built in the memory control circuit 9, and the color difference signal data and the luminance signal data are respectively read by the read address signal. The luminance signal data is converted back to serial data by the parallel-serial conversion circuit 11, supplied to the D / A converter 12, returned to an analog luminance signal, and supplied to the adder 13. The color difference signal data is supplied to the demultiplexer 14,
The digital data of the line-sequential red color difference signal and blue color difference signal is sorted and D / A converters 15R and 15R.
B, and converted back to analog signals to obtain color difference signals RY and BY, respectively, which are supplied to the encoder 16, where they are modulated again by the 3.58 MHz subcarrier and synthesized, and the carrier chrominance signal is obtained. C is obtained from the encoder 16 and supplied to the adder 13 to be added to the luminance signal Y. The horizontal and vertical synchronizing signals are added to the adder 13 from the memory control circuit 9 in synchronization with the reading, and the adder 13 extracts a composite color video signal. In this component type signal processing device,
Since it is stored in the memory 5 as the color difference signals RY and BY, there is a feature that a color is applied wherever the image is connected. This is because the color burst signal is added later, and the subcarrier signal used at the time of modulation in the encoder 16 is used as it is as the color burst signal. In addition, since the horizontal and vertical synchronizing signals are added later, no skew occurs due to the deviation of the horizontal synchronizing signal wherever the image is continued. Therefore, this component system is a signal processing system suitable for so-called memory interpolation, in which a plurality of screens at the time of high-speed reproduction described above are joined. However, as is clear from FIG. 7, this signal processing method requires a decoder and an encoder for color signal processing, which increases the number of circuits and leads to an increase in cost. In addition, the signal passes through the decoder and the encoder, so that the signal is deteriorated, which leads to the deterioration of the image quality. Therefore, particularly when a low-cost device is intended, a method that can process a composite signal as it is is more effective than the component system. Conventionally, as a method for performing signal processing with the composite signal as it is, a serial method, an H-reset method (H-synchronous method), and the like are known. In the serial system, as shown in FIG. 8, a digital color video signal is written into a memory in a flowing manner.
The continuity of the horizontal synchronization signal and the continuity of the burst signal can be maintained. The H-reset method uses a memory in which addresses are defined in a horizontal direction and a vertical direction as a memory for one field or one frame. This is a method of writing data corresponding to one row (see FIG. 9). By doing so, the write position of the head data of each line is aligned in the vertical direction as shown in the figure. In this direction, reading is performed for a fixed length in the horizontal direction indicated by * A in FIG. In this case, if the continuity of the subcarriers is impaired in the case of a composite signal, the color will not be applied as described above. Therefore, data is written in the unit of the subcarrier frequency and read out in the unit of the subcarrier frequency. To do. For example, if the sub-carrier frequency and f _SC, when sampled at a frequency of 3f _SC is such and writes three sample data in the field memory, for example of the three as a unit. In this way, since writing and reading are performed in subcarrier frequency units, that is, in one cycle of subcarriers, continuity of subcarriers can always be guaranteed (see Japanese Patent Publication No. 61-188901). D [Problems to be Solved by the Invention] In the serial method, since the data is written in a cascade manner, the position of the horizontal line in one field cannot be determined. For this reason, it cannot be used for memory interpolation processing for obtaining a playback screen at the time of high-speed playback described at the beginning. The H-reset method can always maintain the continuity of subcarriers. However, as shown in FIG. 9, for example, in the case of a VTR reproduction signal, the signal contains jitter, and A time axis error occurs in the signal of the line, and the last position of the signal of one line is not constant. Therefore, if reading is performed to the position * A with a fixed clock, the signal will be excessive or insufficient, and the continuity at the time of writing will be impaired. This will result in skew. Therefore, in order to solve such a problem, the present applicant first inserts an H end code at the end point of one horizontal line,
It has been proposed that when this H end code is detected, the data in the memory is read out at a constant synchronization by incrementing the vertical readout address of the memory (Japanese Patent Application No. 62-100761).
issue). According to the invention of this method, the data in the field memory is updated in the vertical direction after the last data of the horizontal line is read even if the number of video data of one horizontal line is different due to variable speed reproduction or the like, By reading at the cycle of the horizontal synchronization signal, it is possible to prevent the occurrence of skew and maintain the continuity of subcarriers. However, when the VTR is reproduced at variable speeds, the number of lines forming one field changes, so that there is a problem that the end point of the one-field memory, that is, where the end of the vertical period is located on the memory is not known. I do. Therefore, a method of inputting a V reset signal to the memory when the H synchronization signal is counted from the start of one field to reach a predetermined number, or a method of accurately monitoring the tape feed during variable speed reproduction and performing one vertical period It is possible to calculate the horizontal line accurately in advance and reset it.
These methods have a problem that a circuit becomes complicated. E [Means for Solving the Problems] In the present invention, when writing in synchronization with the horizontal synchronizing signal as in the above-described H-reset method, an H end marker indicating the end position of each horizontal line is stored in the memory. At the same time as writing, the end point of each field is detected by a switching pulse of the rotating drum or the like, and a V-end marker is further written at the end of the last horizontal line. As a digital signal, data in units of subcarrier frequency is written as one unit. F [Operation] Since digital data is written and read in units of subcarrier frequency, continuity of subcarriers can always be maintained. In the horizontal direction and the vertical direction of the field memory, the vertical address at the time of reading is controlled based on the H end marker and the V end marker, and the address can be reset at the end point of the field. Further, at the time of variable speed reproduction, since the V end marker is recorded by the switching pulse of the rotating drum, the occurrence of skew is prevented and the detection of one field period can be easily performed. G [Embodiment] FIG. 1 is a block diagram showing an example of a video signal processing apparatus according to the present invention. In this example, when digitizing a composite color video signal, one sample is set to, for example, 6 bits. Therefore, when A / D conversion is performed, there are 64 levels from 0 to 63, but 1 to 63 are used as video signal data, and the “0” level is used as an H or V end code. (Note that the maximum value [111111] of the digital conversion value may be used as the H or V end code, but the following describes an embodiment in which [000000] is used as the end code.) The digital level of the output of

In the case of [0], the data is changed to [000001] (hereinafter simply referred to as [1]). In FIG. 1, reference numeral 21 denotes an input terminal of a composite color video signal, through which a composite color video signal is supplied to an A / D converter 22. For example, a sync tip level is set to [1] and a white peak level is sampled as a maximum value. Be transformed into 23 is a burst detection circuit for generating a clock signal of subcarrier frequency f _SC, a clock by inputting the output to the timing control circuit 40 is tripled
A frequency of 3f _SC is formed, and this is supplied to the A / D converter 22 as a sampling clock. Numeral 24 denotes a sync separation circuit. The horizontal and vertical sync signals extracted by this circuit are also input to the timing control circuit 40 to control reading and writing of a field memory 28 described later. The digital video signal from A / D converter 22 is

[0] Supplied to the prohibition circuit 25. And the digital level from A / D converter 22

The sample data of [0] is converted into data of level [1]. This prohibition circuit
The digital signal from 25 is converted to a serial-parallel converter 26
And is converted into parallel data in subcarrier frequency units, that is, every three samples in this example, and is supplied to the memory 28 (A, B, C) via the switch circuit 27. In this example, the memory 28 (A, B, C) is of a type that can perform writing and reading at the same time. For example, the memory 28 (A, B, C) is equal to the memory composed of three field memories 28A, 28B, and 28C. And addresses are assigned in the vertical direction. The digital data of three samples in parallel from the serial-parallel conversion circuit 26 is passed through a switch circuit 27 to the three memories 28A and 28 of the memory 28.
One sample is simultaneously written to the same address of B and 28C. Reference numerals 29A and 29B denote H end code generation circuits and V end code generation circuits which output data indicating the end of one horizontal line of video signal data written to the memory 28 and data indicating the end point of one field. There is output from the H-end code generation circuit 29A, H end code via a switch S _a switched by the horizontal synchronizing signal output from the timing control circuit 40, is inputted to the field memory 28A. Also, the V output from the V end code generation circuit 29B
End code is to be supplied via the switch S _B switched by a signal synchronized with the switching pulse SWP of the drum, as described below, together with the image data, for example in the field memory 28B. In this embodiment, the H end code and the V end code are the same code.

[0] is used. Gate circuit for outputting a signal for particular driving the switch S _B to the variable speed reproducing mode is 31, 32A, 32B are field memory 28
(A, B, C) indicates a recording address counter, in particular, 32A indicates a horizontal address counter, and 32B indicates a vertical address counter. Similarly, 33A and 33B indicate a horizontal address counter and a vertical address counter at the time of reading. The horizontal address counters 32A and 33A are supplied with the above-described color subcarrier frequency f _SC as a clock signal, increment the horizontal address of the field memory, and are reset by an H end code. Also, the vertical address counter 32
B and 33B are composed of counters for counting the horizontal synchronization signal,
The vertical address of the field memory is incremented, and the V end marker is reset. The video data read from the field memory 28 (A, B, C) is converted into a serial signal via an SP converter 34 and is input to a D / A converter 36 via a hold circuit 35.
It is converted to an analog signal. Reference numeral 50 denotes an end code detection circuit for detecting H end code and V end code included in video data read from the field memory 28 (A, B, C) as described later. H or V from detection circuit 50
When an end code is detected, the value is held by the hold circuit 35.
To prevent the H or V end code from being output within the scanning period. When the H end code is detected, the horizontal address counter 33A for reading is reset, and when the V end code is detected, the vertical address counter 33B is reset. The embodiment of the video signal processing apparatus according to the present invention is configured as described above, and the input composite video signal is sampled at a sample frequency of 3f _SC , and as shown in FIG. The horizontal synchronization signal is stored as a vertical address while being sequentially distributed to the memories 28A, 28B, 28C. Transverse horizontal address counter 32A of each field memory 28 (A, B, C) is started on the basis of the horizontal synchronizing signal, in particular, Suitchii S _A are switched simultaneously the horizontal synchronizing signal arrives in the field memory 28A Output from the H end code generation circuit 29A.

[0] level H end code is added to the end of the video data. this

Since the [0] level signal is a code that is not output from the prohibition circuit 25, if this code is detected from horizontal line data in the field memory 28A at the time of reading, it can be set as the end point of one horizontal line. Then, at the time of normal reproduction and the vertical synchronizing signal V is input to the switch circuit 37 is supplied as a control signal for the switch S _B from a contact point, thereby switching the switch S _B, V end code generating circuit at this moment Output from 29B

The [0] level V end code is output after being replaced with video data.
Is added as the last data of the last horizontal line data. Therefore, when the V end code is read from the field memory 28B, the end point of one field can be detected, and when the vertical counter 33A specifying the vertical address is reset by the output of the end code detection circuit 50, A state where the data of the next field screen can be taken in can be set. During normal reproduction, as described above, one field of image data is stored in the field memory 28 (A, B, C). Can be output. Incidentally, in the case of the video signal processing apparatus of the present invention, in particular, since the V end mark indicating the end of one field is recorded together with the image data in the field memory in synchronization with the switching pulse SWP, for example, slow reproduction or Even if the number of horizontal lines changes during high-speed playback, 1
Since the end position of the field can be detected by the V end code in the read video data, there is no need to manage the number of horizontal lines in the field in the VTR, and the continuity of the video signal is ensured. Can be. Hereinafter, this point will be described with reference to the waveform diagram of FIG. At the time of cue review or slow playback, as shown in FIG. 3, the envelope waveform A of the playback RF signal disappears when traversing a track, and the number of horizontal lines N in one field period is reduced due to a change in the scanning track trajectory of the head. It changes within a range of several percent. For this reason, at the time of variable speed reproduction, depending on the tape speed, a part of the horizontal synchronizing signal H and the vertical synchronizing signal V is missing in one field as shown in the reproduction synchronizing signal waveform D. Control circuit
Since the continuous synchronization signal waveform E can be obtained by the PLL circuit in 40, the vertical address of the field memory 28 can be incremented in order by the synchronization signal waveform E, and the H end code is also set to each line data. Can be added at the end. The video data B is stored at a predetermined position in the field memory during periods T ₁ , T _2, ... Where a high-quality reproduced RF signal is obtained. Next, the V end code indicating the end of one field is represented by b of the mode changeover switch 37 which is switched during variable speed reproduction.
V switching the switch S _B by a signal obtained from the contact point
As described above, the V code is supplied from the end code generation circuit 29B to the field memory 28B. This switching signal is generated by the horizontal synchronizing signal (H ₁ ) (F waveform) input first after the gate circuit is opened at the changing point of the waveform C of the switching pulse SWP of the rotating drum input to the gate generation circuit 31. It is formed. That is, when the switching pulse SWP is, for example, detects the half-rotation of the drum, switching the switch S _B only the horizontal synchronizing signal input immediately thereafter (H ₁₎ via the mode switch 37 from the gate circuit 31, V The V-end code output from the end code generation circuit 29B is added to video data and output. Then, the gate circuit 31 is reset again, and closes the gate until the next change point of the switching pulse SWP. On the reproducing side, every time the H end code is detected, the horizontal counter 33A indicating the horizontal address is reset, and the vertical address counter indicating the vertical address is incremented by one, or the V end code is read out. When this is done, the vertical address counter 33B is reset and controlled to return to the initial address of one field. Therefore, in the embodiment of the present invention, even at the time of variable speed reproduction, information indicating the end of one field is supplied to the field memory 28, and since this information, that is, the video data of the field memory is read by the V end code, Even when the number of horizontal lines in the memory is changing, video data can be read continuously without inputting special control data. FIG. 4 shows an example of the end code detection circuit 50. Reference numeral 51 denotes a digital comparator for comparing data with the end code ED, and reference numeral 52 denotes a signal S indicating from which field memory the read data is output. And a V / H determination circuit 53A, 53B for determining whether the end code is a V end code or an H end code, and a reset signal generation circuit 53 for forming a signal for resetting the horizontal and vertical address counters 33A, 33B.
Denotes a timing circuit for controlling the output timing of the reset signal and the hold signal. In the initial stage of variable speed reproduction, first, one field image at the reproduction speed is recorded in the field memory as a still image, and then the reproduction speed of the tape is made variable (slow or double speed). Is preferably recorded in the field memory 28 (A, B, C) and read out. Further, at the time of variable speed reproduction, the rotation speed of the drum may be slightly shifted from a specified V cycle within a range in which synchronization is achieved, and control may be performed so that the change in the length of the horizontal line is reduced. As the field memories 28 (A, B, C), three memories 28A, 28B, 28C capable of recording 6-bit video data were used. However, if a 6-bit field memory is further added, the sampling code data becomes Recording and reading processing of the video data converted into 8 bits can be performed. Although the V-end code and the H-end code are the same code, the V-end code can be formed by two or three H-end codes.

Without limitation to [0], for example, in the case of 8 bits, [1]
Data [11111111] can also be used. [Effects of the Invention] As described above, according to the video signal processing apparatus of the present invention, when the composite color video signal is stored in the digital memory and played back, the V indicating the end point of each field is used.
Since the end code can be recorded together with the video data in the field memory, in particular, when the variable-speed reproduction is performed, 1
Even when the number of horizontal lines in the field changes, the vertical position information can be detected on the memory, and the writing and writing of the field memory can be performed without supervising the tape speed and the like.
There is an effect that reading control can be simplified. The V end code has an advantage that the memory capacity does not increase by using a specific data word of the image code.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a video signal processing apparatus according to the present invention, FIG. 2 is a pattern diagram showing an arrangement of H end codes and V end codes recorded in a field memory,
FIG. 3 is a signal waveform diagram for explaining a V-end code at the time of variable speed reproduction, FIG. 4 is a circuit diagram showing an example of an end code detecting section, FIG. 5 is a reproduction RF signal waveform diagram of variable speed reproduction, FIG. FIG. 7 is an explanatory diagram showing the synthesis of a field screen, FIG. 7 is a schematic diagram of a recording / reproducing apparatus using a component video signal, and FIGS. 8 and 9 are explanatory diagrams showing a recording method of a field memory. In the figure, 22 is an A / D converter, 27 is a switch circuit, and 28 (A,
B and C) are field memories, 29A and 29B are circuits for generating H end codes and V end codes, 32A and 32B are horizontal and vertical address counters for writing, 33A and 33.
B indicates a horizontal address counter and a vertical address counter for reading, and 50 indicates an end code detection circuit.

Continuation of front page (56) References JP-A-63-266989 (JP, A) JP-A-63-31294 (JP, A) JP-A-61-189081 (JP, A) , U)

Claims (2)

(57) [Claims] An A / D conversion circuit for converting a composite color signal into a digital color video signal at a frequency that is an integral multiple of a subcarrier frequency; a memory for storing at least one field of the digital color video signal; Recording control means for sequentially writing the digital color video signal into the memory in units of the subcarrier frequency; V indicating the end of one field in synchronization with a vertical synchronization signal;
Means for writing an end mark; read control means for reading the digital signal from the memory in subcarrier frequency units; detection means for detecting the V end mark from the read digital color video signal; 1 by the V-end mark detected from
Means for updating a vertical address of a memory to be read out for each field. In the case of a variable speed reproduction signal, the V end mark is formed in synchronization with a switching pulse of a rotating drum. Processing equipment. 2. When a specific code signal indicating an output level of the A / D conversion circuit is used as the V-end marker, when the code signal appears in digital video signal data,
The video signal processing device according to claim 1, wherein the code is changed to another data.