JPH084348B2 - Signal processing method of digital signal recording / reproducing apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing method of a digital signal recording / reproducing apparatus for recording and reproducing a PAL digital video signal.

[Outline of Invention]

According to the present invention, in a recording circuit system, a PAL system digital video signal to be recorded is recorded with the same address assigned to each field signal, and is reproduced in a field memory of a reproducing circuit system. In the digital VTR signal processing method, which writes the digital video signal of the PAL system video signal according to the address and reads the PAL system video signal from the field memory, the address assigned to each field signal of the PAL system digital video signal to be recorded. By setting the start sample for the start address and line signal so that the phase of the color subcarrier for each field is the same, the image quality and color reproducibility of the playback screen are good during variable speed playback such as high-speed playback Responsiveness to etc. is good, and the memory capacity used at the time of playback is small Those were.

[Conventional technology]

In a conventional digital VTR, the recording circuit system does not record the digital composite color video signal to be recorded with the same address for each field signal.On the other hand, a memory is provided in the reproduction circuit system for reproduction. The digital composite color video signal is stored in this memory based on the address, and when the digital composite color video signal of a predetermined length signal is stored in the memory, it is read out even during variable speed reproduction. ,
It has been made possible to reproduce a composite color video signal capable of forming a substantially complete reproduction screen.

[Problems to be solved by the invention]

By the way, in a PAL color video signal, the color subcarrier has a sequence of 8 fields.
It is necessary to keep the sequence of fields. Therefore, PA
In the digital VTR for the L system, the digital composite color video signal is used as the memory of the playback circuit system from the first to the first.
In order to store every 8th field signal, a capacity of 8 fields is provided, and when 8 fields of the digital composite color video signal are stored in this memory,
I was trying to read it. However, the use of such a memory having a capacity of 8 fields not only makes the memory expensive, but also has a drawback that the response speed becomes low.

Therefore, if this memory having a capacity of one field is used, such a defect can be avoided. But,
By doing so, even if the signals of the same address in the digital composite color video signal, the phase of the color subcarrier differs depending on which of the first to eighth field signals they belong to, the color in the memory A field signal in which the phase of the subcarrier changes according to a sequence of 8 fields can hardly be stored, and thus the color reproducibility of the reproduced digital composite color video signal is deteriorated.

In view of such a point, the present invention, in the recording circuit system, the PAL system digital video signal to be recorded, the same address for each field signal, so as to record, the field memory of the reproducing circuit system, Played PAL
In the signal processing method of the digital signal recording / reproducing apparatus in which the PAL system video signal is read from the field memory while writing the system digital video signal according to the address, the image quality of the playback screen and An object of the present invention is to propose a method which has good color reproducibility, good responsiveness to moving images and the like, and which requires a small memory capacity for reproduction.

[Means for solving problems]

According to the present invention, in a recording circuit system, a PAL system digital video signal to be recorded is recorded with the same address assigned to each field signal, and is reproduced in a field memory of a reproducing circuit system. In the signal processing method of the digital signal recording / reproducing apparatus, in which the digital video signal of is written according to the address and the PAL video signal is read from the field memory, for each field signal of the PAL digital video signal to be recorded The start address of the attached address should be recorded
In the four-field sequence of the first four-field sequence and the latter four-field sequence of the 8-field sequence of the PAL digital video signal, one of the phases of the burst signal that is inverted every two lines The address of the line indicating the phase is set, and in the sequence of the other 4 fields of the sequence of 8 fields, the address of the line indicating the other phase of the phase of the burst signal that is inverted every 2 lines is set and the start is performed. The samples are shifted by a half cycle of each subcarrier so that the phase of the color subcarrier for each field of the PAL digital video signal to be recorded is the same.

[Action]

According to the present invention, the start address of the address assigned to each field signal of the PAL digital video signal to be recorded is the first half of the 8-field sequence of the PAL digital video signal to be recorded and the second half of the sequence. In one of the four field sequences of the four field sequence, the address of the line indicating one of the phases of the burst signal inverted every two lines is used as the address of the line, and the other four fields of the eight field sequence are set. In the sequence (2), the address of the line indicating the other phase of the phase of the burst signal that is inverted every two lines is used, and the start sample is shifted by the half cycle of the color subcarrier. Thus, the phase of the color subcarrier for each field of the PAL digital video signal to be recorded becomes the same.

[Embodiment] A recording circuit system and a reproducing circuit of an example of a digital VTR to which the present invention is applied will be described below with reference to FIGS. 5 and 6. First, prior to the description of the recording circuit and the reproducing circuit of FIGS. 5 and 6, the configuration of the rotary magnetic head device will be described. A rotary magnetic head for recording and a rotary magnetic head for reproduction are attached to the rotating upper drum of a tape guide drum including a fixed lower drum and a rotating upper drum at angular intervals of, for example, 120 °. Each of the recording rotary magnetic head and the reproducing rotary magnetic head is composed of a pair of closely arranged rotary magnetic heads (head chips) having different azimuths of the gaps. The magnetic tape is obliquely wound around the tape guide drum with a winding angle of 330 °, for example.

In addition, a pair of rotary magnetic heads for recording forms a pair of inclined recording tracks close to each other per 1/2 field, so that two pairs of inclined recording tracks are formed per field so that a digital video signal is recorded on a magnetic tape. Record. Then, the digital video signals of each pair of inclined recording tracks recorded in this manner can be reproduced by the pair of reproducing rotary magnetic heads.

First, the recording circuit system of the digital VTR will be described with reference to FIG. (1) is an input terminal for a PAL type analog composite color video signal (one frame is 625 lines). The analog composite color video signal from the input terminal (1) is supplied to the clamp circuit (3) and the sync separation circuit (4) via the low pass filter (2). The pedestal clamp level detection signal from the sync separation circuit (4) is supplied to the clamp circuit (3). The horizontal and vertical sync signals from the sync separation circuit (4) are supplied to the timing signal generation circuit (5). Further, the composite color video signal from the clamp circuit (3) is supplied to the A / D converter (6), and a parallel 8-bit digital composite color video signal (a part excluding the vertical blanking interval from one line is It consists of 948 samples of data) and is channel coded to 47
The shuffling circuit (7a) of each channel is divided into 2 channels to consist of 4 samples of data.
Supplied to (7b). The sampling frequency is four times the color subcarrier frequency.

Each of the shuffling circuits (7a) and (7b) has a memory for, for example, 20 to 30 lines, and the timing of signal writing to the memory is controlled by the timing signal from the timing signal generating circuit (5). To be done.
The configurations of these shuffling circuits (7a) and (7b) will be described in detail later.

The outputs from the shuffling circuits (7a) and (7b) are supplied to the time axis compression circuits (8a) and (8b), respectively. Each of these time axis compression circuits (8a) and (8b) has a memory with a capacity of, for example, 1/6 field, and is provided with a shuffling circuit (7
The time base compression is performed by writing the digital video signals from a) and (7b) into the memory with a clock signal of 7 MHz and reading them out with a clock signal of 8 MHz.

The outputs of the time axis compression circuits (8a) and (8b) are CRC code signal addition circuits (9a) and (9b) -vertical parity check code signal addition circuits (10a) and (10b) -block address addition circuit (1), respectively. (Add block address every 6 lines) (11a), (11b) -Sequentially through the horizontal parity check code signal adding circuits (12a), (12b), if a bit error exists in the MSB, the error It is supplied to the 8-8 conversion circuits (13a) and (13b) for reducing the amount, respectively. The outputs of the 8-8 conversion circuits (13a) and (13b) are block synchronization signal adding circuits (14a) and (14b) -preamble and postamble adding circuits (15a) and (15b) -delay compensation circuit (16a), respectively. , (16b) in sequence and supplied to the parallel-serial conversion circuits (17a), (17b), respectively.

The outputs of the parallel-serial conversion circuits (17a) and (17b) are supplied to scramble circuits (18a) and (18b) for averaging the numbers of 1s and 0s of each bit, respectively. The outputs of the scramble circuits (18a) and (18b) are delayed by the delay compensation circuits (having a delay amount smaller than the delay amounts of the delay compensation circuits (16a) and (16b) described above) (19a) and (19b), respectively.
It is supplied to the L and ECL circuits, and their outputs are supplied to the reproducing rotary magnetic heads Ha and Hb, respectively, and recorded on the magnetic tape TP.

Next, the reproducing circuit system of this digital VTR will be described with reference to FIG. The digital video signal recorded on the magnetic tape TP is reproduced by the reproducing rotary magnetic heads H'a and H'b, and then is transmitted via the amplifiers (22a) and (22b) to the PLL (phase) for detecting the clock signal. Locked loop) and block synchronization signal detection circuits (23a) and (23b) are supplied respectively. The outputs of the circuits (23a) and (23b) are in series-
After being supplied to the parallel conversion circuits (24a) and (24b) and converted into parallel digital signals of -8 bits, they are supplied to the block synchronization signal and block address signal reproduction circuits (25a) and (25b), respectively. If the block address is reproduced, the address of each sample data is also found based on it. The outputs of the reproduction circuits (25a) and (25b) are passed through the 8-8 inverse conversion circuits (26a) and (26b) to the horizontal error correction circuit (27
It is supplied to a) and (27b) respectively. Horizontal error correction circuit (27
The outputs of a) and (27b) are vertical error correction circuits (28a) and (28).
b) respectively.

The outputs of the vertical error correction circuits (28a) and (28b) are output to the error detection circuits (30a) and (3) via the switching means (29a) and (29b).
0b) respectively. Then, during shuttle reproduction (variable speed reproduction), horizontal error correction circuits (27a) and (27b)
Is directly supplied to the error detection circuits (30a) and (30b) through the switching means (29a) and (29b).

The outputs of the error detection circuits (30a) and (30b) are supplied to the time axis error correction circuit and the time axis expansion circuit / deshuffling circuit (31a) and (31b), respectively, and the outputs thereof are deshuffling circuit (32a). , (32b), respectively.

The circuits (31a) and (31b) have a memory having a capacity of, for example, one field, and store sampled data for one field based on the block address during variable speed reproduction so that sampled data for one field is accumulated. Then, it is read out and sent to the deshuffling circuits (32a) and (32b). In fact, the same is true during constant speed reproduction. In addition, the outputs of the circuits (30a) and (30b) are written to the memory with a clock signal of approximately 8MHz and read out with a fixed 7MHz clock signal, so that the time axis is expanded and the write clock signal is timed. The time axis error is corrected by frequency-modulating according to the axis fluctuation. Deshuffling circuits (32a) and (32b) are 1/6 each
It has a memory with a capacity for lines.

The outputs of the deshuffling circuits (32a) and (32b) are supplied to the mixing circuit (33) and channel-decoded.
It is supplied to the error correction circuit (34). The output of the error correction circuit (34) is supplied to the luminance / chromaticity separation circuit and the chromaticity phase control circuit (35). The output of this circuit (35) is supplied to the horizontal and vertical and burst signal adding circuit (37) through the dark clip circuit and the limiter circuit (36), and the synchronizing signal source (38) is supplied to this circuit (37). Horizontal and vertical sync signals and a burst signal are added to the digital color video signal. The output of the sync signal adding circuit (37) is supplied to the D / A converter (38), and the P
The AL type analog composite color video signal is output to the output terminal (41) through the low pass filter and the buffer circuit (40).

Next, with reference to FIG. 4, a specific configuration of the shuffling circuits (7a) and (7b) in the recording circuit system of FIG. 5 described above will be described. The channel-coded 8-bit digital composite color video signal from the input terminal (42) is supplied to the memories (44) and (45) and written alternately, and alternately from the memories (45) and (44). The read digital composite color video signal is output terminal (4
It is designed to be output to 3). Reference numeral (46) is an address counter that counts the clock signal from the input terminal (46a) and generates an address signal. The parallel 13-bit address signal from this counter is used as the address selection circuits (48), (4).
9) and address encoders (50) and (51) are commonly supplied.

Now, the frequency Fsc of the color subcarrier of the PAL system is expressed by the following equation.

Fsc = (1135/4) Fh + Fv / 2 (1) where Fh is the horizontal frequency and Fv is the vertical frequency.

Fv / 2 in equation (1) is called an offset, which is an extremely small value compared to the first term, and is negligible between several consecutive lines, so equation (1) is an approximate equation as shown below. Represented.

Fsc ≒ (1135/4) · Fh ・ ・ ・ (2) From this equation (2), the color subcarrier and the horizontal sync signal are approximately 4
You can see that they are synchronized at the line cycle.

Now, Figure 1 A~H shows the phase S of the composite synchronizing signal SYNC and the burst signal of the respective lines of the PAL color video field signal of 8 fields of signal F ₁ to F _8. Then, at the phase S portion of the burst signal, the line signals L _{1 to} L ₄ are given to the respective line signals in consideration of the phase of the color subcarrier. 2A to 2D show the phases of the burst signals of the line signals L _{1 to} L ₄ , and assuming that the burst signals of the line signals L ₁ and L ₂ are positive, the burst signals of the line signals L ₃ and L ₄ are opposite. Be in phase.
Further, in FIG. 2 E~H shows the line signal L ₁ ~L ₄ color subcarrier phases are offset one by 90 °, the line signals L ₁ and
The color subcarriers of L ₃ are out of phase with each other, and the line signal L ₂
And the color subcarriers of L ₄ are out of phase with each other.

Then, the address counter (46) controls the start timing of counting for each field by the timing signal from the timing signal generator (5), and the timing counter of FIG.
As shown in D, the field signals of the first to fourth fields
F _{1 to} F ₄ are line signals L ₁ [generally Ln (n = 1 to 1
4)], writing to the memories (44) and (45) is started (the arrows in FIG. 1 indicate the writing range), and the field signals F _{5 to} F ₈ of the _fifth to _eighth fields are displayed on the reproduction screen. Of the line signal L ₃ [generally L _{(n + 2)} ), in order to avoid image quality deterioration due to a large change in the start line in the vertical direction of
_{L 5 = L 1, L 6} = L 2 a is] from the memory (44) is adapted to be started writing to (45). In this case, the phase of the color subcarrier of the line signal L ₃ is inverted with respect to the line signal L _1, so that the field signal of the fifth to eighth fields is
F ₅ to F ₈ are field signal F ₁ ~ of the first to fourth fields
For F ₄ , when writing to the memories (44), (45) starts at 1/2 of the cycle Tsc of the color subcarrier (the sample frequency is four times the color subcarrier frequency) as shown in FIG. Memory (44), (45) so that the phase of the color subcarrier at the write start portion is the same for both the field signals F _{1 to} F _{8 of the first} to _eighth fields. ) Is written. Considering this and the offset Fv / 2 in the above formula (1), the sample data of the portion surrounded by the solid parallelogram of the field signal of the first to eighth fields in FIG. 3 is stored in the memory (44). , (45).

Parallel 13-bit address signals from the circuits (48) and (49) are supplied to the memories (44) and (45), respectively. In the address selection circuits (48) and (49), the address signals obtained by switching the address signals directly from the address counter (46) and the address signals encoded by the address encoders (50) and (51) are switched, respectively. Memory (4
It is supplied to 4) and (45).

The selection control circuit (47) is controlled by the address counter (46), and the obtained selection control signal is used to select the address selection circuits (48), (49) and the memories (44) and (4).
5) supplied to. When the memory (44) is writing, the memory (45) is in the reading state, and when the memory (45) is writing, the memory (44) is in the reading state. Then, a parallel 8-bit digital composite color video signal is written in the memories (44) and (45) by the address signal from the address counter, and this is encoded by the address encoders (50) and (51). The digital composite color video signal is shuffled by being read by. In this case, the first sample data in which the phases of the color subcarriers of the field signals F _{1 to} F ₈ of the _first to _eighth fields of color framing are equal are stored in the memories (44) and (45) at address 0 (start address). Written as sample data of.

Meanwhile, conversely, the digital composite color video signal is encoded by the address encoders (50) and (51) by the address signals, and the memories (44) and (4
The digital composite color video signal may be shuffled by being written in 5) and read by the address signal from the address counter (46).

According to such an embodiment, in the recording circuit system, the PAL digital composite color video signal to be recorded is recorded with the same address for each field signal, and the recording is performed in the field memory of the reproducing circuit system. In the digital VTR signal processing method that writes the reproduced PAL system digital composite color video signal according to the address and reads the PAL system composite color video signal from the field memory, during variable speed reproduction such as high speed reproduction, It is possible to obtain a method in which the image quality and color reproducibility of the reproduction screen are good, the responsiveness to moving images and the like is good, and the capacity of the memory used at the time of reproduction is small.

〔The invention's effect〕

According to the present invention described above, in the recording circuit system, the PAL system digital video signal to be recorded is recorded with the same address for each field signal.
In the signal processing method of the digital signal recording / reproducing apparatus, the reproduced PAL system digital video signal is written to the field memory of the reproducing circuit system according to the address and the PAL system video signal is read from the field memory. The start address of the address assigned to each field signal of the PAL digital video signal to be recorded is one of the first 4 fields and the latter 4 fields of the 8 field sequence of the PAL digital video signal to be recorded. In the 4-field sequence of, the address of the line indicating one of the phases of the burst signal inverted every two lines is used, and in the other 4-field sequence of the 8-field sequence, the above two lines are used. Burst signal that reverses every time Shifting half cycle of the color subcarrier for starting material as well as the other address lines indicating the phase of the phase, to be recorded PA
Since the phase of the color sub-carrier for each field of the L system digital video signal is made the same, the image quality and color reproducibility of the playback screen are good and the response to moving images etc. is good during variable speed playback such as high speed playback. It is possible to obtain a signal processing method that is good and that requires only a small capacity of the memory used for reproduction.

[Brief description of drawings]

1, 2 and 3 are diagrams for explaining one embodiment of the present invention, and FIG. 4 is a block diagram showing an example of a shuffling circuit of one embodiment of the present invention, FIG. 5 and FIG. FIG. 6 is a block diagram showing a recording circuit system and a reproducing circuit system of a PAL digital VTR to which the present invention is applied. (7a) and (7b) are shuffling circuits, respectively.

Claims (1)

[Claims] 1. A PAL system digital video signal to be recorded is recorded in a recording circuit system by assigning the same address to each field signal, and the reproduced PAL is reproduced in a field memory of a reproducing circuit system. In the signal processing method of the digital signal recording / reproducing apparatus, which writes the digital video signal of the system according to the address and reads the video signal of the PAL system from the field memory, the digital video signal of the PAL system to be recorded. The start address of the address to be assigned to each field signal in the sequence of the first 4 fields and the sequence of the last 4 fields of the sequence of 8 fields of the PAL digital video signal to be recorded is one of the four field sequences. The position of the burst signal that is inverted every two lines In the sequence of the other 4 fields of the above sequence of 8 fields, the line indicating the other phase of the phase of the burst signal which is inverted every 2 lines. And the start sample is shifted by a half cycle of the color subcarrier so that the phase of the color subcarrier for each field of the PAL digital video signal to be recorded is the same. A signal processing method for a digital signal recording / reproducing apparatus.