JPS61177085A - Reproducing device - Google Patents

Abstract

PURPOSE:To obtain a video signal improved at its SN ratio and stabilized at its synchronizing signal by writing a reproduced modulating video signal in a memory only when the video signal exceeds a prescribed level at the time of speed variable reproduction to obtain a continuous video signal and adding a synchronizing signal to the video signal to reproduce and output the added signal. CONSTITUTION:At the time of speed variable reproduction, the digital data of a video signal are written in an address based upon a writing address signal VAD of a field memory 9A or 9B on the connecting side of a change-over switch 8 when a discrimination signal SD is turned to '1'. Although the digital data are written in the field memory 9A or 9B intermittently, the continuous digital data of the video signal are obtained from a change-over switch 22. At the time of speed variable reproduction, a synchronizing signal part of the digital data of the video signal obtained from the switch 22 is replaced by a synchronizing signal Psync generated by a synchronizing signal generating circuit 27 and the signal Psync is outputted through a D/A converter 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reproducing apparatus that demodulates a modulated video signal reproduced from a recording tape, writes it into a memory, and uses a read signal from the memory as a reproduced output.

[Summary of the invention]

The present invention provides a playback device that demodulates a modulated video signal played back from a recording tape and writes it into a memory, and uses a readout signal from the memory as a playback output. In some cases, writing to the memory is prohibited, and a synchronization signal is added to the signal read from the memory, thereby obtaining a high-quality image without bar noise, etc., and preventing synchronization from being disrupted. It is.

[Conventional technology]

In a rotating head type video tape recorder (VTR), when changing the tape running speed to perform variable speed playback such as slow speed, double speed, picture search, etc., the playback magnetic head is
A plurality of recording tracks T formed diagonally on the recording tape are scanned (see broken lines in FIG. 3). in this case,
For example, in a case where a guard band is formed between tracks, or a case where inclined azimuth recording is performed in which the recording azimuth is different between adjacent tracks, the envelope of the modulated video signal obtained from the reproducing magnetic head is The result is as shown in FIG. 4A. That is, when scanning between tracks, the output of the modulated video signal becomes extremely small.

Conventionally, during variable-speed reproduction, the modulated video signal obtained from the reproduction magnetic head is demodulated and output as is.

[Problem that the invention seeks to solve]

Conventionally, when performing variable speed playback, the modulated video signal obtained from the playback magnetic head is demodulated and the playback output is directly output.
This has the disadvantage that par noise appears on the screen, synchronization is disrupted in this area, and skew distortion occurs on the screen.

In view of these points, the present invention makes it possible to obtain a video signal having good S and a stable synchronization signal even during variable speed playback.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a recording tape (2).
The reproduced modulated video signal is demodulated and stored in the memory (9A
), (9B), this memory (9A), (
The readout signal from 9B) is used as the reproduction output. and,
During variable speed playback, when the modulated video signal is at a low level, writing to the memories (9A) and (9B) is prohibited, and a synchronization signal psync is added to the read signals from the memories (9A) and (9B). It is something.

[Effect]

During variable speed playback, the memories (9A) and (9B) K are intermittently and sequentially supplied with only demodulated video signals when the reproduced modulated video signal is at a predetermined level or higher, and are written to predetermined addresses. As a result, memory (9A).

A continuous video signal with good S/H is read out from (9B). Also, during variable speed playback, memory (9A).

A synchronization signal psync is added to the read signal from (9B), and a video signal with a stable synchronization signal and a good picture quality is obtained as a playback output.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG.

In the figure, (1) is a tape guide drum, and a magnetic tape (2) is wound diagonally around this drum (1) with an angular range of about 180 degrees, and is made to run at a predetermined speed. This magnetic tape +21K is F
For example, one field of an M-modulated video signal is recorded on one track, and adjacent tracks have different recording azimuths.

Further, (3A) and (3B) are rotating magnetic heads having different azimuth angles, and are arranged at an interval of 1800 angles. These heads (3A) and (3B) are made to rotate once in one frame, and therefore the head (
3A) and (3B) are configured to scan the magnetic tape (2) every other field.

The above is similar to the conventionally known rotary two-head type reproducing apparatus, and a modulated video signal is reproduced field by field by the heads (3A) and (3B).

The modulated video signals reproduced by the heads (3A) and (3B) are supplied to the FM demodulation circuit (5) via the reproduction amplifier (4). The demodulated video signal is converted into digital data by an A/D converter (6), and after being subjected to pedestal clamping, for example, by a clamp circuit (7), it is sent to the input side and B side fixed terminals of a changeover switch (8). Field memory (9
A) and (9B). This changeover switch (8
) is alternately switched to the input side and the B side for each field.

Further, the clamp circuit (7) is configured as shown in FIG. 2, for example. That is, the digital data of the video signal from the converter (6) is passed through a digital low-pass filter (
10, and high frequency component noise is removed. Further, this digital data from which noise has been removed is supplied as a sum of D flipflops α11, and pedestal data is latched every horizontal period from the signal fHK. Difference voltage data between this pedestal data and reference voltage data vR is output from the adder. Then, interpolation of this differential voltage data is performed by a digital low-pass filter αJ,
The differential voltage data is subtracted from the digital data of the video signal by the adder α, and its output, that is, the output of the clamp circuit (7), provides the digital data of the pedestal-clamped video signal.

This clamp circuit (according to 71) is a feedforward type, has a fast response speed, and performs accurate ramping. Also, since the video signal does not pass through a capacitor, etc., sag is less likely to occur. Note that the sync chip Clamping is possible as well.

Further, the video signal obtained from the FM demodulation circuit (5) is supplied to the synchronization separation circuit αS, and the horizontal synchronization signal PH obtained from this is supplied to the PLL circuit (lE9).
A write clock signal CLKw synchronized with the synchronization signal Pg is obtained from this PLL circuit Kasumi, and is supplied to the write address signal generation circuit ση. And this generation circuit (1
The write address signal wAD from 7) is supplied to field memories (9A) and (9B).

Further, the modulated video signal obtained from the amplifier (4) is supplied to the level discrimination circuit side. From this discrimination circuit (1B), when the level of the modulated video signal is above a predetermined level,
For example, a discrimination signal SD is obtained which has a high level of 1"1" and a low level of "O" at other times. This discrimination signal SD is transmitted to the field memories (9A) and (9B) through fixed terminals on the input side and B side of the changeover switch α9, respectively.
) as a write control signal. The field memories (9A) and (9B) are in a write state only when the discrimination signal SD is at a high level "1", and are in a read state at other times. In addition, selector switch a
9 is switched for each l field in conjunction with a changeover switch (8). That is, when the selector switch (8) is switched to the A side and the B side, the selector switch α9 is switched to the A side and the B side, respectively.

Also, ■ is an oscillator, and the read clock signal CTJCn from this oscillator ■ is the read address signal generating circuit C? ll is supplied. And this generation circuit +21
The read address signal RmD from 1 is supplied to field memories (9A) and (9B).

Further, the digital data of the video signals read from the field memories (9A) and (9B) are supplied to fixed terminals on the A side and B side of the changeover switch, respectively. This selector switch @ is switched for each l field in conjunction with the selector switch (8). That is, when the selector switch (8) is switched to the A side and the B side, the selector switch @ is switched to the B side and the A side, respectively.

The digital data of the video signal obtained from this changeover switch is supplied to the fixed terminal on the N side of the changeover switch @. The digital data of the video signal obtained from this changeover switch (c) is converted into an analog signal by a D/A converter (to) and obtained at the output terminal -.

Further, an oscillation signal is supplied from the oscillator (7) to a timing generation circuit 4, a timing signal sT from this generation circuit (2) is supplied to the synchronization signal generation circuit, and a timing signal sT is supplied from the synchronization signal generation circuit. A horizontal/vertical synchronization signal psync is generated based on the changeover switch (c).
is supplied to the fixed terminal on the T side.

Further, the timing signal sT from the generation circuit (G) is supplied as a control signal to the changeover switch (C) through the AND gate ■, and the changeover switch outputs the synchronization signal PSynC based on this timing signal S↑. The period is connected to T@, and the other times are connected to the A side. and gate (
), the signal S is at a high level '1' only during variable speed playback.
TR is supplied, and a timing signal sT is supplied to the switching switch (23) only during variable speed reproduction.

Incidentally, a servo reference signal 5REF is generated from the oscillator, and the drum servo and capstan servo are operated by this servo reference signal 5REF, and the field memory (9A
) and (9B), the read phase and write phase are synchronized.

This example is configured as described above, and in a certain field, the changeover switch (8) and α9 are connected to the A side, and the digital data of the video signal is supplied to the field memory (9 people), making it possible to write. At the same time, the changeover switch is connected to the B side, and the digital data of the video signal read from the field memory (9B) can be obtained from the changeover switch.

In addition, in the field following a certain field, the changeover switch (8) and α9 are connected to the B side, and the digital data of the video signal is supplied to the field memory (9B) to make it ready for writing, and the changeover switch (8) and α9 are connected to the B side. @ is connected to the input side, and the digital data of the video signal read from the field memory (9A) can be obtained from the changeover switch ■.

When performing variable speed playback such as slow speed, double speed playback, and picture search by changing the tape running speed, head (3A), (
3B) scans across multiple recording tracks formed on the magnetic tape, so the heads (3A) and (3B)
The envelope of the modulated video signal obtained is as shown in FIG. 4, as described above. That is, when scanning between tracks, the output of the modulated video signal becomes extremely small. In this case, from the discrimination circuit α&, for example, FIG.
A discrimination signal SD as shown is obtained. Therefore, when performing this variable speed playback, the discrimination signal SD is at a high level "1".
When , the digital data of the video signal is written to the address based on the write address signal WAD of the field memory (9A) or (9B) on the side where the changeover switch (81 is switched). field memory (9 people) or (9B)
The digital data written in the same way before the previous frame will remain at the address. Therefore, when performing variable speed playback, the field memory (9A) or (9A)
In B), digital data is written intermittently, and after several frames have passed, digital data for 1 field has been written. Therefore, the changeover switch @
The digital data of a continuous video signal is obtained from the .

Also, when performing this variable speed playback, an AND gate (
Since the signal STR supplied to the selector switch (231C) becomes high level, the timing signal ST is supplied to the changeover switch (231C,
The synchronization signal part of the digital data of the video signal obtained from the changeover switch @ is replaced with the synchronization signal psync generated by the synchronization signal generation circuit (5), and this is outputted via the D/person converter Q4.

Note that during normal playback, the heads (3A) and (3B) correctly scan the recording track on the magnetic tape (2), so
The modulated video signals reproduced from the heads (3A) and (3B) are always at a high level, and the discrimination signal SD is always at a high level "'1". Also, since the signal So supplied to the AND gate (to) is at a low level "IO", the digital data of the video signal obtained from the changeover switch (2) is output as is via the D/A converter (to). Supplied to terminal -. Other than that, the operation is the same as when performing variable speed playback.

As described above, according to this example, when performing variable speed playback, the digital data of the video signal when the modulated video signal from the heads (3A) and (3B) is at a predetermined level or higher is stored in the field memory (9A) * (9B) intermittently writes to this field memory (9A) # (9B)
Since it is obtained by reading out the digital data of a more continuous video signal, a video signal with good S can be obtained, and it is possible to prevent bar noise from appearing on the screen. Further, according to this example, when performing variable speed playback,
Since the synchronization signal portion of the digital data of the video signal read from the field memories (9A) and (9B) is replaced with the synchronization signal Psync from the synchronization signal generation circuit (2), a video signal with a stable synchronization signal is obtained.
It is possible to prevent a skewed cup from occurring.

Further, according to this example, since the read address signal RAD is generated based on the stable clock signal CLKa from the oscillator (2), a stable video signal without jitter can be obtained. Furthermore, according to this example, when variable speed playback is performed, writing is performed in the field memories (9A) and (9B) only when the level of the modulated video signal obtained from the heads (3A) and (3B) is above a predetermined level. Therefore, for example, in the case of so-called segment recording in which only a portion of each track is recorded, it can also be applied to simultaneous recording of Z tracks.

Further, according to this example, since the clamp circuit (7) is provided, the DC level between each track is kept constant during variable speed playback, and horizontal stripe noise can be prevented. .

In the above embodiment, an AND gate (2) is provided to control the supply of the timing signal sT to the changeover switch, but instead of providing the AND gate (to), a synchronizing signal is generated only during variable speed playback. The circuit (a) and the timing generation circuit [present] may be configured to operate. For example, if the timing generation circuit (C) is also used as another circuit (for example, the generation circuit (211)), an AND gate (G) is provided and the synchronization signal generation circuit □ is used only during variable speed playback. It may be configured so that □□ operates.

Further, in the above embodiment, the discrimination circuit CL81 is configured to operate even during normal reproduction, but during normal reproduction, the discrimination operation of the discrimination circuit α& is stopped and the signal SD is always at a high level "'1". ``'' may be configured.

〔Effect of the invention〕

According to the present invention described above, during variable speed reproduction, only the demodulated video signal when the reproduced modulated video signal is at a predetermined level or higher is written into the memory, and a continuous video signal is obtained from this memory. Since the synchronization signal is added to the video signal from the memory and used as the playback output, a video signal with a good S/N ratio and a stable synchronization signal can be obtained as the playback output. Therefore, bar noise and skew distortion on the playback screen can be prevented.

Further, according to the present invention, during variable speed playback, only the demodulated video signal when the played modulated video signal is at a predetermined level or higher is written to the memory, so even when playing back a tape on which segment recording has been performed, etc. Application is possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a clamp circuit used in the embodiment, and Figs. 3 and 4 are diagrams for explaining the present invention. be. (2) is a magnetic tape, (3A) and (3B) are rotating magnetic heads, (5) is an FM demodulation circuit, (8) HC1!3 and @ are changeover switches, (9A) and (9B) are field memories, 211 is a write address signal generation circuit, α& is a level discrimination circuit, (211 is a read address signal generation circuit, [Yes] is an output terminal, and 211 is a timing generation circuit.
Figure 1) is a synchronizing signal generation circuit, and Figure 1 is an AND gate. Fig. 2 of the clamp circuit

Claims (1)

[Scope of Claims] A determination circuit for determining the level of the modulated video signal, which demodulates a modulated video signal reproduced from a recording tape and writes it into a memory, and uses a read signal from the memory as a reproduced output; A synchronizing signal generating circuit is provided, and during variable speed playback, when the discriminating circuit determines that the level is low, writing to the memory is prohibited, and a synchronizing signal from the synchronizing signal generating circuit is provided to the read signal from the memory. A playback device that adds signals.