SU1012457A1 - Digital compensator for loss of television signal being reproduced - Google Patents

Abstract

DIGITAL COMPENSATOR LOSES-. ; TGP-TONE ALARM, containing an IfA unit, sequentially connected first storage register and first key stage, serially connected write address counter and second key stage connected to the address input of the memory unit, sequential drop detector, whose input is The second input, the device and the pulse former, the read address counter and the clock generator, the outputs of which are connected to the clock and setup inputs of the counter in the write and read addresses, as well as to the clock inputs of the memory unit, of the second: key stage and installation; to the input of the pulse former. Research institutes characterized in that: in order to expand functionality by increasing the completeness of loading the volume of the memory block while maintaining the parameters of the reproduced television signal, the first generator of the strobe and the Third key stage, the first information input of which is connected to the driver, are entered in it pulses of fallout, and the second is combined with an additional input of the memory unit, the second storage register connected in series, the fourth key stage, the t OR and arithmetic unit, the output of which is connected to the second i input of the second key stage, serially connected fifth key cascade and third gate driver, connected between the auxiliary output of the memory unit and the second control input of the arithmetic unit, and the second gate generator, 2 connected to the control terminal of the fourth and fifth key stages and to the third control input of the arithmetic unit; the output of the read address counter is connected 1C to the fourth input of the arithmetic unit th block, the output per keyword south kas4 kada - with a second input of the OR. the control input is with the output of the third gate generator, the setup vl and clock inputs of the gate drivers with the corresponding outputs of the clock signal generator.

Description

The invention relates to radio engineering and can be used in digital devices for processing a reproduced television signal. A digital device is known to compensate for the TV signal being reproduced. The digital signal contains the delay of the television signal for the time of two television lines and the first key stage, the first m inputs of which are connected to m outputs block zad kN ,. second m inputs-cm outputs of the memory block, control input - c. (t + 1) –1m output of the memory block, and m outputs –cm inputs of the delay block and m outputs of the device; The m inputs of the memory block are connected to the first input of the device, and (m + IJ-f. input through the drop pulse generator and the drop detector to the second input of the device, the address input of the memory block is connected to the outputs of the write and read address counters to the second input of the device, the clock and setup inputs of which are: -connected to the outputs of the sync signal generator, the other outputs of which are connected to the clock inputs of the delay block, the memory block and the second key stage in the memory block of the em syn Record the digital television signal and record information about the fallouts in it. When reading the memory block, the crash pulse interrupts its () -th output pulse output and simultaneously closes the circuit between the outputs the delay unit and the key stage. This ensures the inclusion of a replacement signal directly at the time of deposition, which is sufficient for high-quality processing of PAL and NTSC signals. However, such a device is not designed to compensate for the fallout of the reproduced television signal SECAM, in which, due to the chosen method of generating a color signal, it is necessary to replace the entire television line affected by the fallout. In addition, the introduction of an additional channel requires an increase in the information capacity of the memory block, which is also a disadvantage of the known device. Finally, a major drawback of this device is the need to build a special memory block — a digital block of the television signal delay for the time of two television lines. The information capacity of such a unit, regardless of the number of channels to which the parallel 1 input digital television signal, reaches when sampling a reproduced signal, for example, at a frequency of 17.625 MHz, is 16384 bits. Its implementation is very cumbersome and even when using expensive integrated circuits with a greater degree of integration, such as shift registers, 4.256 bits occupy a whole larger printed circuit board. Closest to the proposed digital device, suitable to compensate for the deposition of the reproduced television signal SECAM. containing a memory unit, connected in series the first storage register and the first key stage, serially connected write address counter and second key stage connected to the address input of the memory unit, connected in series the drop detector, whose input is the second input of the device and the drop pulse generator, read address counter and sync pulse generator, you (whose moves are connected to the clock and setup inputs of the write and read address counters, as well as clock The inputs of the memory unit, the second key stage and the installation input of the drop pulse generator. 2 However, this device also has the disadvantage of having to build a special memory block for the digital delay signal of the television signal by two lines. functionality by increasing the completeness of the loading of the block volume while maintaining the parameters of the reproduced television signal,. To achieve this goal in digital compensation deposition of a reproduced signal containing. a PSI unit, the first storage register connected in series and the first key stage, the write address counter connected in series, and the second key stage connected. to the address input of the memory unit connected in series, the fallout vector whose input is the second input of the device, and the fallout pulse driver, the read address counter and the clock generator whose outputs are connected to the clock and setup inputs of the read write address counters, and to the clock inputs of the memory unit, the second key stage and the installation input of the formation: the bodies of the precipitation impulses, additionally sequentially connected the first strobe generator and the cell chevy cascade, the first information input of which is connected to the output of the discharge driver, falls, and the second is combined with the additional input of the memory block, the second storage register connected in series, the fourth key cascade, the OR element and the arithmetic unit whose output is connected to the second input the second key stage, the fifth key stage and the third gate generator Yu connected in series between the additional output of the memory unit and the second control input of the arithmetic unit a, and the second gate driver connected to the control inputs 15 of the fourth and fifth key stages and to the third control input of the arithmetic unit, the output of the read address counter connected to the fourth input of the arithmetic unit 20, the output of the first key stage with the second the input of the OR element, and its control input — with the output of the third strobe formation, the setup and clock inputs of the strobe generator — with the corresponding outputs of the clock generator.

In FIG. Figure 1 shows the structural electrical circuit of the digital compensator for the fallout of the reproduced, d television signal; in fig. 2 time diagrams for his work.

The digital compensator for the fallout of the reproduced television signal contains the arithmetic block 1, 5, the first key stage 2, the input of which receives the correction signal from the output of the first storage register 3, the second key stage 4, which commutes the signals, which arrive at 40 address input of the memory block 5 s. -, the stroke of the write address counter 6 and through the arithmetic unit 1 from the output of the read address counter 7, the third key stage 8, to the control 45 input of which signals are generated that are generated in the pulse shaper are dropped 9th on the commands coming from the Drop Detector 10; through the first gate driver 11, from the fourth key stage 12, to which B1 comes the correction signal from the second storage register 13, the output ac through the element OR 14 to: the chemical unit 1, the fifth key stage 15, from the code: which signal It enters the third gate driver 16, and the control input to the gate comes from the output of the second gate driver 17. The entire device is synchronized by the driver of 60 clock pulses 18.

; The device works as follows.

An introductory digital thermal signal, parallelized on m channels, 5

T the first input of the device enters the storage in the memory block 5, with 1; volume three key Cascade 8 does not prevent the signal from passing through the -th channel, Information capacity; memory location N is equal to,

N (n + k)

de p is the number of TV L lines, which are pre-fanged; p p is the number of bits carrying information from one television line in each of the m channels; k is the number of bits that carry information about the presence or absence of one or more dropouts in a given TV line.

Lengthening of packets of impulses on. k bits for each television line is possible when processing (i.e., writing to memory block 5 and reading from it) only its so-called autonomous part, equal, in the case of the color signal SECAM, the duration of the television line without

taking into account the time intervals between the fronts of the gasshero and the synchronization of its pulse lines and the interval from the front of the synchronizing pulse of lines

(from the beginning of the line b) to the end of the chrominance signal quenching. If the playback conditions from the video recorder are such that the length of the unused part of the television line either does not change (for four-head video recorders) or changes to the extent that the active parts of the lines are not allowed with the necessary margin (for single-head video recorders that provide playback up to ten times the rate of permutations) , then there are always time intervals during which it is possible to carry out both writing to the memory block, as well as reading additional k bits from it rmatsii.

As sequential input; Sp-bit parallel layers in the pth cell of memory block 5 (Fig. 2a), the deposition detector 10, to the input of which a reproducible television signal is supplied from the second input of the device, records the occurrence of depositions in the recorded line. Regardless of their number and duration of shaper shaper, impulses of fallout 9 responds only to the command given.

the moment of occurrence in this line of the first fallout. In the presence of such

the commands at the output of the deposition impulse generator 9 appear high potential (logical unit), which remains there until the moment in C-. , laziness of the corresponding sync pulse in the zone of the next horizontal quenching interval (Fig. 2e, c). In the absence of fallout at the output line of the output pulse shaper 9, the potential remains low (logical zero). At the moment of the end of the Record to the PS1m TI 5 nth bit of information on the command of the first shaper 11 (Fig. 2b, c, d), the third key stage 8 switches the th input of the memory unit 5 from the first input of the device to the pulse shaper fallout 9 and keeps it in this position for k clock intervals, thus providing, depending on the presence of high or low potential at the input of the third key stage 8, writing to memory block 5, or k logical units, or k logical zeros are added (Fig. 2e). Thus, suschestvl an entry in the memory unit 5, information about the presence or absence of a given television line deletions. Using k 1 improves system reliability. The readout of nm-bit parallel layers from a number of cells of memory block 5 is performed with an average delay of p / 2 lines, which is achieved by setting the read address counter 7. The information about the presence in the read line of depositions is retrieved in advance, namely from the start of reading k -th bits of information from (p-1) -th p d cells of memory block 5 for k clock intervals of time (Fig. 2g). This is precisely the duration of the strobe, the output of the strobe 17 produced by the shaper is selected, which simultaneously open the fourth 12 and fifth 15 key helmets, dy, and the arithmetic unit 1 switches i s to summation mode (fig.2z, k) to the current addresses reading from memory 5 through the fourth key cascade 12 and the OR element 14 from the second storage register 13, an arithmetic unit 1 introduces an equal value of n bits, which allows direct reading of n bits of information from (p- 1) d yes cell memory block 5 to organize the reading of k bits of information not from (p-1) -th, but immediately from p-th p d cells, thus anticipating reading p bits of information from this row (Fig. 2l). Through the open fifth keynote cad 15, read bits of information from the pth row from the tth output of the memory block 5. Go to the third gate of the strobe IF. If in the ID -and the TV strobe when recording to the memory block 5 one or several drops are recorded, i.e. If the k-bits of information were read out as a sequence of k logical 5s units, then at the moment when the k-ro bit of information is finished reading from the p-th row of cells, a high potential (logical unit) appears at the output of the third forming gate 16, which is stored there remaining quenching time and n more clock intervals (Fig. 2m). This opens for the introduction of an amendment value of 2 from the first storage register 3 to the first key stage 2, and the arithmetic unit 1 switches to the subtraction mode. Such a re- commutation allows the correction to be made to the current readout addresses from memory 5 within the specified time interval, so that instead of referring to the p-th p d cell, the k (p-2) p p d cell starts. This provides for the inclusion of a replacement signal at the time of a television line affected by one or several drops (Fig. 2n). If, however, in the pth TV line, when recording to the memory block, 5 dropouts were not recorded, i.e. read k bits of information are a sequence of k logical zeros of the order, then at the moment when the k-ro bit of information is read out of the p-th p d cells at the output of the third generator of gate 16, the potential (logic zero) is low, blocking the introduction of the correction through the first key stage to the arithmetic unit 1, And since after the k clock intervals elapse, the fourth 12 and fifth 15 key stages are also locked, then no correction is introduced into the current read addresses of the memory block and, therefore, As a matter of fact, after reading the n bits of information from (p – 1) p of d cells, the next packet of n p r p d cells begins to pass to the device output. It should be noted that the introduction of additional information about fading into a digital television signal cannot fundamentally degrade the quality of reproduction, since the inputted k bits of information are located in un-. the used part of the television line, kbtora, furthermore, at the output of the digital temporal distortion corrector, is fully regenerated to ensure compliance with GOST 7845-79 (Fig. 2о, p). Thus, in the proposed device, the reproduction of the reproduced television signal is compensated without using additional memory devices, and, at the same time, without increasing the actual information capacity of the gang unit by ensuring the functional completeness of loading its volume.

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Claims (1)

DIGITAL COMPENSATOR LOSS -. '.NEW PLAYBACK TV signal containing a block of memory,' sequentially connected the first storage register and the first key stage, series-connected record address counter and second key stage, connected to the address input of the memory block, series-drop detector whose input is the second input of the device and the drop driver, the counter of read addresses and the driver of the clock signals, the outputs of which are connected to the clock and installation inputs of the hell meters recording and reading, as well as to the clock inputs of the memory block, the second key stage and the installation input of the drop-down pulse shaper, characterized in that, in order to expand the functionality by increasing the completeness of loading the volume of the memory block while maintaining the parameters of the reproduced television signal, it - the first gate driver and the third key cascade are connected in series, the first information input of which is connected to the output of the pulse shaper, and the second combined with additional input of the storage unit, serially connected second storage register, the fourth key cascade, and an OR arithmetic unit, whose output is connected to _a second input of the second core stage, thus po- $ fifth switch connected howling stage and the third gate driver included between an additional output of the memory block and the second control input of the arithmetic block, and the second gate driver connected to the control inputs of the fourth and fifth key stages and to the third the control input of the arithmetic block, while the output of the read address counter is connected to the fourth input of the arithmetic block, the output of the first key stage is connected to the second input of the OR element, and the control input is connected to the output of the third gate driver, the setting and clock inputs of the gate formers the outputs of the shaper of the clock signals. · the memory is connected to the first device, and the (w + 1) -th input of the pulse shaper drop out the detector of the drops to the second device; address input