SU1290564A2 - Digital storage for processing television signals reproduced from video tape recorder - Google Patents

Abstract

 This invention relates to magnetic recording of television signals. In relation to A. and.with. No. 1104689 extends the functionality of the device by processing the signals of the test television lines. The device contains blrk 1 and 2 of memory, counters 3, 16 write addresses, counters 4, 23 read addresses, sync selector 5, shapers (F) 6, 24 clock pulses, F 7, 11, 1-9 horizontal sync pulses, F 8, 12, 25 start counting of lowercase sync pulses, F 9, 13, 21 gates, keys 10, 14, 17, 22, F 15, 26 frame sync pulses, clock generator 18, counter 20 horizontal sync pulses, element OR 32. Newly entered sequentially connected f 27 clock pulses, f 28 strobe, f 29 additional frames of sync pulses and the element OR 31. 2 ill. (Oh cl N5; about JV O) 4 to

Description

The invention relates to the magnetic recording of television signals and can be used in compensators of temporary distortions of video recorders and is additionally the 1st to the author. No. 1104689.

The purpose of the invention is to expand the functionality of a digital storage device for processing television signals reproduced from a video recorder by processing signals from test television lines.

FIG. Figure 1 shows the electrical circuit diagram of a digital storage device for processing television signals reproduced from a VCR; in fig. 2 are vector diagrams illustrating the operation of a digital storage device for processing television signals reproduced from a VCR.

A digital storage device for processing television signals reproduced from a video recorder comprises (FIG. 1) a first memory block 1, whose information input is the information input of a digital storage device for processing television signals reproduced from a video recorder. The information output of the first memory block 1 is connected to the information input of the second memory block, the information output of which is the information output of the digital memory.

for processing television signals, 40 pulses. First shaper output

15 frame sync pulses connected to the first input of the second counter 16 write addresses, the second input of which is connected to the output of the second key 14.

45 The output of the second counter 16 of the write addresses is connected to the first input of the third Key 17, the output of which is connected to the address input of the second memory block 2. The first output of the sync generator 18 is connected to the first input of the third shaper 19 horizontal sync pulses, the output of which is connected to the first input of the counter 20 horizontal sync pulses. Output counter 20

55 horizontal sync pulses connected to the first input of the third gate driver 2.1, the output of which is connected to the first input of the fourth key 22. The output of the fourth key 22 is connected

playable from a VCR. The address input of the first memory block 1 is connected to the first output of the first counter 3 write addresses. The read address input is connected to the first output of the first 4 read address counter. The input of the sync selector 5 is the sync input of a digital storage device for processing television signals played from a video recorder. The first output of the sync selector 5 is connected to the input of the first shaper of 6 clock pulses., The output of which is connected to the first input of the first shaper of 7 horizontal sync pulses. The output of the first driver 7 horizontal sync pulses connected to the first input of the first form

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tel 8 start counting lowercase pulse synchronization, the output of which is connected to the first input of the first shaper 9 gate. The output of the first gate driver 9 is connected to the first input of the first key 10. The output of the first key 10 is connected to the first input of the first counter 3 of the write addresses and the clock input of the first block 1 of the memory. The second input of the first shaper 9 strobe is connected to the second output of the first counter 3 write addresses, the second input of which is connected to the output of the first shaper 7 horizontal sync pulses. The output of the first shaper 6 clock pulses is connected to the second input of the first key 10 and to the second input of the first shaper 8 of the counting beginning of the lower case pulses. The output of the second shaper 11 horizontal sync pulses connected to the first inlet of the second shaper 12 start counting lowercase sync pulses, the output of which is connected to the first input of the second shaper 13 of the gate. The second input of the second gate driver 13 is connected to the second output of the first counter of 4 read addresses. The output of the second gate driver 13 is connected to the first input of the second key 14, the output of which is connected to the read clock input of the first memory block 1, to the write clock input of the second memory block 2 and to the first input of the first counter of the 4 read addresses, the second input of which is connected to output of the second shaper 11 horizontal synchronization clock read input of the second memory block 2, with the first input of the second counter 23 read address and with the second input of the counter 20 horizontal sync pulses. The output of the second read address counter 23 is connected to the second input of the third key 17, the third input of which is connected to the second output of the clock 18 The third output of the clock 18 and connected to the second input of the fourth key 22 via the second clock generator 24 lowercase sync pulses, with the second input of the second key 4, with the second input of the second shaper 12 start counting lowercase sync pulses, with the first input of the second

shaper 11 horizontal sync pulses, - with the first input of the first shaper 15 cadre sync pulses, with the first input of the second shaper 26 cadre sync pulses and through the third shaper 19 horizontal sync pulses and the third shaper 25 start counting the lower sync pulses, with the second input of the third shaper 21 st. An additional output of the clock 18 is connected to the first input of the third shaper 27 clock pulses, the output of which is connected to the first input of the fourth shaper 28. The first output of the fourth gate driver 28 is connected to the first input of the first driver 29 additional frame clock pulses, the second input of which is combined with the second input of the third driver 27 clock pulses and connected to the first output of the clock 18, and the first output is connected to the first input of the second driver 30 additional frame sync pulses . The second input of the second shaper 30 additional personnel sync pulses is connected to the second output of the fourth shaper 28, the third input is combined with the second input of the first shaper 7 horizontal sync pulses, with the second input of the second shaper 11 horizontal sync pulses and connected to the second output of the sync selector 5, and the junction is connected. the input of the first element 31 OR, the second input of which is connected to the third output of the sync selector 5, and the output from the second 10

905644

eye entrance of the first shaper 15 personnel sync pulses. The second output of the first shaper 29 additional frame sync pulses is connected to the second input of the fourth gate shaper 28 and to the first input of the second OR element 32, the second input of which is connected to the fourth output of the synchro generator 18, to the output from the second input of the second shaper pulse 26 of the sync pulse, the output of which connected to the second input of the second counter 23 read addresses,

A digital storage device for processing television signals reproduced from a video recorder operates as follows.

A television signal reproduced at a certain speed of a video tape in the form of a digital stream parallelized into m channels, pos15

20

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blunt to the input of the first block 1 of memory, which aligns the duration of the reproduced active line to the nominal value due to the distortion of the blanking interval while maintaining the total duration of the reproduced television line constant. At the same time to highlight c. the reproduced line H of its active part - the active line; it is necessary to form a strobe pulse of the T record ... Such a form

This is done by the first gate driver 9, and this is done in such a way that the reference time point O coincides with the leading edge of the reproduced horizontal sync pulse. To do this, the control input of the first shaper 8 for counting the lowercase sync pulses from the first shaper of the lower sync pulses receives a reproducible 1 st line pulse, previously compressed with a reproducible clock sequence of pulses, thereby opening an auxiliary counter located in the first shaper of 0 - 8 counts horizontal sync pulses, which counts the number of reproducible clock pulses ranging from O to the beginning of the active line. Upon reaching this point in the first format-. At the beginning of the counting of the lower-case sync pulses, a pulse is generated that triggers the first driver 9, which opens the first

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51290564

It makes it possible to record driving bits carrying the active playback of the first memory block 1. 3 addresses of the record, which is carried out in n t nn n with p n p n o

at time 0 „, i.e. during the blocking of the recording process, counts the number of reproducible clock pulses necessary to record the active line. If the active line information is carried N.

ft

samples following the frequency f in each of the hectares of the parallel channels, the duration of the recorded active line being reproduced will be equal to

H

AK

 N.

When the last bit of the active line enters the first block 1 of the memory, the decoder located in the first gate 9 is received the corresponding code i ;. the combination from the first counter of the 3 write addresses generates a pulse, which stops the effect of the write gating pulse. The first key 10 is closed, which prevents recording to the first memory block 1 before the next active line of the television signal,

The read strobe from the first memory block 1, which is generated similarly to the strobe pulse, is written to, with time 0, also bound to the leading edge of the reproduced line pulse, but reading the recorded information occurs at the reference clock frequency f corresponding to the nominal speed of the tape. As a result, the duration. readable active line) is equal to

before

and it turns out from being recorded by

  "AN-NDS

N (1;

This in turn affects the duration of the read gating pulse from the first memory block 1.

 N.N. . At the same time, the reproduced horizontal pulse is phased.

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in the second generator of 11 horizontal sync pulses, the reference clock pulse sequence coming from the second generator of 24 clock pulses, and an auxiliary counter located in the second generator 12 of counting waste synchro pulses to achieve an average read start delay of, in addition to the number of reference clock pulses, OH, before the start of the active row, counts the AND number of pulses, adequate to half the information capacity of the first block of 1 memory in each of m parallel channels. This solution provides correction of the active line duration when the reproducible clock frequency deviates on both sides from the nominal value. The length of the corrupted portions of the rows is corrected in the second block of 2 memories, which, by virtue of its larger information capacity, allows to restore the nominal durations in the reproduced television signal. The order of the alternation of the write and read processes is controlled by the third key 17 by commands from the sync generator 18.

Since, in accordance with the accepted processing algorithm, the gating

The read pulses from the first memory block 1 and the write gates to the second memory block 2 must match in all respects, then the read strobe pulse,

formed in the second gate generator 13, opening the second key 14, thereby allowing the reading of information read from the first memory block 1 into the second memory block 2.

The information is recorded using the second counter 16 of the write addresses, which is of sufficient size to access any cell of the second memory block 2. A preset of the second counter 16 of the write address is produced by frame reproducible pulses. After phasing in the first shaper 15 frame sync pulses

clock sequence received from the second generator 24 clock pulses, they arrive at the installation input of the second counter 16 addresses of the record.

The information recorded in the second memory block 2 is read at the same recording of the reference clock frequency f, however, the time point 0 of the read gating pulse from the second memory block 2 is associated with the leading edges of the reference horizontal pulses following the Hp period. Therefore, the active | lines H and are read from the second memory block 2 without changing the time scale, and the pause times dT are aligned to the nominal values T.

The formation of a read pulse in the third gate generator 21 begins with the fact that a reference pulse, pre-phased with a reference clock sequence of pulses, arrives at the control input of the third generator 25 at the start of counting the horizontal sync pulses from the third generator -19 horizontal sync pulses thereby opening an auxiliary counter, located in the third driver 25, of the start of counting of the horizontal sync pulses, which counts the number of reference clock pulses , laid out from the moment O to the beginning of the active line. When this point is reached, a third pulse shaper 25 produces a pulse that triggers the third strobe generator 21, which opens the fourth key 22, which permits reading the first and subsequent bits carrying information about the active line from the second memory block 2.

The second read address counter 23 has a number of states that provides access to any cell of the second memory block 2. However, this number significantly (ten or more times) exceeds the number of bits in the active row. Therefore, to eliminate ambiguity in determining the end point of the read gating pulse, the device uses a counter 20 horizontal sync pulses whose number of bits is matched with the number of bits in the active line. Preset of the counter 20 horizontal sync pulses is carried out at the moment of time 0ts (in the period of blocking the reading from the second block 2

memory) phased reference clock sequence reference lowering pulse. When reading information from the second memory block 2, the 20 horizontal sync pulse counter counts the number of reference clock pulses needed to read the active line. The decoder located in the third gate generator 21, upon receipt, from the 20 horizontal sync pulse code counter corresponding to the last 6, is received. active line, produces a pulse, terminating the effect of a read gating pulse. The fourth key 22 is closed, which does not allow reading from the second memory block 2 until it is time to read the first and subsequent bits of the next active row.

A preset of the second read address counter 23 is produced by frame reference pulses. After phasing in the second shaper 26 frame sync pulses with the reference clock pulse sequence following from the second shaper 24 clock pulses, they arrive at the set input of the second counter 23 of the read addresses.

The initial frame synchronization process starts at the time of the appearance of the leading edge of the frame damping pulse P P, which arrives relative to the reproduced signal not at the moment of the end of the active part of the field, but later by an amount equal to half the information capacity of memory block 2. This is due to the fact that reading from memory block 2 is performed with a delay equal to half of its information capacity with reference to an external reference source of clock signals. Therefore, the frame signals from the sync generator 18 are delayed with respect to the reproduced television signal by the same amount. The RVB impulse, after the necessary clocking by lower-case reference pulses in the third shaper 27 clock pulses, opens the fourth shaper 28, generating a strobe, the leading front of which, in turn, enters the information input of the second shaper 30 more

tel HR sync pulses. Here, this front is linked to line reproduced pulses and an additional personnel pulse is formed, which is formed in this way at the input of the first RSHI element 31, where it is combined with a reproducible personnel sync pulse coming from the sync selector 5. Simultaneously formed in the fourth gate driver 28 is inverted - the strobe enables the first shaper 29 additional personnel sync pulses, which generates an additional reference personnel impulse The average delay is equal to half the information capacity of memory block 2. The required delay is carried out using a counter, the transfer pulse of which goes to the second input of the second element, 32 OR as an additional reference personnel pulse, as well as to the second input of the fourth gate generator 28, where it stops forming the gate, which, in turn, closes the counter of the first imager 29 additional personnel clock pulses. The second input element 32 OR receives a reference frame pulse from the clock 18, which is combined with the additional frame sync pulses formed in the first shaper 29. To form a narrow additional reproducible frame pulse, the signal from the second frame shunt is received from the second frame sync pulses. from the bits of the counter of the first former, 29 additional personnel sync pulses.

one

Splitting the frame synchronization process into two stages avoids the loss of information at 1 by establishing a new one.

additional time synchronization ep read, committing still (K + 1) -th

circulation cycle, ahead of the recording vector by the value of (N - H - tj) O (Fig. 2e). When the vector reaches

M in one of the preceding, in relation to the (K + 1) th cycle, reversal cycles. The condition for additional frame synchronization is compliance with the inequality dK L1 (Fig. 2a).

The write vector, which is ahead of the read vector by an amount, reaches, for example, in the Kth cycle

reading the moment M, he also ends his (k + 1) th circulation cycle, resetting at the moment M. At this point, the frame synchronization process ends in the proposed device.

10 and reset to

left moment MO (fig. 26). At the same time, the read vector, which completes the kth cycle, is ahead of the recording vector, which started its (K + 1) th cycle, by the value of e QK + ifv - (. Condition eO is a guarantee against information loss at this stage of frame synchronization .

When the read vector reaches the moment M. and is reset at the moment .MO, the normal position is restored, at which the read vector in its (K + 1) -th cycle is separated from the write vector by the value (Fig. 2c). However, now the moment of the main frame synchronization m due to underutilization of the information capacity of memory block 2 in the k-th cycle is in the (k + 1) -th cycle shifted relative to the moment M by the value of A NJ, - iK - (, t. e. the time interval UK between the moments of M and M. in

oII

This case is equal to dk DK + / 1 uK + N - iK-U) N-4

(Fig. 2d). . The value of A, and hence the value of W, must be chosen in such a way that on a given dk, even in the case when AK4tj, to ensure the strict inequality iK Sij. Solving this inequality simultaneously with the above condition 6 O with respect to H, you can get

i7-uK 4 / N -fj.

l

Thus, given N, i, & K, it is always possible to choose such that information loss, including the test line signal, will not occur.

In Ck + 1) -th cycle, when the moment M is reached, the recording vector is reset at zero time, starting the first reversal cycle in a new image field. At this time, the vector

reading the moment M, it also ends its (k + 1) th access cycle, resetting at the moment M. At this point, in the proposed device, the frame synchronization process ends.

Formula of the invention Digital storage device for processing television signals reproduced from a VCR on the author. No. 1104689, characterized in that, in order to expand the functionality of a digital storage device for processing television signals reproduced from a video recorder, by processing the signals of test television lines, the third connected clock generator, the fourth gate driver, the first driver additional cadre clock pulses, the second shaper of additional cadre clock pulses, and the first element OR the second input of which connects with the third output of the sync selector, and the output with the second input of the first form

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HR sync puller, the first input of the third clock generator is connected to an additional output of the clock generator, the first output of which is connected to the second input of the third clock generator and to the second input of the first generator of additional personnel clock pulses, the second output of which is connected to the second input of the fourth gate generator, and a second sync pulse, the second output of which is connected to the second input of the fourth gate generator and the second clock sync pulse. the OR element — with the second input of the second shaper frame sync pulse; the second input of the second OR element is connected to four fifth clock output, the second output of the fourth strobe shaper is connected to the second input of the second shaper additional vertical sync pulses, a third input coupled to the second output sinhroselektora.

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Editor V. Kovtun

Compiled by A. Fedotov

Tehred and Popovich Proofreader Reshetnik.

Order 7918/59

Circulation 660

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

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Claims (1)

SUMMARY OF THE INVENTION Digital storage device for processing television signals reproduced from a VCR by autosw. No. 1104689, characterized by the fact that, in order to expand the functionality of digital. a third storage device for processing television signals reproduced from a VCR by processing the signals of test television lines, a third clock driver, a fourth strobe driver, a first additional frame sync driver, a second additional frame sync driver and a first OR element are introduced, the second input of which is connected to the third output of the sync selector, and the output to the second input of the first When framing personnel clock pulses, the first input of the third clock driver is connected to an additional output of the clock generator, the first output of which is connected to the second input of the third driver of clock pulses and the second input of the first driver of additional frame clocks, the second output of which is connected to the second input of the fourth gate driver the second OR element - with the second input of the second driver of the frame sync pulses, the second input of the second OR element is connected to the fourth in swing clock, a second output of the fourth gate driver connected to the second input of the said second additional vertical sync pulses, a third input coupled to the second output sinhroselektora.