SU1499436A1 - Multichannel generator of pulse trains - Google Patents

Abstract

The invention can be used in automatic control devices. The purpose of the invention, the extension of functionality, is achieved by introducing a register 10 in which a control code is stored that determines the operation mode of the pulse train generation channels 8. The storage unit 17 stores codes defining the number of pulses in a series for each channel 8 of forming a series of pulses. The channel number 8, in which the code is written, determines the decoder 9. The device also contains a generator of 1 clock pulses, an OR element 2, AND 3, 4 elements, shapers of 5-7 pulses, control inputs 11-14, information inputs 15, outputs 16.1 -sixteen. N channels. 1 hp f-ly, 1 ill.

Description

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It determines the mode of operation of channels 8 for forming a series of pulses. Memory unit 17 stores codes defining the number of pulses in a series for each channel 8 of forming a series of pulses. Channel number 8, in which the code is written,

identifies the decoder 9. The device also contains a generator of 1 clock pulses, an element OR 2, elements AND 3, 4, drivers 5-7 pulses, control inputs 11-14, information inputs 15, outputs 16.1-16.P channels. 1 hp f-ly, 1 ill.

The invention relates to a pulse technique and can be used in automatic control devices, as well as in computing devices.

The purpose of the invention is to expand the functionality by ensuring the start-up of channels of forming a series of pulses at different times and successively.

The drawing shows the function

device schematic.

The multichannel generator of a series of pulses contains a generator of 1-stroke pulses, an element OR 2, elements 3 and 4, shapers 5-7 pulses, channels 8,1-8. N forming series, pulses, a decoder 9, register 10, inputs 11 -14. Control, information inputs 15, outputs 16.1-16.p channels, block memory to 17.

The output of the generator 1 is connected to the first inputs of the formate 6 and 7, channels 8, the memory unit 17 and the gate of the decoder 9. The input 11 through the OR element 2 is connected to the second: 1 and the driver 6, the output of which is connected to the second input of the storage unit 17 the third input of which is connected to the input 13. The input 12 through the element AND 3 is connected to the second input of the element OR 2. The input 14 is connected to the fourth input of the storage unit 17, the first output of which is connected to the second input of the imager 7, the output of which connect to the second channel inputs in 8. The second outputs of the storage unit 17 are connected to the corresponding information inputs of the decoder 9, each of the n outputs of which are connected to the third input of the corresponding channel 8. The last output of the decoder 9 is connected to the resolution enable input of the record 10. The third outputs remember

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block 7 is connected to the information inputs of the register 10 and the fourth inputs of channels 8. The outputs of register 10 are connected to the corresponding fifth inputs of Channel 8, the first inputs of channels 8 to the corresponding inputs of the element

And 4, the output of which is connected via shaper 5 to the second input of element 3. The second outputs of the channels 8 are the outputs of 16 channels. The third output of the previous channel 8 is connected to the sixth input of the subsequent channel 8. The third output of the last channel 8 is connected to the sixth input of the first channel 8. Information input 15 is connected to the fifth input of the storage unit 17.

Channel 8 of forming a series of pulses contains multiplexer 18, trigger 19, element 20, counter 21,

The output of the multiplexer 18 is connected to the input of the preset trigger 19, the direct output of which is connected to the first input of the element AND 20, the bb of which is connected to the counter input of the counter 21 and is the second output of channel 8, the second input of the element 20 and 20 is the first input of channel 8, The first input of the multiplexer 18 is the second input of channel 8, the second input of multiplexer 18 is the sixth input of channel 8, the input of the address of the multiplexer 18 is the fifth input of the channel. 8, the write enable input of the counter 21 is the third input of channel 8, the information inputs of the counter 21 are the fourth inputs of channel 8. The overflow output of the counter 21 is connected to the installation input of the trigger 19 and is the third output of the channel 8, and the inverse output of the trigger 19 is the first output of the channel eight.

The storage unit 17 contains a trigger 22, a multiplexer 23, a delay element 24, an element 25, a counter 26, a random access memory (RAM) 27,

The inverse output of the trigger 22 is connected to the first input of the AND element 25, the output of which is connected to the installation input of the counter 26, the overflow output of which is connected to the installation input of the trigger 22 and is the first output of the storage unit 17. The outputs of the counter 26 are connected to the corresponding address inputs of the RAM 27 and are the second outputs of the storage unit 17. The control input of the multiplexer 23 is connected to the second input of the AND element 25, the mode selection input of the RAM 27 and is the third input of the storage unit 17. The first input of the multiplexer 23 s Connections with the input of the delay element 24 and is the fourth input of the storage unit 17, the output of the delay element 24 is connected to. the entry gate of the RAM 27, whose information inputs are the fifth inputs of the storage unit 17. The second input of the multiplexer 23 is the first input of the storage unit 17. The preset input of the trigger 22 is the second input of the storage unit 17. The output of the multiplexer 23 is connected to the counter installation input 26. The outputs of the RAM 27 are the third outputs of the storage unit 17.

The device works as follows.

Inputs 11-14 of control and informational inputs 15 are connected to the parallel interface terminals.

The multichannel generator operates in the following three modes: the recording mode, when the storage unit 17 records information from the information inputs 15 on the number of pulses in each series and on the sequence of the series; single pulse mode; the cyclic loop input mode of the counter 26 pulses from a geotic (periodic) generation of a series of pulses.

In the initial state, the trigger 22 of the storage unit 17 and the triggers 19 of the channels 8 are reset, the counter 26 is in the initial state, and the input 14 does not receive pulse signals.

In the first mode, the multichannel generator operates in a consistent manner.

To translate into this mode, it is necessary to send a zero signal to the input 13. At the same time, the RAM 27 switches this mode to the recording mode of the nulerator 1. After that, the triggering signal from input 1.1 through the OR element 2 enters the second input of the imaging unit 6, which produces a signal synchronizing with generator 1 pulses, which enters the trigger setup input 22. This signal A block 17 is started, memorizing, which inputs into the counters 21 channels 8 an information about the number of pulses in the generated series and myles and into register 10 the code for the order of the series. This happens as follows. Zero signal with inverse

The output signal at the control input of the multiplexer 23 allows the passage of pulse signals from the input 14 through the multiplexer 23 to the counting input of the counter 26. In addition, from the reset input of the counter 26 is removed the signal to prohibit the counting, received up to this point from the output of the element

0 and 25. After that, the input 14 is synchronized with the information supplied to the information inputs 15, and consequently, to the information inputs of the RAM 27, pulses are applied, which,

5 pass through the multiplexer 23, implement the counting sequence of the counter 26. Code combinations from the output of the counter 26 are fed to the address inputs of the RAM 27. Pulse signals from the input 14 through the delay element 24 entered to organize the required RAM recording time diagram 27 are also fed to the input gating write RAM 27. So

5, after the (n + 1) th cycle of the recording in the RAM 27 of the storing unit {of the receiving unit 17, information about the number of pulses in the series and the order of the series of pulses is entered at the corresponding addresses.

I To transfer the multichannel generator to the second mode, it is necessary to input a single signal at input 13, and zero at input 12. Unit

5, the signal 27 transfers RAM 27 to read mode, through element I 25, opened with a single signal from the inverted output of trigger 22, sets a signal on the reset input of the counter 26 that prohibits switching of the counter 26 by signals received to its account input, and, besides In addition, a single signal from input 13 allows passage through multiplexer 23 to counter 1. After that, the trigger signal from input 1.1 through the OR 2 element is fed to the second input of driver 6, which produces a signal synchronizing with generator 1 pulses, s set input to flip-flop 22. This signal is triggered zapom1nayu1tsy unit 17 in counters 21 vdayuschy ka-in55 catch 8 formation of pulses generated by a series of numbers x and mylcov and code register 10 in order sequencers series. This happens as follows. Zero signal with inverse

the output of the trigger 22 closes the element 25, which removes the reset signal from the corresponding input of the counter 26. The pulses arriving at the counting input of the counter 26 from the output of the multiplexer 23 realize the counting sequence of this counter. Code combinations with counter outputs

26 enter the address inputs of the RAM

27 and, in addition, to the corresponding inputs of the decoder 9. Moreover, each address code on the address inputs of RAM 27 corresponds to a pulse signal

at a certain output of the depshfratora 9, jr with the cash from the output of the former 7 if

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The input to the resolution of the installation of the counter 21 of the corresponding channel 8. At the same time, the information outputs of the RAM 27 contain information recorded in the RAM 27 at this address, which is entered into the corresponding counter 21 by the corresponding signal from the output of the decoder 9. the RAM 27 cells are recorded in the register 10 by the signal from the (n + 1) output of the decoder 25 9. Thus, in the counters 21 of channel 8, information is recorded corresponding to the number of pulses generated by each of the channels 8, and in register 10 is written code, respectively An order of series generated by a multichannel generator. After the completion of the counting sequence, the output of the overflow of the counter 26 produces a pulsed signal that resets the trigger 22. A reset signal is received to the reset input of the counter 26, which sets this counter to its original state and prohibits the switching of this counter. The overflow signal also enters the second input of generator 7, which generates a signal synchronized by pulses from generator 1, which arrives at the first inputs of multiplexers 18 of channel 8. Channel 8.k can be triggered as a signal from the output of generator 7, supplied to the first input of multiplexer 18, and a signal from the overflow output of the counter 21 channel 8.k-1, which is fed to the second input of the multiplexer 18 (channel 8.1 is started on the second input of the multiplexer 18 from the output of the overflow of the counter 21 of channel V.p.). The start signal of the channel 8.k depends on the signal at the corresponding output of the register

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In register 10, only one unit is recorded, the channels are started alternately, and the first channel is started, which corresponds to a single signal at the output of register 10. The signal from the single output of flip-flop 19 opens element 20, through which the counting input of counter 21 and output 16.k devices receive pulses. The number of these pulses corresponds to the code recorded in counter 21. The pulse from the overflow output of counter 21 is fed to the corresponding channel 8.k + 1 input and to the reset input of channel 19 trigger 8.k. After that, the generation of pulses by channel 8.k is stopped, since AND 20 is closed by a zero signal from the direct output of this trigger. During the generation of pulses by the channel 8.k from the inverse output of the trigger 19 to the corresponding input element And 4 receives a zero signal. On the element i 4 output, a single signal is present before the start of any of the channels 8 and after termination of 1 generation by the last of the channels 8.П, since during the generation of any of the channels 8, the corresponding input of the element 4 receives a zero signal,

To transfer the multichannel generator to the third mode, it is necessary to send single signals to the inputs 12 and 13. The operation of the multichannel generator in the third mode is similar to its operation in the second mode. But at the end of the last of the channels 8, the driver 5 by switching a zero signal at the output of the element AND 4 into a single produces a single pulse, which, passing through the open signal from input 12, the element AND 3 and the element OR 2, goes to the second input of the imager 6.

10. If at the output of register 10, connected to the control input of multiplexer 18 of channel 8.k, a single signal, through multiplexer 18, the input from trigger setup 19 receives a signal from the output of driver 7, if the signal is zero, through multiplexer 18 to trigger setting 5 19, a signal is output from the overflow output of channel 8.k-1 counter. Therefore, if only units are recorded in register 10, the start of all channels occurs simultaneously with a signal from the output of imaging unit 7 if

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In register 10, only one unit is recorded, the channels are started alternately, and the first channel is started, which corresponds to a single signal at the output of register 10. The signal from the single output of flip-flop 19 opens element 20, through which the counting input of counter 21 and output 16.k devices receive pulses. The number of these pulses corresponds to the code recorded in counter 21. The pulse from the overflow output of counter 21 is fed to the corresponding channel 8.k + 1 input and to the reset input of channel 19 trigger 8.k. After that, the generation of pulses by channel 8.k is stopped, since AND 20 is closed by a zero signal from the direct output of this trigger. During the generation of pulses by the channel 8.k from the inverse output of the trigger 19 to the corresponding input element And 4 receives a zero signal. On the element i 4 output, a single signal is present before the start of any of the channels 8 and after termination of 1 generation by the last of the channels 8.П, since during the generation of any of the channels 8, the corresponding input of the element 4 receives a zero signal,

To transfer the multichannel generator to the third mode, it is necessary to send single signals to the inputs 12 and 13. The operation of the multichannel generator in the third mode is similar to its operation in the second mode. But at the end of the last of the channels 8, the driver 5 by switching a zero signal at the output of the element AND 4 into a single produces a single pulse, which, passing through the open signal from input 12, the element AND 3 and the element OR 2, goes to the second input of the imager 6.

The multichannel generator is restarted and the pulse train generation cycle is repeated. This occurs until the zero signal from input 12 closes the element I 3,

Claims (2)

1. A multichannel pulse train generator, comprising a clock pulse generator, the output of which is connected to the first inputs of the pulse train generation channels, an OR element, characterized in that, in order to extend the functionality, the first and second elements AND, first, second and the third pulse formers, a decoder, a register, a storage unit, with the output of the clock generator connected to the first inputs of the first and second pulse formers, the first input of the storage unit and the strobe The first input of the decoder, the outputs of the first through (n + 1) th connection with the corresponding second inputs of the channels forming a series of pulses, the last output of the decoder connected to the input of the register, the outputs of which are connected with the corresponding third inputs of the channels forming the series of pulses, the first outputs of which connected to the corresponding inputs of the first element And, the breathing of which through the third pulse shaper is connected to the input of the second element And, the output of which through the element OR is connected to the second input The first pulse generator, the output of which is connected to the second input of the storage unit, the first output of which is connected to the second input of the second pulse generator, the output of which is connected to the fourth inputs of the pulse series forming channels, the second outputs of the memory unit are connected to the corresponding information unit; hb: the inputs of the decoder, the third outputs - with the corresponding information inputs # 1 and the fifth inputs of the channels formed no pulse series, the second output the previous channel of forming a series of pulses - with the sixth input of the subsequent channel of forming a series of pulses, and the second output of the last s of the channel for forming a series of pulses — with the sixth input of the first channel for forming a series of pulses. 2. The generator according to claim 1, characterized in that the channel for generating a series of pulses contains a multiplexer, a trigger, an element, and a counter, the output of the multiplexer being connected to the preset trigger input, the direct output of which is connected 5 with the first input of the element AND, the second input of which is the first input of the channel for forming a series of pulses, the output of the element AND is connected to the counting input of the counter, the output of the overflow 0 which is connected to the trigger setup input and is the second output of the pulse train generation channel, the inverse trigger output is the first output of the shaping channel 5 series of pulses, the resolution input of the counter is the second input of the channel for forming a series of pulses, the address input of the multiplexer is the third input of the channel for forming the series 0 pulses, first and second inputs the multiplexer - the fourth and sixth inputs of the channel for forming a series of pulses, respectively; the information inputs of the counter - by the fifth inputs channel forming a series of pulses.