SU964649A1 - Storage unit interfacing device - Google Patents

Description

(B) DEVICE FOR STRESSING MEMORY BLOCKS

  1 The invention relates to computing technology and can be used in information storage and transmission systems. A device for interfacing memory blocks, which contains a drive, write and read buses connected to the inputs of the write, read and strobe shapers, as well as the delay element is included between the input of the accumulator and the output of the recording strobe t1. A disadvantage of this device is low reliability. The closest to the invention is a device for interfacing memory blocks containing the element NOT three AND elements and the OR element connected via the second AND element to the first AND element, and through the third AND element to one of the gate formers, the read driver and the NOT element The output of which is connected to one of the inputs of the first and second elements AND, the other inputs of which are connected respectively to the outputs of the strobe and recording drivers, the OUTPUTS of the OR element and the first And element connected to the corresponding inputs accumulate 2. A disadvantage of the known device is low speed, since the duration of the write-read cycle is equal to the tripling time to the drive for the execution of a write or read operation, i.e. The speed of the device is three times lower than the speed of the drive. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that the device for interfacing the memory blocks, which contains the recorder signature shaper, read signal shaper, accumulator, AND elements, the first OR element, whose output is connected to the first input of the accumulator, and the inputs are connected to the outputs of the first and second elements And, the first inputs of which are connected respectively to the output of the write signal generator and the output of the read signal generator, the first gating signal generator of which the output is connected to the second inputs of the gating signal. The second element and the accumulator, and the second gating signal generator, the output of which is connected to the second input of the second element AND, triggers, elements NOT, single generators, the second and third elements OR, and elements three through eight are introduced, and outputs The third and fourth elements AND are connected respectively to the inputs of the second element OR, the output of which is connected to the first input of the first trigger, the second input of which is connected to the output of the third element OR, whose inputs are connected respectively to the output The first and six elements I, the first input of the third element I are connected to the input of the recording signal generator, the first input of the seventh element I, the input of the first element NOT and the input of the first generator of single signals whose output is connected to the first input of the fifth element I, output the first element is NOT connected to the input of the second generator of single signals and the first input of the sixth element I, the second input of which is connected to the first input of the eighth element AND and the inputs of the second element NOT, the read signal generator and the transducer Another single signal generator whose output is connected to the second input of the fifth element AND, the second input of the third element AND is connected to the output of the second element NOT and the input of the fourth single signal generator, the outputs of the second and fourth single signal generators are connected respectively to the inputs of the fourth element tl, the outputs of the first trigger are connected respectively to the second inputs of the seventh and eighth elements And, the outputs of which are connected respectively to the inputs of the first and second signal conditioners The second gate input is connected to the first input of the second trigger, the second input of which is connected to the output of the drive, and the output to the first input of the third trigger, the second input of which is connected to the input of the readout signal generator, and the output is the output of the device. FIG. 1 shows the block diagram of the proposed device) in FIG. 2 - time diagrams that show his work. The device contains a shaper 1 of the recording signals, a first shaper 2 gating signals, a first element AND 3 first element OR C, a drive 5 first trigger 6, a shaper 7 read signals, a second shaper 8 adjustment signals, a second 9, third 10 and fourth 11 elements And, the second element OR 12 ,. the fifth 13 and sixth 1 elements AND, the third element OR 15, the second trigger; ep 16, the seventh .17 and eighth 18 elements AND, the first 19 and second 20 single signal generators, the first element NOT 21, the third 22 and fourth 23 single generators signals, the second element is NOT 24 and the third trigger 25. In FIG. 1 denotes a write input 2b and a device read input 27 and a device output 28. FIG. 2 denotes the duration of the input signal on the input signal of the device, the duration of the output signal of the device read input, the duration tp of the write cycle — read, the output delay time ut — of its passage through the first element NOT, the recording duration t ц read reading, time dt of the write cycle delay relative to the beginning of the input signal. The device works as follows. The input signal Tgg (Fig. 2) is fed to the first input of the element And 10 and the input of the former 1. In the absence of a given time signal output fgfj, at the input 27 at the second input of the element 10 there is a resolving potential. In this case, the input signal passes through the OR element 12 and sets the trigger 6 to one state. The signal from the direct output of the trigger 6 permits the passage of the input signal through the element 17 to the input of the imager 2. The input signal triggers the imager 2, the output of which permits the passage of the next recording signal to the input of the accumulator 5.

shaper 1, and switches the drive 5 to the recording mode.

If the output signal comes after the input signal, and the write cycle in drive 5 has not finished (Fig. 2a), the output signal will not go through element I. 14, because the input signal through element 21 will prevent it from passing for a cycle time amp t records After completion of the write cycle, the output signal passes through the AND element I, the OR element 1, and switches the trigger 6 to the zero state. The signal from the three inverse output of the sixth 6 permits the passage of the output signal, through the element 18 to the input of the imaging unit 8. The output signal; launches the imaging unit 8, the output of which permits the readout signal, 5, to the input of the accumulator 5. formed by shaper 7.

In case the output signal arrives before the input signal (Fig. 2.6), the read cycle begins with the arrival of the output signal, and the write cycle is delayed by time (Fig. 2.6 / until the output signal ends, because the output signal through the HE element 2k It prohibits the passage of the input signal through the element 10. If the input and output signals arrive one time (Fig. 2, c), none of them passes through the elements 10 and 14, since their second inputs will have a inhibitory potential. In this case, the outputs of generators 19 and 22, which are triggered by fronts and the input and output signals, respectively, coincide in time and pass through AND 13, the signal from whose output through OR 15 sets the trigger 16 to the zero state, and the read cycle begins. The write cycle will begin after the generators 20 and 23 are triggered which are triggered by the falling edges of the input and output signals, respectively, at the end of the read cycle. The duration iTQ.iy of the signals at the outputs of the generators 19, 20, 22 and 23 is chosen from

 OAN Tr 1

where the delay time when the trigger is turned on or off 6.

In this case, if the input signal comes before the output signal for a time

 The trigger 6 is first set to one state by the input signal, and then to zero by the coincidence signal of the output signals of the generators 19 and 22. In this case, the device works like the simultaneous arrival of the input and output signals, and the write-read cycle time is extended by time 2. But since, this increase can be neglected.

Therefore, at any time ratios between the input and output signals, recording and reading from accumulator 5 will occur, but the output signal of accumulator 5 may be delayed relative to the output signal by xit-i (Fig. 2a). In order to eliminate this disadvantage, the signal from accumulator 5 is entered by the gate strobe into trigger 16 and rewritten into trigger 25 according to the output signal.

The technical and economic advantage of the proposed device is that it provides a faster response than the known one.

Claims (2)

Invention Formula A device for interfacing memory blocks containing a write signal shaper, a read signal shaper, a drive, AND elements, the first OR element whose output is connected to the first drive input, and the inputs to the outputs of the first and second AND elements, the first inputs of which are connected respectively to the output of the write signal shaper and the output of the read signal shaper, the first gating signal shaper, the output of which is connected to the second inputs of the first And element and the storage device, and the second shaper g strobe signals, the output of which is connected to the second input of the second element AND, characterized in that, in order to increase the speed of the device, it contains triggers, elements NOT, generators of single signals, second and third, elements OR, and elements AND from the third and fourth elements And they are connected respectively to the input of the second element OR, the output of which is connected to the first input of the first trigger, the second input of the latter is connected to the output of the third element I W, the inputs of which are connected according to ®1 but to the output terminals and the sixth elements And, the first input of the third element And is connected to the input of the recording signal generator, the first input of the seventh element And, the input of the first element NOT and the input of the first generator of single signals whose output is connected to the first input of the fifth element And, the output of the first This element is NOT connected to the input of the second generator of single signals and the first input of the sixth element AND, the second input of which is connected to the first input of the eighth element Nor to the inputs of the second element NO, the read signal generator and the third g the generator of single signals whose output is connected to the second input of the fifth element I, the second input of the third element I is connected to the output of the second element NOT and the input of the fourth fourth generator of single signals, the outputs of the second and fourth generators of single signals are connected respectively to the inputs of the fourth element I, the outputs of the first trigger are connected, respectively, with the second inputs of the seventh and eighth elements I, the outputs of which are connected respectively to the inputs of the first and second signal drivers of strobir Ani -, the output of the gating signal generator is connected to the first input of the second trigger, the second input of which is connected to the output of the accumulator, and the output to the first input of the third trigger, the second input of which is connected to the input of the read signal generator, and the output of the device. Sources of information taken into account during the examination 1. USSR author's certificate No. 01999, cl. G 06 F 13/02, 1973. 2. Authors certificate of the USSR, cl. G 06 F 13/02, 1978 (prototype).