SU488256A1 - Memory device - Google Patents

Description

one

The invention relates to a technique for recording electrical signals in measuring and computing systems widely used in nuclear physics.

The most common devices for the accumulation of electrical signals, made in the form of multichannel analyzers, include an address register, a synchronization unit, a drive, a generator, an adder, and electrical signal sensors.

The recorded electrical signals arrive at the input of the adder and accumulate in it during specified time intervals using the generator. Each time interval pulse triggers a sync block, which produces three pulses. The first of them records the contents of the adder to the accumulator, the second pulse changes the state of the address register by one, and the third pulse reads the contents of the next address of the accumulator and transfers it to the adder to continue accumulating electrical signals for the next time interval.

Such a device eliminates the possibility of accumulating electrical signals from many sensors. In addition, the use of an adder as an intermediate memory of recorded electrical signals over a long period of time, which can last from seconds to several minutes, depending on the experimenter's requirements, reduces the noise immunity.

devices.

The aim of the invention is to improve the noise immunity of the device.

The goal is achieved by the fact that a coding block and a logical element OR, whose inputs are connected to the outputs of the sensors and the inputs of the coding block, the outputs of which are connected to one input of the address register, are entered into the storage device, the other inputs of this

register connected to the generator output, the output element "OR connected to the input of the synchronization unit.

The drawing shows a block diagram of the proposed device.

The memory device contains sensors of signals 1, a logical element "OR 2, a coding unit 3, an address register 4, a generator 5, a synchronization unit 6 (7 is a reading pulse; 8 is a unit addition pulse), and

also adder 9, drive 10; 11-pulse recording.

The electrical signal from any sensor 1 is fed to the logical element "OR 2 and to the coding unit 3. The outputs of the coding unit are connected to the higher bits

“B address register 4, defining the part of accumulator 10 belonging to this sensor. The time in each channel of the accumulator is set by generator 5, which generates at regular intervals the pulses arriving at the lower-order counting input "and the address register 4. The output of the element" OR 2 starts the synchronization unit 6, which firstly reads 7, which reads the contents of the accumulator 10 at the address specified by the address register 4, and transfers it to adder 9, then nmnul 8 changes the contents of adder 9 to a unit and after that impulse II writes the new contents of adder 9 to NAC device 0. Consequently, the electrical signals from the sensors will accumulate at the corresponding addresses of the accumulator 10 during predetermined time intervals.

The introduction of the coding unit and the logic element OR has allowed the accumulation of signals from many sensors and increased noise immunity of the device. In the present device, the content is stored in the accumulator and only with the arrival of the next electric signal, it is transferred to the adder and stored in it for no more than a duration of a pa .1 ng: cycle, which is usually a single microsecond. Therefore, the likelihood of a content failure: the ator will be determined by the product from:; osh; and: the duration of the memory cycle, the duration of the specified time interval and the intensity of the signals from the sensor. When turning off or changing the supply voltage, the contents of the accumulator, which, as a rule, consists of ferrite cores, remain almost unchanged, while the contents of the adder, which, as a rule, consist of triggers, can take a random value.

Claims (1)

Invention Formula A memory device containing an address register, a synchronization unit, an adder, sensors, a generator and a drive, the first inputs of which are connected to one output of the synchronization unit; the second outputs of the synchronization unit, the outputs of the address register are connected to the third inputs of the storage device, characterized in that. that, in order to improve the noise immunity of the device, it contains a coding block and a logical element "OR, whose inputs are connected to the sensor outputs and inputs to the coding block, whose outputs are connected to one input of the address register, the other inputs of this register element "OR connected to the input of the synchronization unit.