SU924696A1 - Serial-to-parallel code converter - Google Patents

Description

(54) SERIAL CODE CONVERTER

The invention relates to digital computing and can be used in the construction of transducers, the input of the modules of the interface of digital devices with communication channels.

A known converter of a serial code into a parser code containing an input driver, a pulse distributor, a register, a group of elements AND, a trigger and elements AND IJ. .

The disadvantage of this converter is a large amount of equipment and relatively low speed.

The closest in technical essence and circuit construction to the proposed is a serial to parallel converter containing a shift register, a pulse generator and a pulse distributor. In addition, the converter contains a control unit with one stability delay 2.

A disadvantage of the known device is low noise immunity due to the lack of means of protection against a false starting pulse. PARALLEL

control and use in the management of one-stable bolt elements.

The purpose of the invention is to increase the noise immunity of the converter.

The goal is achieved by the fact that a serial to parallel converter containing a shift register, whose information input is connected to

The information input of the converter, the pulse generator and the pulse distributor, the clock input of which is connected to the output of the pulse generator, the clock input of the shift register is connected to the second output of the pulse distributor, the trigger, the AND element, the OR element are turned on, and the pulse distributor is executed in the form of

20 connected counter and decoder, the first, the second, the third and fourth outputs of which are respectively connected to the first input of the element I, with the information input of the shift

25 register, with control set by the output of the converter and with the first input of the element OR., The second input of the element AND is connected to the information input of the converter and the inverse setting input of the trigger, the second.

the third inputs of the OR element are connected respectively to the output of the AND element and the control input of the converter; the output of the OR element is connected to the trigger reset input, the zero output of which is connected to the counter reset input, the clock input of which is connected to the output of the pulse generator ,.

Fig. 1 shows a block diagram of the proposed converter in Fig. 2, a timing diagram of its operation;

The Converter contains a shift register 1, the element And 2, the decoder 3 / counter 4, the generator 5 imgpulsov, trigger 6, the element OR 7, the counter 4 and the decoder 3 together form the distributor 8 pulses.

The converter works as follows

In the initial state, the trigger 6 is in the off state and maintains the counter 4 in the zero state, blocking the counting of the synchronous pulses of the generator 5.

When a starting pulse arrives at the unit input of the trigger 6, the latter is started and enables the counting of the clock pulses from the pulse generator. The state of the counter 4 is decrypted by the decoder 3. After the time interval corresponding to half of the starting parcel, the decoder 3 issues a pulse B (Fig. 2), which arrives at the And 2 element where the presence of the starting parcel is checked. If an impulse noise was taken as a starting parcel, the duration of which does not exceed half the duration of the starting parcel, the AND 2 element generates a signal that, through the OR 7 element, arrives at the zero input of trigger 6 and turns it off. In this case, the counter H4 is blocked and the converter goes into the initial state. If the starting premise is valid, then the above-mentioned switching off of the trigger b does not occur and the counter 4 continues counting the clock pulses. In this case, the decoder 3 generates a series of pulses, the number of which corresponds to the number of information bits and they are located in the middle of the information packet. Each pulse in the shift register shifts the information bits,

At the end of the last information parcel, the decoder 3 generates a pulse 7 (FIG. 2e) strobe the rewriting of parallel data. On the stop parcel the decoder 3 generates a pulse D, which through the OR element 7 enters the zero input of the trigger 6 and turns it off. In this case, counter 4 is blocked and the converter returns to the initial state.

Along with an increase in noise immunity, the proposed transducer provides an increase in the reliability of operation due to the removal of delay elements and the reduction of the shift register size to the number of information bits in

a sign that is significant due to the practice of forming a register of units with a size equal to the size of the sign.

Claims (2)

Invention Formula Serial to parallel converter containing 5 a shift register, the information input of which is connected to the information input of the converter, a pulse generator and a pulse distributor, characterized in that, in order to improve noise immunity, a trigger, an AND element, and an OR element are entered into it, and the pulse distributor is in the form of series-connected the counter and decoder, the first, second, third and fourth outputs of which are connected respectively to the first input of the element I, to the information input of the shift register, to the control output of the transform the body and the first input of the OR element, the second input of the AND element is connected to the information input of the converter and the inverse setting input of the trigger, the second and third inlet 5 DI of the OR element are connected respectively to the output of the AND element and the control input of the converter, the output of the OR element is connected to the reset input of the trigger , zero output P of which is connected to the reset input of the counter, the clock input of which is connected to the output of the pulse generator. Sources of information taken into account in the examination  1, Usoltsev AG, Kislin B.P. Conjugation of discrete channels. zi with a computer. M., Svy, 1973, p. 25, rice 1.8. 2. US patent No. 3946379, 0 published, 1976. & R III l ULJLJLJl l L