SU1270762A1 - Information output device - Google Patents

Abstract

The invention relates to the field of computing and can be used to output data from electronic keyboard computers to external memory blocks. The aim of the invention is to improve the speed of the device. The goal is achieved by introducing into the device the second element AND, the code converter, the pulse distributor, the pulse generator. The code converter contains a NOT element, an encoder, the first and second groups of AND elements and OR elements. The entered blocks allow you to output information from the floating-point representation of numbers that is natural on a keyboard computer, taking into account the fact that the information is dynamically changed, and the sync signals are represented in phase (L pulse code. 1 Cp f files, 3 un.

Description

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The invention relates to computing and can be used to output data from electronic keyboard computers to external memory blocks.

The aim of the invention is to increase speed.

On. FIG. 1 shows a block diagram of the proposed device} in FIG. 2 is a block diagram of a code converter; in fig. 3 - device operation diagrams

The device contains (Fig. 1) microprocessor 1, from which information is output, trigger 2, counter 3, memory block 4, first and second elements OR 5 and 6, generator 7, first and second elements AND 8 and 9, converter 10 code distributor 11 pulses shaper 12 packs of pulses. In addition, the device contains (Fig. 2) the element is NOT 13, the encoder 14, the first and second groups of elements And 15 and 16, the elements of ISH 17

The device for viewing information works as follows.

In the initial state, the counter 3 and the 12 ps pulse generator are blocked by the logical 1 signal, via the bus Output. The output information of the microprocessor 1 appears at its outputs and goes to the converter 10 of the code, and the phase-pulse-coded bit signals of the microprocessor 1 arrive at the inputs of the imaging unit 12 bursts of pulses.

With the arrival of the signal, the Output (Fig. 3a) is unlocked from counter 3, and the driver 12 forms a burst (Fig. 3b), the numbers of which correspond to the number of bits of the output information. Moreover, the first impulse in a pack coincides in phase with the discharge signal corresponding to the younger (senior) discharge of the output information, the second pulse coincides with. the next bit is a dnm signal and so on

In front of him; The front of each pulse from the packet starts the distributor 11 pulses, which produces four pulses shifted relative to each other by one beat of the output frequency of the generator 7 (Fig. A, F, E, W, g). The first of these pulses, the trigger 2 is set to one, the third is reset. To the zero state (Fig. 3L), a

The code converter 10 in the first code produces a comma-code, in the second the converted code of the output information of the microprocessor 1.

The signals (Fig. 3k) arriving at the counting input of counter 3 from the output of the element OR 6 set the address of memory block 4, and the signals (Fig. 3k)

From the AND element, PI 5, information is recorded in the memory block 4. However, writing the combo code is possible only if from the output of the microprocessor 1 to the inputs of the AND 8 elements

and 9 resolution will be received (comma signal). In this case, during the time of the discharge signal, the address of the memory block 4 is changed twice, and the write signal is received twice.

(figs, 3 and k). The first signal records the code, and the second one records information corresponding to this bit signal. At the end of the last pulse

the driver 12 and the signal Output device enters the initial state.

For the device to function normally, the output signal must

be a duration of at least two periods of the frequency of the discharge: signals, otherwise it is possible to output not all bits of information.

The character code is output in the same way as a bit of numeric information. When using a device for outputting such information, the code of which is output in a separate cycle, and the sync signals are represented by a number-pulse code, it is necessary to provide a logical O signal to the inputs of elements 8 and 9. In this case, the code will be output in the same way as do numerical information.

The code Converter 10 (Fig. 2) contains the encoder 14. the element is NOT 13, the first and second group of elements

Claims (2)

Both 15 and 16 and OR elements 17. The encoder 14 is intended to convert the output code of the microprocessor 1. When using K145 series microprocessors, it is necessary to convert the output seven-segment code to a more convenient one for further processing, for example 2/10 code. The encoder in this case can be a combinational circuit that implements the following dependencies: 2 A – E B E G; 2 A F B E; B-F-A E G, A-C; A- In F. G; -De 2 ;, 2, 2, 7. - bits 2/10 of the code; ABEFG - variable segment code. Depending on the signal, trigger 2 arriving at the first inputs of the first group of elements AND 15 and through the element NOT 13 - at the first inputs of the second group AND 16 elements at the output of converter 10, there is a converted code of microprocessor 1, or a comma code It is pre-installed at the second inputs of the first group of elements And 15. The positive effect of introducing into the proposed device new nodes and blocks is the ability to output information from the microprocessors to the external memory blocks with a natural form laziness numbers at which point instruction code appears in the cycle of the corresponding discharge simultaneously with output information, and the information provided in the dynamic form, and clock signals - a pulse position code. Claim 1. An information output device comprising a trigger, a counter memory block, first and second OR elements, a generator and the first AND element whose output is connected to the first input I of the first OR element, the counter outputs are connected to the inputs of the first group of memory block These outputs, which are outputs of the device, the output of the second element OR is connected to the second input of the counter, the second input of the second element OR is connected to the second input of the trigger. characterized in that, in order to increase the speed of the device, a second AND element, a code converter, a pulse distributor, a pulse builder, the group inputs and the input of which are respectively the inputs of the first group and the first input of the device are entered into it, the first counter input is connected to the input shaper pulse generator, the output of which is connected to the first input of the pulse distributor, the first output of which is connected to the first input of the trigger and the second input of the second element And, the first input of which is connected It is the second input of the device, the output of the pulse generator is connected to the second input of the pulse distributor, the second, third and fourth outputs of which are connected respectively to the first input of the first element And, the second input of the trigger and the second input of the first element OR, the output of the latter is connected to the input of the memory unit, the inputs of the second group of which are connected to the outputs of the code converter, the inputs of the group of which are the inputs of the second group of the device, the output of the trigger is connected to the input reobrazovatel code output of the second AND element is connected to a first input of the second OR gate. 2. A device according to claim 1, characterized in that the code converter comprises an encoder, a NOT element, the first and second group of AND elements, OR elements whose outputs are the outputs of a code converter, the encoder inputs and the second inputs of the AND elements of the first group are inputs code converter groups, the input of the element is NOT connected to the first inputs of the AND elements of the first group and is the input of the code converter, the encoder's outputs are connected respectively to the second inputs of the AND elements of the second group, the first inputs of which are connected to the output element NOT, the outputs of the element And the first and second groups are connected respectively to the inputs of the elements OR. R Yu J Phi1.2