SU1277121A1 - Device for exchanging information - Google Patents

Abstract

The invention relates to the field of computing and can be used in control and monitoring systems for the exchange of information between computers and peripheral devices, computers and controlled objects. The aim of the invention is to reduce the hardware costs and increase the speed of the device by simultaneously recording and comparing sequential information. The goal is achieved by the fact that the device containing the transceiver register 3, the trigger 2, the element OR 4, the counter of 1 bits, entered two pulse generators 5.7 pulses and the output register 6. 2 Il. (L

Description

1 - 12 The invention relates to computing and can be implemented in control and monitoring systems for the exchange of information between computers and peripheral devices, computers and controlled objects.

The aim of the invention is to reduce hardware costs and increase the speed of the device by simultaneously recording and reading sequential information.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagram of his work.

The device contains (FIG. I) a 1-bit counter, trigger 2, transceiver register 3, an SHSh 4 element, the first pulse driver 5, the output register 6 and the second pulse generator 7, information output 8 and input 9 of the serial code of the device, synchronizing input 10 and input 11 permitting the operation of the device, information output 12 and input 13 of the parallel device code.

The device works in the following way.

The exchange of information between the computer and the peripheral device takes place under the control of the computer, which generates the UPR signal of access to the peripheral device on input 11 and the SIM synchronization signal on input 10. The UPR and SIM signals are programmed.

When the UPR signal is received from the computer (Fig. 2), the counter 1 is set to the counting mode and the trigger 2 is in the zero state. By the signal from the output of the trigger 2, the register 3 is set to the shift mode. An I / O cycle of one byte of information begins. From the output of the high bit of register 3 in the computer, at output 8, the first bit of the byte recorded in register 3 is received. The first bit of the byte transmitted to the peripheral device enters the serial input of the register 3 of the transceiver to input 9 from the computer. At the time of arrival from the computer of the first sync pulse SIM, there is an increase in unit content of the counter 1. Through the elsgment OR 4, the SIM signal is passed to the sn / d input of register 3, shifted the information stored in register 3, and written to its low-order bit present at the input

0

0

five

five

0 35

40 5 50

21 2

code. At the output of the high bit of register 3, the second bit of the byte arriving at the computer is set, which reads this bit and forms the second SIM pulse. The process then repeats.

Within 8 cycles of the device, one byte, previously recorded in register 3, goes to the computer, and one byte from the computer is written to register 3. During the input process, the counter

1 calculates the sync pulses of the SIM, and the state of the counter 1 changes on the falling edge of the sync pulse. At the end of the eighth pulse, the counter 1 returns to the zero state. At this moment, the driver 5 generates a pulse, arriving 1st at the synchronization input of the output register 6. The contents of register 3 (output from the computer byte) are written to the output register 6

and through the output 12 enters the peripheral device. In addition, the pulse from the output of the imaging unit 5 is supplied to the installation input of the trigger

2 and sets it to one. Trigger 2 translates register 3 into parallel information recording mode. At the time of the removal of the UPR signal, counter 1 is reset, and the shaper 7 generates a pulse arriving through the SHSh 4 element at the synchronous input of the register 3. In the register 3, a new byte is written, which arrives at the checkpoint 13 from the peripheral device. When a new UPR signal appears, the I / O cycle of the next byte of information begins.

Thus, the proposed device simultaneously transmits information in two directions and, therefore, has greater speed. In addition, it is bo-. It is easier to implement because it contains a smaller number of elements and connections.

Claims (3)

1 The invention relates to computing and can be understood in control and monitoring systems for the exchange of information between computers and peripheral devices, computers and controlled objects. The aim of the invention is to reduce hardware costs and increase the speed of the device due to simultaneous recording and reading of sequential information. FIG. 1 shows a functional diagram of the device; see 2 is a temporary chart of his work. The device contains (FIG. I) a 1-bit counter, trigger 2, transceiver register 3, an SHSh 4 element, a first pulse shaper 5, an output register 6, and a second pulse shaper 7, information output 8, and an input 9 of a serial code of a device synchronizing input 10 and input 11 permitting the operation of the device, information output 12 and input 13 of the parallel device code. The device works as follows. The exchange of information between the computer and the peripheral device takes place under the control of the computer, forming the UPR signal of accessing the peripheral device on input 11 and the SIM synchronization signal on input 10. The UPR and SIM signals are generated by software. When the UPR signal arrives from the computer (Fig. 2), the counter 1 is set to the counting mode and the trigger is in the zero state. 2. By a signal from the output of trigger 2, register 3 is set to shift mode. An I / O cycle of one byte of information begins. From the output of the high bit of register 3 in the computer, at output 8, the first bit of the byte recorded in register 3 is received. The first bit of the byte transmitted to the peripheral device enters the serial input of the register 3 transceiver to input 9 from the computer. At the time of arrival of the first sync-pulse SIM from the computer, the unit content of the counter 1 increases by one. Through the ORG signal OR 4, the signal SIM goes to the SnRhro input of register 3, shifts the information stored in register 3 and writes to its lower bit the 1 2 sequential code at the input. At the output of the high bit of register 3, the second bit of the byte arriving at the computer is set, which reads this bit and forms the second SIM pulse. The process then repeats. During 8 operation cycles of the device, one byte, previously recorded in register 3, goes to the computer, and one byte from the computer is written to register 3. During the input process, the counter 1 counts the SIM clock pulses, and the state of the counter 1 changes from the rear sync pulse front. At the end of the eighth pulse, the counter 1 returns to the zero state. At this moment, the driver 5 generates a pulse, arriving 1st at the synchronization input of the output register 6. The contents of register 3 (output from the computer byte) is written to the output register 6 and through output 12 goes to the peripheral device. In addition, the impulse from the output of the imaging unit 5 is fed to the setup input of the trigger 2 and sets it in the unit state. Trigger 2 translates register 3 into parallel information recording mode. At the moment of removal of the signal, the SPD will reset the counter 1, and the former 7 will generate a pulse arriving through the SHSh 4 element to the synchronous input of the register 3. Register 3 is written to the new byte, arriving on code 13 from the peripheral device. When a new UPR signal appears, the I / O cycle of the next byte of information begins. Thus, the proposed device simultaneously transmits information in two directions and, therefore, has greater speed. In addition, it is bo-. It is easier to implement because it contains a smaller number of elements and connections. Claims The device for information exchange contains a transceiver register, the information input of the parallel code of which is the information input of the parallel code of the device, and the information input and output of the serial code are respectively the information input and output of the serial code of the device312 a trigger, an OR element and a bit counter, the sync input of which is connected to the synchronization input of the device, characterized in that, in order to reduce the hardware costs of the device, two pulse drivers and an output register are entered into it, the output of the output register being the output of the device parallel code , information input Connected to the information output of the parallel transceiver register code, and the synchronous input - to the trigger installation input and through the first form 21 worldizer and pulse with the output of the bit counter, the reset input of which is connected to the trigger sync input, device operation enable input and through the second pulse shaper to the first input of the OR element, output connected to the sync input of the transceiver register, and the second input to the synchronizing input of the device, mode control input the transceiver register is connected to the trigger output, the information input of which is connected to the zero potential bus of the power source. cfyue.Z