SU1504652A1 - Queue orering device - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in service scheduling devices. The aim of the invention is to improve the reliability of the device by eliminating the loss of requests with a duration shorter than the cycle time of the device reading. The device for queuing contains two registers of information storage and a shift register, two groups of AND elements, a group of delay elements, a pulse distributor, a trigger, an OR element, a pulse shaper, a counter, and a switch. In the device, by using the shift register to control the switch, the device outputs the required priority code from the counter, and the use of a group of delay elements and the connection of the trigger inputs to the device inputs allows processing requests of any duration, and the short-term single interference is prevented. 1 il.

Description

The invention relates to automation and computing and can be used in service order control devices.

The purpose of the invention is to increase the reliability of the device by eliminating the loss of requests with a duration shorter than the reading cycle of the device,

The drawing shows a diagram of the device.

The device contains the first register 1, with triggers 2, the second and third registers 3 and 4, the first group of elements AND 5, the second group of elements AND 6, delay elements 7, pulse distributor 8, element OR 9, trigger 10, counter P, switch 12 pulse generator 13, a group of request inputs 14 of the device, a group of information outputs 15 of the device, installation input 16 of the device and input 17 of the device.

The device works as follows

In the initial state, registers 3 and 4, trigger 10 and counter L1 are reset. The zeroing is performed by a single pulse at the input 16 of the device. Register I bits are zeroed automatically through delay elements 7. Back

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service requests are received at the device inputs 14, fixed in the triggers 2 of register 1, and through the elements of AND 5 the corresponding bits of the register 3 are set to one. The priority of requests increases with increasing request sequence number. Elements 5 and 5 prevent triggering of register 3 when short-term unit interference appears at inputs 14, Interference is considered to be a signal whose duration is less than trigger 2, the Interference will set one of triggers 2 to 1, but after a time determined by the value of the delay element, trigger 2 will return to the initial state. Since the trigger 10 is reset, then the register 4 and the counter 11 are in the mode of waiting for the parallel reception of information specified by the unit from the inverse output of the trigger 10. On the clock input 17 Twa read pulses arrive. Consider one tact reading device. On the leading edge of the read pulse, the pulse distributor 8 is started. The pulse from its first output through the element OR 9 goes to the clock inputs of register 4 and counter 11. On the leading edge of this pulse, the contents of register 3 are written to register 4, and zero is entered into counter 11. If a request of the highest priority is recorded in register 4, then the unit from the N-ro output of the register 4 opens the switch 12 and the highest priority code enters the outputs 15 of the device from the counter 11, then the pulse from the second output of the pulse distributor 8 is set to one trigger 10, the signal c the inverse output of which translates register 4 into the information shift mode ,. and counter II is in counting mode. In addition, the driver 13 generates a single impulse, which passes through the elements of AND 6 and resets only those bits of register 3, of which one is copied to register 4. The next N pulses coming through the OR 9 element from the outputs of the pulse distributor 8 sequentially shift the information in register 4 and add one to the contents of counter 11. If in the iM bit of register 4 there was one, then the outputs 15 of the device from counter 11 through the switch 12 i-ro request code will be issued. The register 4 will be reset to zero after the end of each read cycle, the (N + 3) -M pulse from the output of the pulse distributor 8 trigger 10 is set to zero.

The following reading cycles occur similarly.

Claims (1)

Invention Formula A queuing device containing the first register, the first group of N elements AND (where N is the number of request inputs of the device, the first delay element, the pulse distributor, the OR element and the counter, with the first input of each i-ro AND element of the first group (i 1 , N) is connected to the i-th query input of the device, the second input of the i-ro element And the first group is connected to the output of the i-ro bit of the first register, characterized in that, in order to increase the reliability of the device by eliminating the loss of requests with duration shorter the read cycle of the device, N-1 delay elements, the second and third registers, the second group of N elements AND, the trigger, driver, pulses, and the switch, with the i-th clock input of the first register connected to the iM request the device input, the i-th information input of the first register is connected to the device power bus, the i-th zero input through the i-th delay element is connected to the output of the i-th bit of the first register, the output of the i-i element of the first group is connected to the single input i-ro bit of the second register, zero input i- ro of the bit of which is connected to the output of the i-ro element AND the second group, the output of the i-ro bit of the second register is connected to the iM information input of the third register, the output of the i-ro bit of which is connected to the first input of the i-ro element AND of the second group, the output of the N-ro bit of the third register is connected to the control input of the switch, the second inputs of all elements of the second group are combined and connected to the output of the pulse generator, the input of which is connected to the inverse output of the trigger and the recording control inputs of the third register and counter, switch output The device is an output of the device, the information input of the switch is connected to the output of the counter, the counting input of which is connected to the clock input of the third register and the output of the OR element, the first input of which is connected to the first output of the pulse distributor, the second output of which is connected to the single input of the trigger the third to (H + 2) -th pulse pulses are connected respectively to the inputs of the OR element from the second to (H + 1) -th (Y + 3) -th output of the distributor 46526 the pulses are connected to the zero input of the trigger, the synchronizing input of the trigger and the second register, and the set inputs of the counter and the third register are connected to the setup input of the device, the trigger input of the pulse distributor is the input of the device, the information inputs of the counter and trigger, information inputs of all The bits of the second register and the serial input of the third register are connected to the logical zero bus of the device.