SU1723349A1 - Spark advance timer - Google Patents

Abstract

The invention relates to the field of engine construction, in particular, to devices for discrete control of the ignition time of an internal combustion engine. The aim of the invention is to improve the accuracy of determining the advance angle of ignition. The goal is achieved by introducing a synchro generator 8, a code converter 9, a buffer register 10, a D-flip-flop 11 and functional connections, which ensures the formation of an arbitrary function of the ignition angle. 2 Il.

Description

The invention relates to the field of engine construction, in particular, to discrete control devices for the ignition timing of an internal combustion engine.

The aim of the invention is to improve the accuracy of determining the advance angle of ignition.

Figure 1 shows the functional diagram of the device; Fig. 2 shows a timing diagram of its operation, the voltage at the outputs: a — the first element I, b — the second element C, and c — the third element I, g — the first output of the sync pulse generator; d - the second output of the sync pulse generator; e - output Loan counter, w - output of the inverse trigger.

The controller contains a one-shot 1, the first element And 2, the inverter 3, the second element And 4, the third element And 5. the clock generator 6, the reversible counter 7, the shaper 8 clock pulses, the Converter 9 codes, the buffer register 10. D-tritger 11.

The input of the regulator is connected to the input of the one-shot 1, the first input of the first

element And 2, the second input of the first element And 2 is connected to the output of the one-shot 1. The output of the first element And 2 is connected to the first input of the second element And 4, the inverter 3 and the input of the driver 8 sync pulses.

The output of the inverter 3 is connected to the first input of the third element And 5. The output of the clock generator 6 is connected to the second inputs of the second and third elements And 4.5. The summing input of the counter 7 is connected to the output of the second element 4, the subtracting input of the counter 7 is connected to the output of the third element 5. The first output of the driver 8 sync pulses is connected to the synchronous input of the buffer register 10. the second output of the forma- tor 8 is connected to the reversing synchronous leads counter 7 and D-flip-flop I. The group of information outputs of counter 7 is connected to the inputs of the converter 9, the outputs of which are connected to the information inputs of the buffer register 10, the group of information outputs of which are connected to information inputs Dami reversible counter 7.

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The output of the meter 7 is connected to the S-input of the D-flip-flop 11, the inverse output of which is connected to the third input of the third element And 5. The direct output of the D-flip-flop is the regulator output. The information input of the D-flip-flop is connected to the logic level O, the R-inputs of the counter 7 and the D-flip-flop 11 are connected to the initial setup bus (not shown).

The purpose of the regulator elements is the following. The one-vibrator 1 and the first element I 2 are designed to generate a pulse, the duration of which is equal to the difference of the durations of the pulse arriving at the controller input from the sensor output (not shown), and the pulse at the output of the single vibrator 1. The clock oscillator 6 serves to generate counting pulses for counter 7. Element AND 4 serves for valveing the summing pulses arriving at the input of counter 7 during the action of the pulse from the output of the first element AND 2. Inverter 3 and third element And 5 serve for valveing pulse-deducting s, arriving at the input of the counter 7 during the absence of a pulse from the output of the element II. Counter 7 serves to sum and subtract the pulses arriving at its corresponding inputs. The code converter 9 serves to convert the code at the output of counter-7 to the required updated code, which is adequate to the exact value of the time interval and the corresponding ignition advance angle. The buffer register 10 serves to temporarily store the code from the output of the converter 9 until it is parallel rewritten through the information inputs to the counter D-flip-flop 11 to generate an interval of subtracting pulses and a signal to the ignition system.

The device works as follows.

The signal from the output of the sensor (not shown), whose operation depends on the frequency of rotation, is fed to the input of the one-shot 1 and the first input of the first element AND 2. The pulse from the output of the one-shot 1 is fed to the second input of the first element AND 2, at the output of which a pulse is generated whose duration is determined by the difference in the pulse durations at the output of the sensor and the pulse at the output of one-vibrator RE1. The pulse-shaped pulse (see Fig. 2a) is fed to the input of the inverter 3, the first input of the second element I 4 and the inverting input form Vatel 8 clock. As a result, the output of the second element And 4 impulses

generator b to the summing input of the reversible counter 7. This is followed by a direct counting by the reversing counter 7 for the duration of the pulse from the output

element 2. The number of counted pulses from the output of the counter 7 in the form of a binary code is fed to the input of the converter 9, where the required optimal code of the ignition advance angle is formed at the corresponding frequency of rotation of the engine shaft. At i the end of the pulse from the output of the element I 2, the shaper of 8 clock pulses is started, at the first output of which a pulse TI1 is formed (Fig. 2, d), and

5 at the second output - impulse TI 2 (figure 2, d). On the first clock pulse ТИ1, the code from the output of the converter 9 is overwritten into the buffer register 10. On the second clock pulse ТИ2, the converted code

0 is overwritten with the output of the buffer register 10 in parallel along the information inputs to the reversible counter 7.

In the initial state, the D-flip-flop 11 is set at the input R to the zero state,

5, therefore, from the inverse output of the D-flip-flop 11 to the third input of the third element And 5, a single level arrives. At the end of the pulse from the output of the first element And 2. from the output of the third element And 5 do

0 pulses (Fig. 2, c) to the subtracting input of the reversible counter 7. There is a subtraction of the previously recorded code of the number in the counter 7 until its output does not receive a pulse (Fig. 2, e) about zero zero counter 7. By a pulse from the output of the Loan of the counter 7, the trigger 11 is set to one (FIG. 2, g). At the same time, the positive difference of the front () of the signal from the output of the D-flip-flop 11 takes place directly in control of the ignition system (for example, electronic thyristor or transistor). In addition, the zero-level signal from the inverse output of the trigger 11 prohibits by the third input of the third element And 5 the flow of counting pulses to the counter 7.

Claims (1)

Invention Formula Advanced Angle Torch 0 for an internal combustion engine, containing a single vibrator, first, second and third elements And, an inverter, a clock generator, a reversible counter, a regulator input connected to the input of a single vibrator 5 and the first input of the first element And the second input of the first element And connected to the output of the one-shot, the output of the first element And connected to the first input of the second element And the input of the inverter, the output of the last connected to the first input the third element And, the output of which is connected to the subtracting input of the reversible counter, the summing input of which is connected to the output of the second element And, the second inputs of the second and third elements And are connected to the output of the clock generator, characterized in that, in order to improve the accuracy of determining the ignition time, driver of clock pulses, code converter, buffer register, D-flip-flop, with the output of the first element I connected to the input of the driver of clock pulses, the first output of which is connected to the synchronous input m buffer register, and the second output with synchronous reversible counter inputs and D0 five trigger, the group of information outputs of the reversible counter is connected to the inputs of the code converter, the outputs of which are connected to the information inputs of the buffer register, the group of information outputs of which are connected to the information inputs of the reversible counter, the output of the Loan is connected to the S-input of the p-flip-flop, the inverse output of which is connected to the third input of the third element And, the direct output of the D-flip-flop is the output of the controller, the information input of the D-flip-flop is connected to the level of the logical OYR-inputs reversing The counter and D-flip-flop are connected to the initial installation bus. 1 FIG. 2