SU720507A1 - Buffer memory - Google Patents

Description

(54) BUFFER STORAGE DEVICE

The proposed drive can be used as a buffer device and discrete communication systems, in particular in the transmitter and receiver of the telegraph apparatus, as well as as an operational locking device.

Known drives telegraph code combinations, where the device contains a drive on the shift registers for N bits and a counter with a coefficient of count equal to N. The outputs of the bits of the counter are connected to the inputs of the element I, from the output of which a signal is received that controls the recording and reading of information into the drive. For the addressing, the phase indication of the address is used, gtrice.m when recording the next character, the phase of the counter changes by one step under the influence of the signals of the generator of single pulses 1.

A similar phase indication of the representation of addresses is used in the storage of telegraph code combinations, where the drive is made in the form of -shift shift registers, where "/ C is the number of bits

In the CODE combination, and N is the number of stored code combinations 2.

The input information cables are connected via switch to the inputs of the corresponding registers. Next address; -completed combination is stored in the counting record with a counting factor equal to Y, the outputs of which bits are connected to the Kj inputs of the first element AND, the output of which is connected to the control inputs of the relay, the output of this second element AND is connected to the installation the signal trigger flusher accumulates & t, another trigger trigger input is connected to the read bus.

Another input is the second element. And it is connected to the output of the third element I, whose inputs are connected to the output of the read counter bits, with a counting factor equal to N.

In the readout counter, the accounts of the account are stored: L x code combinations.

Claims (2)

The phase of the write and read counters is altered by the action of single pulses fed through the write and read buses. A disadvantage of such devices is their dynamic mode of operation. This significantly increases power consumption compared with a static mode of operation or when working with a high duty cycle, which is typical for operation, for example; in the telegraph apparatus. The purpose of the invention is to reduce the power consumption due to the transition from continuous drive operation to start-stop operation with high duty cycle. This is achieved by the fact that the device contains two OR elements, an inverter and a pulse generator that has one of the inputs connected to the write bus, another input; To a clock bus, one of the outputs of the pulse generator is connected to the input of the first OR element and the second And, and the output of the first element OR is connected to the clock input of a sequential type memory block, another output of the pulse generator is connected to the input of the second OR element and through the inverter to the input of the second element AND, the other inputs of the first and a second OR elementon connected to the read bus. The scheme of the proposed device is shown in the drawing, where a block of memory 1 of a sequential type is indicated, elements 2, 3 OR, elements 4, 5 AND, inverter 6, trigger 7, shaper 8 bursts of pulses, a counter of 9 numbers, input 10 and output 11 coding tires , clock bus 12, write bus 13, read bus 14. The memory block can be built on static shift registers for the purpose of circulation and information controlled switches at the inputs of shift registers or on static random access memory devices whose address inputs are connected to the outputs of the address counter. Suppose that the memory block is made on four-bit shift registers (it 4). The work of the proposed drive is as follows. After the initial installation signal, the counter of 9 numbers, which in this case consists of two bits, and the trigger are reset, for example, zero. In this case, the element 5 And is triggered and the control signal is fed to the recording input of the block 1 of the memory. In this case, the information inputs of the shift registers are connected to the input code bus 10, and the circuit is broken. Simultaneously with the information on the tires 10, the “record” signal is received on the recording bus 13. In this case, the shaper of 8 bursts of pulses is triggered, and at one output a bundle of four pulses () appears, and at the other output a bundle of three pulses appears simultaneously. Under the influence of four pulses arriving at the clock input of the registers of the memory block through the element 2 OR information is recorded in the first bits of the registers and is advanced further to the final, fourth bit. A pack of three pulses is fed to the clock input of the counter 9 numbers. Due to the fact that the counting coefficient of the counter is equal in this case to 4 ((4), the phase of the counter will lag one step away from the phase of the memory block determined by the place of the first recorded information. Element 4 AND will not work, since the moment the signal from element 5I is present, both signals are present from the outputs of the pulse generator, but in antiphase. Thus, the alternate recording and reading signals allow the device to sequentially write and read information into the accumulator. melts only when writing (microchip pulses) and reading (one clock pulse), which reduces power consumption compared to drives operating in a continuous dynamic mode. Another advantage of this drive is the ability to analyze the first combination immediately after recording it into the accumulator, since it appears at the output of the memory block immediately after the write cycle. Invention A buffer storage device containing a sequential-type memory block, information inputs to the outputs They are connected respectively to the input and output codewords, the number counter, the outputs of which are connected to the corresponding inputs of the first element I, the output of which is connected to the control input of the memory unit of the sequential type and the input of the second element I, whose output is connected to the same setup input of the trigger, another installation input of which is connected to the read bus, and a clock bus, characterized in that, in order to reduce the power consumption of the device, it contains two elements OR, an inverter) and a formate s bursts, one input of which is connected to schine recording, the other input - to a clock bus, one of the outputs of the pulse generator are connected to the input of the first element OR and the input of the second element AND, and the output of the first element OR is connected to the clock input of the memory unit of a sequential type, another output of the generator of the pulse package is connected to the input of the second element OR And, the other inputs of the first and second elements OR are connected to the read bus. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 493805, cl. G 11. From 7/00, 1974. 2 .. USSR author's certificate number 557504, cl. H 04 L 13/08, 1974 (prototype).