SU1336074A1 - Information receiving device - Google Patents

Abstract

The invention relates to the reception and transmission of information and can be used to receive information in binary code in systems with a large number of transmitters operating in a common communication channel. The purpose of the invention is to increase the reliability of reception. The information in the sequential code is fed to the informational inputs of the shift register 4 and the memory block 19. The location of the executive bits of the information in the information bytes is predetermined. The pulse generator 25 triggers the clock 24. At the output of the pulse former 9, a pulse is formed, the duration of which is equal to the duration of the waveform. In memory block 19, information from the output of counter 1 is recorded. The number of units counted from the outputs of counter 27 is compared with a predetermined threshold number using the setting inputs of the comparison unit 26. If the threshold number is exceeded, a signal from the output of the comparison unit 26 is fed to the control input of the register 28. From the outputs of the register 28, the corresponding control signals are transmitted to the actuators. 1 il. i (L 00 00 Oi about 4:

Description

The invention relates to the field of reception and transmission of information and can be used to receive information in a two-way code in systems with a large number of transmitters operating in a common communication channel.

The purpose of the invention is to increase the reliability of reception.

The drawing shows a block diagram of a device being offered for receiving information.

The device contains counters 1 and 2, the element NOT 3, the shift register 4, the decoder 5, the block 6 of the actuating elements, the 7, the decoder 8, the pulse former 9 pulses, the element OR 10, the AND-NOT element 11, the decoder 12, the elements NOT 13 and 14, switch 15, element 16, counter 17, pulse shaper 18, memory block 19, decoder 20, OR element 21, pulse shapers 22 and 23, clock 24, pulse generator 25, comparison block 6, counter 27, register 28.

The pulse shaper 9 is made on the counter. Shapers 18, 22 and 23 pulses contain counters, items are NOT

The device works as follows.

The information in the sequential code enters the information input of device B in the form of identical codegrams, one after the other. The first byte in each codogram is a marker code, which is not repeated in other information bytes, and corresponds to the beginning of the codogram. Each information byte of a codogram contains information that can be divided into two groups; information bits and performance bits. Information bits affect, for example, display elements, which themselves are not sensitive to rare interference and single failure. Executive bits affect actuators that should not be triggered by single faults. The location of these bits in the information bytes is set in advance. The logical values of these bits (0,1) are determined by the sources that these bits form, for example, sensors for voltages, temperatures, pressures, and other similar parameters. In the case, for example, if the indicated parameters exceed the critical values, the missing bits of information receive the value of logical ones and should be communicated to the actuators with maximum confidence.

After starting the pulse generator 25, the chroniser 24 is turned on, at the output of which control pulses are formed. The codogram bits successively arrive at the information input of the shift register 4, the information input of the memory block 19.

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The clock input of the shift register 4 is supplied with clock pulses accompanying each bit of information. Descrambler 5 decodes the code of the codogram marker after its accumulation in shift register 4 and generates a signal that wraps the total number of bits of counter 7 and counter 17 of the execution bits, thereby providing the beginning of the count of the incoming information bits in the codogram. In addition, the signal at the input of the imaging unit 9 pulses. The latter is made on the counter, which counts two pulses corresponding to the arrival of the marker from the output of the decipheror 5 in. the time of the zero half-cycle of the control signal of the chroniser 24. Thus, at the output of the pulse generator 9 a pulse is formed, the duration of which is equal to the duration of one waveform (from one marker to the next) and fed to the input of the AND-NOT element 11. During the arrival of the bit of the soundgram, the counter 7 counts their number and generates at its outputs codes of the number of bits that are decoded by decipher 8. The latter is designed so that it decodes only the numbers of the executive bits of the waveform, the reception accuracy of which It must be high. The signals corresponding to these bits from the outputs of the decoder 8 through the element OR 10 are fed to the input of the element AND-HE 11, which is opened by the clock pulses of the tracking information bits.

At times when the element AND-NOT 11 is closed, there is a high level of voltage at its output. At the same time, the “Record / read” of the memory block 19 is set to record information, the counter 1 of the codogram review is set to zero, the outputs of the switch 15 are connected to the outputs of counter 2 by control signals from the outputs of the AND-11 elements and NOT 14. Counter 17 operates from the front of the output signal AND-NOT 11 and records the number of execution bits allocated by the decoder 8, i.e. at its outputs, normalized addresses of the executive bits of information are formed, which saves the capacity of the memory block 19. At the same time, along the positive edge of the output signal of the NANDI element 11, the pulse shaper 18 generates a pulse, which through the OR element 21 is fed to the pulse shaper 22. From the output of the imaging unit 22, a pulse is fed through the element NOT 13 to the control input of the memory unit 19 and the value of the execution bit is written to the memory unit 19. In the same way, the other executive bits recorded from the codogram by the decoder 8 are recorded. In addition, a pulse from the output of the pulse former 22 is fed to the input of the pulse former 23, which forms a narrow pulse on the falling edge of the input signal and zeroes the counter 27. The NE-NE 11 produces a low voltage level at its output, while the counter 1 is turned on to the pulses from the output of the clock 24, the outputs of the switch 15 are switched from the outputs of the counter 2 to the outputs of the counter 1, At the output of the "Write / Read memory block 19", the information reading mode is activated.

Counter 1 counts up to the number determined by decoder 12, and this number corresponds to the number of codograms counted by counter 2, i.e. equal to the capacity of counter 2. Counter 17 at this time is set to the current address of the executive bit. High-frequency pulses from the output of the chroniser 24 are fed to the input of an AND 16 element, which is prepared for opening by signals from the outputs of the HE 3 and 14 elements. Pulses from the output of an AND 16 element through the OR 21 element are fed to the input of the pulse former 22, which generates pulses for addressing the block 19 memory. Thus, at the address of this bit, all the values of these bits are viewed in all codograms arriving at a given time. The number of units read at the output of memory block 19 is counted by a counter 27. This number from the outputs of counter 27 is compared with a predetermined threshold number using block 26 of comparison. If the threshold number is exceeded, the signal from the output of the comparator unit 26 is fed to the control input of the register 28. Signals corresponding to the allocated bits are sent to the information inputs of the latter from the outputs of the decryptor 20, which decodes the state of the counter 17 execution bits. From the outputs of register 28, the corresponding signals are provided to the inputs of the actuator unit.

The device provides a selection from the incoming information of bits intended for bringing to the actuators, storing the logical values of these bits and periodically reading and summing the values for repeatedly repeated codograms, comparing the received sums with a predetermined threshold value and, depending on the result of the comparison - issuing information to the executive items. This increases the reliability of the received information from an external source of codograms, eliminates the reception of bits that have changed their value under the influence of interference, accidental failures, reduces the accident response of actuators, ensures the reliability and safety of their work.

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Claims (1)

Invention Formula A device for receiving information containing a block of actuators, the first, second and third counters, the outputs of the first counter are connected to the corresponding inputs of the first decoder, a pulse generator, the first element OR, the AND-NOT element whose output is connected 0 with the input of the zero setting of the second counter, the first pulse shaper, differing in that, in order to increase the reliability of reception, a shift register, a comparison block, a switch, a chronizer register, a second, third and fourth pulse shapers, a second, third and the fourth decoders, the second element OR, the first, second and third elements are NOT, the output of the pulse generator is connected to the input of the clock, the first output of which is connected to the clock input of the third counter and the first input of the first pulse shaper , the second output is with the first input of the second pulse generator, the third output is with the first inputs of the third and fourth pulse formers,  element And with the clock input of the second counter, the outputs of which are connected to the corresponding first information inputs of the switch and the inputs of the second decoder, the output of which is connected 0 with the inverse counting input of the second counter and through the first element is NOT connected to the second input of the AND element, the information input of the shift register is combined with the information input of the memory block and is the first input of the device, the clock input of the shift register is combined with the clock input of the fourth counter and the first input of the element is the second input of the device, the outputs of the shift register are connected to the corresponding inputs of the third decoder, the output of which is connected to the inputs of setting the first and fourth counters the second input of the first pulse generator, the outputs of the fourth counter are connected to the corresponding inputs of the fourth de5 encoder, the outputs of which are connected to the corresponding inputs of the first OR element, the output of which is connected to the second input of the NAND element, the output of which is connected to the second input of the fourth pulse shaper, the counting input per0 0 first control inputs the memory unit and the switch and through the second element NOT to the third input of the element I and to the second control input of the switch, the second information inputs of the second are connected to the corresponding outputs of the third counter, the outputs to the corresponding first address inputs of the memory block, the second address inputs which are connected to the corresponding the outputs of the first counter, the output of the element And is connected to the first input of the second element OR, the second input of which is connected to the output of the fourth pulse generator, the output - to the second input of the third pulse generator, the output of which is connected to the second input of the second pulse driver and through the third element NOT the second control input of the memory unit, the output of which is connected to the first input of the fifth counter, the second input of which is connected to the output of the second pulse shaper, the outputs to the corresponding first inputs and a comparison unit, the second inputs of which are the installation inputs of the device, the outputs of the first descrambler are connected to the corresponding information inputs of the register, the control input of which is connected to the output of the comparison unit, outputs - with the corresponding inputs of the block of executive elements.