RU1811019C - Device for cycle synchronization - Google Patents

Abstract

The invention relates to multichannel telecommunications and can be used in digital information transmission systems. The purpose of the invention is to increase noise immunity. The device contains a shift register 1, a sync group decoder 2, an OR 3 element, an AND 4 element, an OR 5 element, a sync group distortion decoder 6, a synchronization hold control unit 7, a first element NO 8, a drive 9 for synchronism output, an And 10 element , generator equipment block 11, element AND 12, element OR 13, drive 14 at the input to the synchronism, element NO 15, trigger 16, element 17. frequency divider 18. The device allows you to change the functioning algorithm of the loop holding circuit depending on the number of symbol errors in the sync group. This provides a significant increase in the average drive filling time for the exit from synchronism upon exposure to errors in the transmission path, which. in turn, leads to increased noise immunity of the device. 2 s. P. f-ly, 3 ill.

Description

Cuettaj group

. &

about

The invention relates to multichannel telecommunications and can be used in digital information transmission systems.

The purpose of the invention is to increase noise immunity.

In FIG. 1 is a block diagram of an apparatus for synchronizing in cycles; in FIG. 2 - a sync group distortion decoder; in FIG. 3 is a synchrocheck circuit control unit.

The device for synchronizing in cycles contains a shift register 1, a sync group decoder 2, a first element OR 3, a first element AND 4, a second element OR 5, a sync group distortion decoder 6, a synchronization hold control unit 7, a first element NO 8, a drive 9 by exit from synchronism, the second element And 10, the block 11 of the generator equipment, the third element And 12, the third element OR 13, the drive 14 at the entrance to the synchronism, the second element NO 15, trigger 16, the fourth element And 17, the frequency divider 18; the sync group distortion decoder 6 includes a sync group analyzer 19, a counter 20, a first delay unit 21, a distortion store 22, an element 23, a trigger 24, a second delay unit 25; the synchronization hold circuit control unit 7 comprises a first element NO 26, a first AND element 27, an OR element 28, a NOT element 29, a second NO element 30, a second And element 31, a trigger 32.

A device for synchronizing in cycles operates as follows.

The group digital signal is fed to the input of the n-element shift register 1 (n is the number of characters in the sync group). Each combination of symbols, similar in structure to the sync group, causes the formation of a signal at the output of the decoder 2 of the sync group. If the device is in a state of synchronism, then the signal from the output of the decoder 2 through the OR 13 element coincides at the input of the And 4 element with the signal from the output of the generator equipment block 11. From the output of the And 4 element, a drive reset signal is generated to exit out of synchronism 9. As a result, this drive is discharged to the zero state, at which the installation signal of the generator equipment unit 11 cannot be generated at the output of the And 10 element.

At the same time, the group digital signal is fed to the first input of the decoder 6 distortions of the sync group. In this case, signals at its output are generated as follows. If there are errors in mi in the sync group, then there are no signals at the first and second outputs of the decoder 6 distortions; if errors

mi rn2, a signal is generated at the first output; if m m2 errors, a signal is generated at the first and second outputs of the decoder 6.

Responses to the result of the analysis of the number of distortions in the sync group are received at the first and second inputs of the synchronism retention circuit control unit 7. The signals at its output are formed as follows:

- with m mi errors in the sync group (there are no signals at the first and second inputs of block 7), signals coinciding in time with the signal from the output of the generator equipment block 11 are generated at the first and second outputs of the control block 7;

- with mi m m2 errors in the sync group (the presence of a signal at the first input of block 7 and no signal at the second) at the first output of control unit 7, there is no signal if the drive 9 is completely empty upon exit from synchronism, and a signal is generated that coincides with the signal from unit 11 of the generator equipment, if at least one unit is recorded in the drive 9 after exiting synchronism, while there is no signal at the second output of the control unit 7;

- with m 1P2 errors in the sync group

(the presence of a signal at the first and second inputs of block 7) there is no signal at the first and second outputs of block 7.

Thus, in the state of synchronism in the absence of distortion in the sync group at the first and second outputs of the distortion decoder 6, there are no signals. At the first and second outputs of the synchronism retention circuit control unit 7, signals are generated that match

in time with a signal at the output of the generator equipment block 11. As a result, there is no signal at the output of the element NO 8, and writing to the drive 9 after the exit from synchronism. In turn, the signal from the output of the AND 4 element through the OR 3 element keeps the drive 9 in the zero state.

In the synchronism search circuit, the signal from the output of the sync decoder 2 coincides in time with the signal from the output of the frequency divider 8, the division coefficient of which is equal to the division coefficient of the generator equipment block 11. In this case, the signals from the output of the element And 12 through

the OR element 5 holds the drive 14 at the entrance to the synchronism in the filled state.

In case of distortion of the sync group due to the influence of noise in the linear path, the synchronization hold circuit is activated. The order of filling of the drive 9 for the exit from synchronism corresponds to the algorithm described above. The group digital signal is fed to the first input of the decoder 6 distortion of the sync group. This decoder determines the number of distorted characters in the sync group.

The decoder 6 distortions of the sync group works as follows. The signal from the generator equipment unit 1.1, which determines the frequency of the transmission cycles, is fed to the third input of the distortion decoder 6. Taking into account that this signal determines the beginning of each transmission cycle (or coincides with the last symbol of the sync group), in delay block 25 it is due to a delay of Nn clock cycles (where N is the total number of characters in the transmission cycle; n is the number of characters in the sync group) -. is in accordance with the time when the first symbol of the sync group is received in the analyzer 19. Therefore, at the output of the delay unit 25, a sequence of signals is generated that follows the frequency of the transmission cycles and determines the position of the first sync symbol in these cycles. The signal from the output of the delay unit 25 sets the trigger 24 to the state corresponding to a single signal at its output. As a result, the And 23 element is open. Clock pulses supplied to the second input of the sync group distortion decoder 6 pass through the open element AND 23 to the input of the counter 20. The counter 20 has n outputs and works as follows. Each clock pulse supplied to the input of the counter 20 corresponds to a signal that appears sequentially on the first, second,; ...., nth output of this counter. In the analyzer 19 symbols of the sync group, at the moment a signal appears from the first output of the counter 20, the analysis of the first symbol of the sync group occurs. If the symbol is not distorted, there is no signal at the output of the analyzer 19; if it is distorted, then from the output of the analyzer 19, the signal is recorded in the distortion storage device 22, calculated on a unit of cells. Next, the second, third, ... are analyzed; nth pulse of the synchro group. At the time of analysis of the last symbol of the sync group, the signal from the pth output of counter 20 is fed to the second input of trigger 24 and sets

there is zero potential at its output. As a result, the supply of clock pulses through the element And 23 to the input of the counter 20 is stopped. The sync symbol analyzer 8 is turned off from operation until the first symbol of the next sync group arrives. Thus, by the end of the analysis of the synchroperge symbols in the accumulator 22 of distortions, the number of cells corresponding to the number of distorted characters in the synchro-group will be filled. In addition, as described above, if there are errors in the sync group m n (filled with + 1 cell), then the first output of the distortion storage device 22 is a constant unit. If there are errors in Chapter 2 (filled in TP2 + 1 cell), a constant single signal appears at the second output of drive 22. As a result, at the time of the signal from the generator equipment unit 11, which determines the position of the last symbol of the sync group, to the third input of the synchronization hold control circuit unit 7 at its first and second inputs, signals are received that determine the degree of distortion of the sync group according to the algorithm presented above. The distortion accumulator 22 is reset by a signal from the generator equipment unit 11, which is delayed in the delay unit 21 by one clock cycle, i.e., after the control signals are generated at the outputs of the synchronization hold control unit 7. The same signal from block 11 is delayed in block 25 by N-n clock cycles and includes a counter 20 and analyzer 19 to analyze the next sync group.

The cyclic holding circuit control unit 7 operates as follows. In the state of synchronism, as was shown above, the drive is 9 times out of synchronism. Trigger Z3 is in a state in which its potential is zero potential. Therefore, the element And 31 is closed, the element And 27 is open. As a result, the second input of the control unit is turned off from operation. At the initial occurrence of distortions in the sync group, two results of the analysis of the symbols of the sync group are possible :;

Claims (3)

1. m: Ј mi errors were detected in the sync group. In this case, the distortion accumulator 22 of the decoder b of the synchro group distortions is filled with less than less than G + cell. Therefore, at the first output of the distortion decoder 6, the signal is absent. At the time of receipt of the signal from the generator equipment block 11, a signal is generated at the output of the NO 26 element, which through the open AND element 27 and the OR element 28 the element NO 8 hits the input, the signal coincides, but it is absent at the second output, time with a similar signal from the block; therefore, at the output of the element NO 26, the signal 11. At the output of element NO 8, the signal is absent, absent, and at the output of element NO 30 is present, therefore, writing to the drive 9 will produce a signal which, through the opening out of synchronism, is not carried out. The fifth element And 31 and the element OR 28 is at the same time the signal from the output of the element falls on the element NO 8. As a result, NO 26 is supplied to the second output of block 7; the output of element NO 8 is a recording signal in drive and through the element of the IL of the drive is fed 9 to exit the synchronism is not at the first input. element And 4, a match is formed. Moreover, since the second time with a signal from the block 11 of the generator 10 output of the control unit 7 (output element Total equipment at the second entrance. In re-NO26) there is no signal, resetting the result of the output of the element And 4tel 9 to exit synchronism to zero a signal is generated which does not occur through the electronic state. He saves OR OR.3i is applied to the Reset input to its previous state. fed 9 at the exit from synchronism, 15Ya. When detected in the sync group keeping it in the zero state, and a signal is generated on the basis of errors the fourth input of the control / shadow block 7 by the chainper, and also on the second outputs of the decryption-retention of cyclic synchronism, 6 distortion deletion. Therefore, at the outputs of the elective drive, trigger 3 is in a state in which there are no signals 26, 30. AT at its output - zero potential. 20result in the first and second outputs of the blo; , 2. In the sync group, an rh control mic 7 is detected; no signals are generated, errors. In this case, the drive 22 is-; which leads to the formation of a signal on the bottom of the decoder and the distortion is full. The output of the element is NO 8, which is written + 1 or go more cells. Therefore, it is transferred to the drive 9 after exiting the synchronized output of the decoder 6 of the distortion 25mA, increasing the degree of its filling. When a signal is generated that arrives at this, taking into account the absence of a signal to the second input of element NO 26 of block 7 by the upstream output of control unit 7, an equalization signal is generated. As a result, an output element of the drive element 9 is generated. NO 26. at the time of receipt on his second- 3., When a signal input from the block 11 of the generator circuit is detected in the synchro group for 30mi: Ј nrii errors at the first and second outputs of the ore, there is no signal. In their very own distortion decoder 6, there are no signals; at the outputs of the elements I 27 and I 31 they wave. Therefore, at the outputs of the NO elements of the control unit 7, a signal also non-26.30 of the control unit 7 is generated. Therefore, on the first and second outputs, the first of which goes to the second Dahblok 7 at the time of the signal from the 35th output of this block and through the OR element of the generator equipment 11-zero-3- to the input of the And 4 element, coincides in time battle potential. This leads to the fact that the signal from the block 11 of the generator output of the element And 4 signal, which is through the equipment. At the output of AND element 4, the FORCE element holds the drive 9, a signal is emitted which, through the BUikb element y from synchronism in the zero state, 40 OR 3 resets drive 9 at the output yy, is not formed, but at the output of the element from synchronism to zero state. In NO, a signal is generated, which is filled in with its Queue, the signal from the output of the element only the first cell of the storage device 9 at the output NO, through the open element And 31 and the synchronism. At the same time, the signal OR 28 is sent to the input of the element element NO 8; it arrives at the fifth 45 NO 8, providing a ban on writing to storage; ЩЩЩ control unit 7. This signal is a measurer 9 to exit synchronism. Simultaneously triggers 32, setting the signal to reset the output from the Yang element elra, a single signal is output. Therefore, OR 5 enters the fourth input of the 7th storage block 7 into the drive 9 after the control is out of control, returning the trigger 32 to the synchronism outcome of the first unit, the And element 27 is the 50ripe state. The hold circuit is thus turned off 10; it starts from work, since at its second time, it returns to the state of the first input (output of the element HE 29) - constant synchronism Eo. ynny zero potential. When filling the drive 9 at the exit; ; ; In the future, when partially filled, out of synchronism, at its output, the generated signal barely 9 leaves the synchronism 55etc resolution signal, which 9, its filling is carried out as follows — it arrives at the first input of AND element 10. In the following way:. In this case, the synchronism search circuit, consisting of 1, upon detection in the sync group of the elements AND 12.17, element NO 15, yy rn. S m2 of errors at the first output of the element OR 5, trigger 16, drive distortion decoder 6 is formed 14 at the input of synchronism and divider 18 frequency, is included in the operation at the first absence of a sync group. If the cyclic synchronization fails, the drives 9.14 at the exit from the synchronism and at the entrance to the synchronism are full, and the signal from the output of the frequency divider 18 through the open element And 10 sets the generator equipment block 11 to a new state. At the same time, the same signal through the OR element 3 resets the drive 9 at the exit from synchronism to the zero state and sets the trigger 32 to the initial state, at which the zero potential is at its output. SUMMARY OF THE INVENTION 1. A device for synchronizing in cycles, comprising a shift register in series, the input of which is an input of a group signal, and a sync group decoder, as well as the first, second, third and fourth AND elements, the first and second OR elements, the first and second NO elements, a drive at the exit from synchronism, a drive at the entrance to synchronism, a frequency divider, a trigger and a block of generator equipment, the first input of which is connected to the first input of the frequency divider and is the input of the clock frequency three, and to the second input of the generator equipment block and the first input of the first OR element, the output of the second AND element is connected, the output of the drive is connected to the first input of the output from synchronism, the reset input of which is connected to the output of the first OR element, to the second input of which the output of the first element And, while the output of the sync decoder is connected to the first inputs of the second element NO, the third and fourth elements AND, and the outputs of the third element And and the second element NO are connected to the first input m, respectively, of the second OR element and a trigger, the output of which is connected to the second input of the fourth AND element, the output of which is connected to the second inputs of the trigger, the second OR element and frequency divider, the output of which is connected to the second inputs of the third AND element and the second NO element and to the third input the second AND element, and the output of the second OR element is connected to the drive input at the synchronism input, the output of which is connected to the second input of the second AND element, while the output of the generator equipment block is connected to the second input I will give the first AND element and the first NO element, the output of which is connected to the drive input for synchronism recovery, which means that, in order to increase the noise immunity, a sync group distortion decoder, a synchronism retention circuit control unit and a third OR element are introduced, the first and second inputs of which the output of the sync group decoder and the second output of the synchronism retention circuit control unit are connected, the first output of which is connected to the first input of the first element NO, and the output of the third 0 OR element is connected to the first input of the first AND element, while the input; the group signal of the device is connected to the first input of the distortion decoder, the second input of which is the input of the clock frequency of the device, and the first and second outputs of the distortion decoder of the sync group are connected respectively to the first and second inputs of the synchronization hold control unit, to the third, fourth, and fifth the inputs of which are connected respectively the outputs of the generator equipment block, the first OR element and the first element NO, and the output of the generator equipment block 5 is connected to the third input of the sync group distortion decoder. 2. The device according to claim 1, with the proviso that the sync group distortion decoder is made in the form of a sync group analyzer, counter, AND element, trigger, first and second delay blocks and a distortion storage device, the first and the second output of which are, respectively, the first and second outputs of the decoder of the distortion synchro group, the first and second inputs of which are the input of the synchro group analyzer and the second input of the I element, the output of which is connected to the counter input, whose outputs are connected to the control inputs I will give a synchro group analyzer, while the input of the first delay unit is connected to the input of the second delay unit and is the third input of the decoder, and the outputs of the first and second delay units are connected respectively to the Reset input of the distortion storage device and the first input of the trigger, the output of which is connected to the first input of the element And, a p-output is connected to the second trigger input 0 counter, and the output of the synchro group analyzer is connected to the input of the distortion storage device. 3. The device pop. 1, characterized in that the block of control of the hold-5 synchronism circuit is made in the form of the first and second elements NO, the first and second elements AND, the element NOT, the OR element and the trigger, the output of which is connected to the first input of the second element And element NOT - to the first input of the first element AND, to the second input of which the output of the first element NO is connected, the first input of which and the first input of the second element NO are respectively the first and second inputs of the control unit, the third input of which is the second input of the first about the element NO connected to the second input of the second element NO, the output of which is connected to the second input GroupWar 26 / g the second AND element, the output of which and the output of the first AND element are connected to the inputs of the OR element, the output of which and the output of the first NO element are respectively the first and second outputs of the control unit, the fourth and fifth inputs of which are the second and first inputs of the trigger, respectively. Figure 2