SU1377911A1 - Storage device for telegraph apparatus - Google Patents

Abstract

The invention relates to computer technology, in particular to storage devices, and can be used in telegraph technology, in the systems for preparing, transmitting and displaying alphanumeric information. The aim of the invention is to increase the reliability of the device. The device contains an input register of 1 number, a block of 2 memory, an output register of 3 numbers, information outputs 4 and inputs 5, a counter 6 of the address with a counting input of the device's address 8, a driver 9 of single pulses. owls, counter 12 of reference signals, elements 7, 10, 13-15, 26, 29, 31, 32, 38, 39, control block 16, triggers 25, 34, 35, elements IL 11, 27, 30, 36, delay element 33 and elements NOT 2B, 40, 41. Reliability of the device operation is achieved by ensuring that the information recorded in block 2 is protected from accidental and erroneous actions of the operator by eliminating the possibility of overlap after (L

Description

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This is achieved by automatically setting the address for recording new information when switching from the output mode, stopped by the Text section to the recording mode. The address from which the recording of a new information message can be started is recorded as a difference of state 11

The scientific research institute of the outputs of counters 6 and 12. A new message can be recorded either after the initial setup signal at input 19, or when two output signals of the logical zero appear at the output of register 3 after the input information input signal arrives at input 20. 1 hp lts, 3 ill.

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The invention relates to computing technology, namely, storage devices, and can be used in telegraph technology, systems for transmitting, preparing and displaying alphanumeric information.

The aim of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 and FIG. 3 shows functional diagrams of embodiments of a control unit and a single pulse generator, respectively.

The proposed device contains (FIG. 1) an input register 1 numbers, a memory block 2, an output register 3 numbers, information outputs 4, information inputs 5, an address counter 6, the first element AND 7, an inversion input 8, a single pulse former 9, a second element 10, the first element 11, the counter 12 of the reference signals, the third 13, the fourth 14 and five elements 15, the control unit 16, the start input 17 of the read mode input 18 stop the device, the input 19 of the initial installation in the recording mode, the input 20 signal availability of input information, the second clock input 2 1, the read permission input 22 of the next information mark, the input 23 of the signal for forming the code splitting code.

FIG. 1 denotes the third start input 24 and the second reset input 24 of the driver 9 single, pulses.

The device also contains the first trigger 25, the sixth element And 26, the second element SHP1 27, the first element

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NO 28, seventh element AND 29, third element SHSh 30, eighth 31 and ninth 32 elements AND, delay element 33, second 34 and third 35 triggers, fourth element OR 36, output 37 of information input resolution, ten 38 and eleven 39 elements And, the second 40. and the third 41 elements NOT and indicator output 42.

The control unit 16 (.Fig. 2) contains the pulse shaper 43, the first trigger 44, the first 45 and the second 46 elements AND, the first element OR 47, the second trigger 48, the third element AND 49, the third trigger 50, the second element OR 51, the fourth element AND 52, third element OR 53, fourth trigger 54, fifth element AND 55, fourth element OR 56, sixth element AND 57, first differentiating element 58, fifth element OR 59, fifth trigger 60, seventh element AND 61, .- first delay element 62, eighth element AND 63, sixth element OR 64, ninth element AND 65, seventh element OR 66, second the second delay element 67 and the second differential switch 1) the neutralizing element 68. The shaper 9 of single pulses contains (FIG. 3) trigger 69, element OR 70, differentiating element 71, trigger 72, element And 73, counting trigger 74, differentiating elements 75, 76, the element OR 77, the triggers 78, 79, the elements AND 80 and the differentiating element 81.

The proposed device works as follows.

When a signal arrives at input 19 (Fig. 1), the initial state of the device is set to the recording mode. Under the influence of the signal at input 19 at the second output of the block. 16 a signal appears allowing the passage through the AND 14 element of the recording signals to the input of the block 2, and the third output of the block 16 - the signal blocking the passage of the control signals of the register 3 through the AND 15 element. At the same time, the operation of the AND 38 elements is blocked , And 39. As a result, the output of the element And 39 is constantly present signal O, indicating the absence of information at the outputs 4. The signal, which occurred at the fourth output of block 16, resets the counters 6 and 12, which are below impulse input 8 continuously and synchronously switch. At the same time, the initial setup signal from input 19 switches the trigger 25 to a state that allows clock pulses from input 8 to pass through element AND 26 to input of element OR 27 from whose output the pulses go to input of unit 2. As a result, unit 2 is reset. all addresses.

Upon completion of writing the code 00 ... 0 at the last address of block 2 and when the pulse ends at the output of the element OR 27, the element AND 7 is triggered, the trigger 25 returns to the initial state and the pulses from input 8 through AND 26 will stop. From this point on, the output of the SHS 27 element is an O signal, which for block 2 is a read signal, and for register 1 after the NE element 28, a write signal. This completes the installation of the device in the initial state, in which it remains until the start of recording information.

When recording information on inputs 5, the code of the information sign is received, and on input 20 - the sync signal of the logical unit. Availability of input information

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gister 1. Since block 16 is already set in recording mode, the signal received at its input from input 20 will confirm the recording mode and the output state of block 16 remains unchanged.

When a signal arrives at the input 20 of the imager 9, the enable signal for the element 14 is excited at its third output. As a result,

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The cash, which appeared at the output of the element And 13, when the counter 12 occupies the zero state, through the element And 14 and the element OR 27 enters the input of the block 2 and records the information stored in the register 1 in it. the bit of block 2 is recorded 1. At the end of the signal at the output of the element And 13, the driver 9 generates a single subtraction signal at the first output, which prohibits the passage of a single pulse through the element 10 from a sequence of pulses input through input 8 to the input of the counter 12. phase counter 12 otst is one step of the phase counter 6. The output driver 9 to AND gate 14, a blocking signal is supplied. Simultaneously with the recording of information in block 2, the signal from the output of the element 14 is fed to output 37 to synchronize the input of information into the memory (for example, from a keyboard, not shown in Fig. 1).

The code combination of the next character at inputs 5 and the signal accompanying it at input 20 can appear only after the termination of the signal at output 37, i.e. after the end of the record in block 2 of the previous character. At the end of the signal at output 37 at the write input of block 2, the reading potential (O) is set, and the write potential (1) is set at the control input of register 1. Therefore, as soon as the inputs of the 5 and 20 through the Vits, respectively, code combination of the next character and the accompanying signal 1, they will be recorded in register 1.

When the following signal arrives at input 20 from register 1, the code of the second character and 1 will be recorded in block 2 at the second address.

When writing each block to block 2, the signal 1 is written to the additional bit of block 2. After the signal at the output of the element 13 ends, the driver 9 again removes the resolution signal from the element 14 and again generates a signal on the first output that prevents the passage through the element 10 one more clock pulse to the input of the counter 12, the phase state of which will lag one more step away from the phase state of the counter 6. The recording of the next telegram signs is similar. After

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the last n-th digit of the telegram is written to the additional bit of block 2 at address n + 1, a text separation indicator is entered, which is a signal O, for which a pulse signal is fed to input 23 from the Text section key (not shown in Fig. 1) by which the driver 9 generates a signal that prevents the passage of another clock pulse through the AND 10 element to the input of the counter 12, which from this moment will be lagging n + 1 step away from the counter 6, i.e. the phase difference between counters 12 and 6 will store the current address, equal to n + 2 (the equality of the phases of counters 6 and 12 corresponds to the first current address).

Thus, the first character of the next telegram is written at address n + 2, and at address n + 1, block 2 stores the code 00 ... O. In this case, O in the additional bit of block 2 is in this case an indication of the separation of the text and indicates the end of the previous message. Further recording of information occurs as described.

To output information from the device, an output is given to input 17, starting the read mode from block 2, where block 16 blocks the operation of element 14, initiates operation of the driver 9 and sets counters 6 and 12 to the same initial state. As a result, at the fourth output of the imaging unit 9, a signal appears that permits the operation of the element 15. At the control input of the unit 2, the read signal and information stored therein constantly appear at its outputs, with each signal 8 inlet, switching m. counter 6. Element I 13, decoding the initial state of counter 12, outputs a signal through element 15 and element OR 30 to the control input of register 3, according to which the information sign read from block 2 is written to register 3 and output to outputs 4. In this case, from the additional bit of block 2, the additional bit of register 3 records signal 1, which, after the information has been written to register 3, enters output 42, signaling the presence of the first character code at outputs 4. On windows

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When the signal at the output of the element And 13 shaper 9 removes the enabling signal from the input element And 15, and the signal from the first output prevents the passage of one pulse from the sequence of clock pulses jHa input 8 through the element 10 at the input of the counter 12. In this case, the counter 12 is behind by one step from counter 6,

If there is a signal at output 42, a code is read from outputs 4. After reading, a sync signal is input to input 22, according to which shaper 9 with a signal from its fourth output again enables operation of element 15 and, through element 41, blocks operation of element 39 and stops the signal output 42. The device is ready to output the next sign; When the continuously operating counter 12 once again occupies the initial zero state, the next information sign from the outputs of block 2 (similar to that described) will be written to register 3. When reading and displaying the division of text text, writing it into register 3 and changing the phase of counter 6 by one step is the same as when displaying information characters, but code 00 ... from block 2. O and the zero signal from the output of the extra bit of register 3 blocks the operation of element I 39, at output 42 of which the signal O is stored, indicating that there is no information on the outputs 4. As a result, the input 22 does not receive a signal that triggers the operation of the imaging unit 9.

Thus, on the sign of the division of the text information output will be stopped. In this case, the current address in the form of the phase difference of the counters 6 and 12 corresponds to the address of the first character of the next information message (telegram), in this case, the address n + 2 (n is the address of the last information sign of the output message). To output the next message, the operator must again give a signal to input 17. All subsequent messages are output in the same way as described. The device provides for the protection of information stored in block 2 from accidental and erroneous actions of the operator by eliminating the imposition of subsequent messages on previously recorded ones, as well as providing automatic

setting the start address of a new message when moving from reading and outputting to writing an informational message.

If the operator has mistakenly started entering in block 2 a new information message, when previous messages have not yet been removed from block 2, then the sign code from inputs 5 and signal 1 from input 20 are recorded in register 1. At the same time, a signal is set at the third output of driver 9 element 14 is operation. However, element 14 operation is blocked by a signal from the second output of block 16, which analyzes the device’s previous mode of operation at each pulse at input 20. Since in this case, block 16 establishes that the arrival of a pulse at input 20 was preceded by the output of information, which was stopped by the text division sign, blocking signals are stored on the second and third outputs of block 16, prohibiting the recording of information in block 2 and output information from the device. By the signal from the fourth output, the block 16 sets the counters 6 and 12 to the zero state. At the same time, the signal from the first output of block 16 sets the trigger 35 to a state in which the signal from its inverse output blocks the passage of 10 pulses from the input 8 to the input of the counter 12. The latter remains in the zero state until the lock is removed from the element And 10. At the same time, the signal from the direct output of the trigger 35 permits the passage of pulses from the input 8 through the element 29. As a result, with each clock cycle of the signals at the input 8, synchronously with the switching off of the counter 6, the information from block 2 is read into register 3, starting from the first address sa. In this case, the readout of information from the outputs 4 is not performed, / since the AND 39 element is blocked by the signal from the second output of the block 16 and the signals 1 from the additional register bit 3 to the output 42 do not pass, and the output 42 O. is kept permanently. In this case, with each signal 1 of the additional register bit 3, trigger-34 is set to a position in which the direct drive signal blocks AND 32, and vice versa, each O signal corresponding to the text division sign, recorded in dopol

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the low bit of register 3, through the element NOT 40, the element AND 31 and the delay element 33 sets the trigger 34 to the state permitting the operation of the element 32.

The presence of the delay element 33 ensures the installation of the trigger 34 in a state allowing the signals from the output of the element 31 to pass through the element 32, after the end of the pulse at the output of the element 31, and therefore the signal at the output of the element 32 appears when at the output of the element 31 there appear at least two consecutive pulses successively one after the other. The first sets the trigger 34 to the state that permits operation of the And 32 element, and the second pulse passes through the And 32 element, while the trigger 34 is in the permission state. The appearance of two pulses in succession at the output of the And 31 only is possible when the last message (telegram) is output from block 2, because only after it in the additional bit of block 2 at all subsequent addresses is the O recorded earlier when the block 2 is zeroed .

At the output of element 32, a signal appears indicating that the current address at a given moment corresponds to the address from which the next message can be written to block 2, because no information was recorded at all subsequent addresses, which is indicated by the absence of an additional The resolution of block 2 of signal 1. The current address is equal to the address of the Mth sign recorded in block 2 last, incremented by two, i.e. M + 2, since after the output of the Mth sign. Ett; e took two steps to derive two zero signals. The output signal of the element 32 and the trigger 35 is set to the initial state. In this case, firstly, the lock is removed from the AND 10 element and the counter 12 from this moment can again switch synchronously with the counter 6. Thus, the address from which the new message can be started is fixed as a phase difference ka 6 which is continuously switched, and the counter 12, which up to this point has been in the zero state. Secondly, the trigger 35 from this

moment blocks the passage of pulses through the element And 29, which stops the recording of information from block 2 to register 3; thirdly, when trigger 35 is switched by a signal from an output of an element 32, block 16 sets the recording mode, since from its second output a permit signal arrives at the input of element 14, the second input of which already has an enable signal from the third output of the driver 9 as a result of a signal arriving at input 20. As soon as a signal appears at the output of AND 13, it passes through AND 14, enters the input of block 2 and writes to it at the address M + 2 information stored until this point in register 1, and at M + 1 zap syvaets mark the separation of the text.

Thus, the address from which the recording of new information can be started after the output of the sign is stopped by separating the text is automatically set when the first signal arrives at input 20, while the search for the address does not exceed one count cycle of counter 6. Due to this, the distortion information stored in block 2, due to the imposition of subsequent information on the wound recorded, which increases the reliability of the device.

Using inputs 24 i for editing and the stop signal at input 18 allows for the correction of the information recorded in block 2.

Claims (2)

1. A supplementing device for a telegraph apparatus containing an input number register, a memory block, an output number register, a single pulse shaper, a call signal counter, a control unit, the first AND element, the first to fifth And elements, and an address counter, the count input which is a device access input, whose information inputs are the information inputs of the group of the input number register, the outputs of the group of which are connected to the information inputs of the group of the memory block, the outputs of the group of which The values are for the information inputs of the GROUP of the output number register, the outputs of the group of which are inst. 0 about 0 five the formational outputs of the device, the outputs of the address counter are connected to the address inputs of the memory block and the inputs of the group of the first element I, the counting input of the address counter is connected to the first input of the second element I, the second input of which is connected to the first output of the single pulse generator, the second output of which is connected to the first input of the first element OR, the second input of which is connected to the output of the second element AND, and the output of the first element OR to the counting input of the signal counter, the outputs of which are connected to the input A group of the third element I, the output of which is connected to the first inputs of the fourth and fifth elements I, the second inputs of which are connected respectively to the third and fourth outputs of the single pulse generator, the first start input of which is connected to the input of the recording confirmation signal of the control unit and is the signal input the presence of input information of the device, the clock input of which is the synchronization input of the single pulse generator, the second start input and the first reset input of which is the corresponding On the read permission input of the next information mark and the input signal of forming the text separation code of the device, respectively, the third start input and the second reset input of the single pulse generator are the edit inputs of the device information text, the first start input of the read mode and the stop input of the control unit are respectively the start input the read mode and the stop input of the device, the entry of the initial setup to the write mode of the device is the first input of the write mode of the block control, characterized in that, in order to increase the reliability of the device, the first to the third triggers are introduced into it, the first to the third elements are NOT, the sixth to the eleventh elements are AND, the second to the fourth elements are OR, the delay element and the additional bit each register of a number, with the installation of the installation of the first trigger connected to the first input of the recording mode of the control unit, the first input of the recording mode lock of which is connected to the first element AND and the reset input of the first trigger, the direct output of which is connected to the first input of the sixth element AND, the output of which is connected to the first input of the second OR element, the output of which is connected to the write-read input of the memory unit and the input of the first element NOT; the output of which is connected to the control input of the input number register and the input of the first element And, the second input of the sixth element And is connected to the counting input of the address counter, the input of the third element And and the first input of the seventh element And, the output of which is connected to the first The third input OR, the output of which is connected to the control input of the output number register and the first input of the eighth AND element, whose output is connected to the first input of the ninth AND element and the input of the delay element, the output of which is connected to the installation input of the second triggers, the output of which is connected to the second input of the ninth element I, the output of which is connected to the reset input of the third trigger and the recording mode input of the next information sign of the control unit, the first input of which is connected to the setup input the third flip-flop, the direct output of which is connected to the second input of the seventh And element, the inverse output of the third flip-flop is connected to the second input of the second And element, and the recording resolution enable input of the control unit, the second output of which is connected to the third input of the fourth And element, the output of which is connected to the second the input of the third OR element and the first input of the fourth SHS element, the second input of which is connected to the output of the fifth AND element, the second input of the third OR element and the second input of the recording mode of the control unit, t th output of which is connected to the third start input of the single pulse shaper, the third input of the fifth element AND, the first input of the tenth and eleventh AND elements, the second inputs of which are connected respectively to the -OUTPUT of the second element NOT, the second input of the eighth element NOT whose input is connected to the fourth output of the single pulse generator, the third reset input of which is connected to the output of the fourth ele . i. jg 5 20 25 Q. ds 50 five the OR input and the second input of the write mode of the control unit, whose input lock input input is connected to the output of the tenth AND element, the first start input of the single pulse generator is connected to the additional bit of the input number register, the output of the additional bit is connected to the additional information the input of the memory block whose auxiliary output is connected to the input of the additional bit of the output register of the number, the output of the additional bit of which is connected to the input of a reset second flip-flop, a second input of the NOR .odinnadtsatogo and third input AND gate whose output is the output of the indicator, and the fourth output element is the output resolution information of the input device. 2. The device according to claim 1, characterized in that the control unit comprises a pulse shaper, first-to-five triggers, first-to-ninth elements AND, first to seventh elements OR, first and second differentiating elements, first and second delay elements, the input of the start of the reading mode of the block is the input of the pulse generator, the first output of which is connected to the installation input of the first trigger and the first input of the first differentiating element, the output of which is connected to the reset input of the third trigger, inverse to the course of which is connected to the first inputs of the first and fifth elements AND, the outputs of which are connected respectively to the first and second inputs of the fourth element OR, the third input of which is connected to the input of the first delay element and the output of the second element AND, the first inputs of the first and second elements AND are connected to the second output of the pulse former and the first input The first element OR, the output of which is connected to the installation input of the second trigger, the direct output of which is connected to the first input of the third element AND, the second inputs of which, the third input of the first element AND and the first input of the sixth element AND are connected to the direct output of the fourth trigger, installation input which is connected to the output of the third element OR, the first the input of which is connected to the output of the fourth element AND, the first input of which is connected to the direct output of the third trigger and the first input of the second OR element, the output of which is connected to the reset input of the first trigger, the direct output of which is connected to the reset input of the fourth trigger and the first input of the ninth of the AND element, the second input and output of which are connected respectively to the output of the sixth OR element, to the first input of the seventh OR element and the setup input of the fifth trigger, the inverse output of which is connected to the first input of the fifth element And, the second input of which is connected to the inverse output of the fourth trigger, the direct output of the fifth trigger is connected to the second input of the second element And and the first input of the seventh element And, the output of which is connected to the second input of the third element And, the third input of which is connected to you code of the second differentiating element, the reset input of the second trigger is connected to the output of the sixth element AND the output of the seventh element AND is connected to the input of the second delay element, the output of which is connected to the second input of the second element OR, o d of the first delay element connected to the first input of the fifth element Hilti, whose output is connected to the reset input of the fifth flip-flop, third flip-flop set input is the input of the stop, the second input of the first differentiating element, second r t emlxl Q 5 0 5 0 five the inputs of the first and fifth OR elements, the third input of the second OR element, and the fourth inputs of the third and fourth OR elements are combined and are the first input of the block recording mode, the second input of the sixth AND element and the first input of the eighth AND element are combined and are the first input blocking the block record, the third input of the fifth element And, the second inputs of the fourth and seventh elements AND are combined and are the input of the block record confirmation signal, the first input and output of the sixth element OR are connected respectively to the output of the eighth elec And the second input of the ninth element AND, the second input of the sixth element OR is the recording mode input of the next block information sign, the input of the second differentiating element is the enable input of the block recording mode, the third input of the first differentiating element is the second input of the block recording mode, the third input of the sixth And element and the second input of the eighth And element are combined and are the second input of the block write mode lock; the second input of the seventh SH) element is the input of the read mode lock the block, the outputs of the fifth and third elements of AND are the respective first and second outputs of the block, the direct output of the first trigger and the output of the fourth OR element are respectively the third and fourth outputs of the block. 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