SU1599851A1 - Data input device - Google Patents

Abstract

The invention relates to the field of automation, in particular to the automated workplace of the employee of the passport office, and can be used in the construction of an automated population accounting system. The purpose of the invention is to improve the reliability of the device. The device contains synchronizer 1, counters 2.14, data format selector 3, memory block 4, registers 5.8, address selector 7, comparators 6.9, triggers 10, 11, elements OR 12.13 elements group 15, element delays 16, element AND 17. The goal is achieved by operatively monitoring the collection and entry of data of specified formats, which is ensured by the introduction of the data format selector of the first and second comparators, the second OR element, the second trigger and the reversible counter. 4 il.

Description

ten

15

The invention relates to an automated anti-crash system, in particular to an automated workstation of an employee of the passport office, and can be used in constructing an automated public accounting system.

The purpose of the invention is to increase the reliability of the device by operatively monitoring the collection and entry of data in predetermined formats.

Figure 1 presents the block diagram of the device; figure 2 shows an example of a specific constructive implementation of the synchronizer; fig.Z - the same, the data format selector; in FIG. A -. the same as the address selector.

The device (figure 1) contains the synchronizer 1, the counter 2 addresses, se- :: ;; Lecturer 3 data format, memory block 4, first register 5, first comparator 6, address selector 7, second register 8, second comparator 9, first 10 and second 11 triggers, first 12 and second 13 elements OR, reversible counter 14, a group of elements 15, element 16 of delay and element 17 I. Figure 1 also shows the synchronizing 18 and informational 19 inputs of the register 8, which are the second group of inputs, the signal inputs 20-22 of block 7, which are the second group of inputs, as well as the first 23, second 24, third 25 and fourth 26 information outlets.,

20

25

35

40

The synchronizer G (Fig.2) contains a generator 27 clock pulses, trig. ger 28, the first element of I.29, the element of OR 30, the second element of AND 31, the first 32, the second 33 and the third 34 delay elements

Figure 2 also shows the inputs 35, 36 of the synchronizer and its outputs 37-39

The pulse from the output of the element OR 30, the delayed element 33 for the response time of the counter 2, the trigger 28 is reset to the initial state, blocking the arrival of pulses from the generator 27 through the element AND 29. In addition, the same pulse goes to the output 38 of the synchronizer as a control pulse by reading and then to the input of reading of memory block 4, where GiPL is read. - 11-1А-Д - - - Af

The selector 3 of the data format (fig.Z) - held by the cell. address, defined contains the decoder 40, the elements of the required counter 2. 41-43, memory block 44, the element OR 45, the contents of the read cell memory delay element 46 and the register 47. In addition, the inputs 48-50 are shown in FIG. .

50

These signals are fed to the information input of register 5, to the synchronization input of which a pulse is output from the output 39 of the synchronizer after a delay on the element 34 for the time of reading information from the memory cell.

The address selector 7 (FIG. 4) contains a memory block 51 made in the form of a permanent storage device, the OR element 52, the first delay element 53, the register 54, the second delay element 55.

Figure 4 also shows the inputs 20-22 and 56 of the unit 7 and the outputs 57-59.

0

five

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25

35

40

.

In Fig. 1, the numbers 60 and 61 denote the outputs of the first comparator 6, and the position 62 denotes the start input of the device.

The device works as follows.

Before starting, all its elements and components are reset (the setting circuits to zero are not shown in the drawing in order to simplify it).

Register 8 uses the information bus from input 19 to the clock pulse from input 18 to enter the number of frames of information material that the operator must enter into the system as a sequential set of messages of a given format. Then the operator presses the Work key (not shown) and the Start pulse receives at input 62, which passes to the single input of the trigger 28 and sets it to the single state, in which he opens the element 29 at the potential input, to the impulse .: the input of which receives impulses from the generator 27.

The first pulse of the generator 27, having passed the element AND 29 and then the element OR 30, goes through the output 37 of the synchronizer 1 to the counting input of the counter 2 of the address, which fixes the first unit to the address.

The pulse from the output of the element OR 30, the delayed element 33 for the response time of the counter 2, the trigger 28 is reset to the initial state, blocking the arrival of pulses from the generator 27 through the element AND 29. In addition, the same pulse goes to the output 38 of the synchronizer as a control pulse reading and then to the read input of the memory block 4, where readsAf

- held by the cell. address determined by the counter 2. The contents of the read memory cell

These signals are fed to the information input of register 5, to the synchronization input of which a pulse is output from the output 39 of the synchronizer after a delay on the element 34 for the time of reading information from the memory cell.

The contents of register 5, via output 23, are fed to a display screen on which the format and contents of the document document to be typed are displayed (the display is not shown).

The address selector 7 is designed to form a message of a predetermined format, for which function keys on the control panel (not shown) have function keys, each of which is marked with corresponding identifiers 1 letters and numbers.

Pressing any of them initiates the appearance of a pulse on one of the inputs 20-22 of the block. 7

The 11 pulse of dialing from one of the inputs 20-22 goes to the corresponding input of the memory block 51, made in the form of a ROM, in which cells the security codes are called by pressing the corresponding function keys.

The input to the corresponding fixed cell of the block 7, the pulse set reads its contents to the infrared input of the register 34, to the sync input of which a pulse arrives from the output of the delay element 53, where it is delayed for the time of reading data from the memory block.

In addition, a pulse of dialing through the element OR 52 is fed to the pulse inputs of elements 41-43, and pa 3, a high resolution potential is supplied to the potential input of one of which from the output of the decoder 40.

Taking into account that at this moment in the counter 2 the first address is fixed, then one of the elements AND 41-43 will be opened with a high potential corresponding to this address. Suppose, for definiteness, an AND 41 element is open. Then the pulse from the output of the OR 52 element, passed the AND 41 element, enters the read input of the corresponding memory cell of the block 44, made in the form of a ROM, where the code of the specified data format is stored.

This code is read from memory block 44 to the information input of register 47, the synchronous input of which receives the same impulse, passed the elements OR 45 and was delayed by delaying element 46 for reading the data from the memory of block 44.

From the output of register 47, the code of the required format is output to output 24 and then displayed on the display screen. In addition, the same code

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opa10

15

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25

Em to the first information input of the comparator 6, the second information input of which receives the code of the selected format.

After entering the codes into registers 54 and 47, the pulse from the output of delay element 55, which delays the pulse by transient time in registers 47 and 54, is fed to the clock input of the comparator 6, the output signals of which are determined by the values of the input codes.

If the codes of the selected and correct formats match, then at the moment the clock pulse is applied to the input of the comparator 6, the latter generates a pulse at output 60, which, first, enters through AND 17 to the summing input of the reversible counter 14, where the fact of correct dialing is recorded.

Secondly, the impulse from the output 60 arrives at the zero input of the trigger 11, confirming its zero state, in which the element And 17 is open with a high potential from the zero output of the trigger 11.

Thirdly, the same pulse arrives at the synchronization of the input of the comparator 9, the information inputs of which are supplied with the numerical values of the register codes 8 and counter 2, and to the input of the delay element 32.

The comparator -9 only works if the input codes are equal, i.e. when counter 2 detects a code that is equal to the code stored in register 8. Delay 32 delay delays the input pin by a time equal to the trigger time 10, if it is triggered by a comparator output signal. Since there is no output signal of the comparator 9 in this case, the trigger 10 remains in the initial state and the high potential from the zero output opens the element I 31, through which the pulse from the output-ele -: ;; The delay element 32 and the OR element 30 are fed to the counting input of the counter 2, the address of the following format is set, and the delay element 33 is fed to the read input of the memory block 4, reading the format code for the formation of the register input 5 in the above way.

thirty

40

45

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55

Fourth, the same pulse from the output of delay element 33 enters

to the zero input of the trigger 28, confirming its zero state.

Fifth, a pulse from the output 60 of the comparator 6 passes through the OR 13 element and then goes to the installation inputs of the register 47 of the selector 3, register 5 and through the OR element 12 to the installation input of the register 54.

If the code of the chosen format does not coincide with the code of the correct format, then the comparator p 6 produces a pulse at the output 61. This pulse, first, goes to the subtractive input of the reversible counter 14, where it records the fact of the wrong dialing.

Secondly, the same impulse goes to the single input of the trigger 11, sets it to the single state, and then through the OR 12-2o element to the setup input of the register 54, resetting it to the initial state. T: riggon 15 11, going to the unit state, low potential from the zero output blocks operation at the potential input.

The operator observed on the screen the result of his dialing, which enters output 26 from register 54, and the correct set. From output 24 of the device, making sure that the answer is incorrect, presses the C key in the correct format in the manner described. Now the comparator 6 fixes this situation by issuing a pulse at output 60, However, the element I 17 im-.: .- pulse from output 60 to the summing input of the reversing counter 14 will not pass, because element 17 is locked with a low potential from the zero output of the trigger 11, But then, with this impulse arriving at the zero input of the trigger 11, the latter returns to the initial state.

In addition, the pulse from the comparator output 60 is described as follows: it goes to the input 36 of synchronizer 1 and through the OR 13 element to the input 50 of the selector 3, as well as to the setup input of the register 54.

After the message codogram is fully typed, it fixes comparator 9 by comparing register codes 8 and counter 2, which are the same,

As a result of the comparison, the next pulse from the output 60 of the comparator 6, entering the synchronizing input of the comparator 9, will cause the appearance of

its pulse output, which will set the trigger 10 to one state, and the low potential from the zero output will block the element And 31,

In addition, the same pulse arrives at the installation input of the counter 2, resetting it to its initial state, and at the pulse inputs of the And 15 elements, rewriting the contents of the reversible Counter 14 to the input 25.

The contents of the reversible counter will determine the degree of readiness of the documentary operator to perform the tasks assigned to him. After the contents of the reversible counter are rewritten to the input 25 by the same pulse, the delay element 16 held for the time of the census being rewritten, the reversible counter 14 and the trigger 10 are reset.

After that, the device is ready for a new work cycle.

Claims (1)

Invention Formula An information input device comprising an address selector, a synchronizer, the first element OR, the element AND a group of elements AND, a memory block, the first and second registers, the counter address element, delays, the information inputs of the address selector are the second group of information inputs of the device, first The second outputs of the synchronizer are connected to the counting input of the address counter and the input of the readout of the memory block, respectively, characterized in that, to increase the reliability of the device, a data format selector is entered into it, Which is connected to the output of the address counter, the synchronizing input is connected to the third output of the address selector, the first comparator, whose information inputs are connected to the second input of the address selector and the output of the data format selector, and the synchronous input / connection to the first output of the address selector, the second comparator The information inputs of which are connected to the outputs of the address counter and the second register, and the sync input is connected to the first output of the first comparator, the output of the second comparator is connected to the single input m of the first trigger, the input of the delay element. The first input of the second element OR, the synchronizing input of the group of elements AND, and the installation input of the first address counter, the output of which is connected to the address input of the memory block whose output is connected to the information input of the first register, the synchronous input of which is connected to the third synchronizer output, the first input of which connected to the inverse output of the first trigger, the zero input of which and the reset input of the reversible counter are connected to the output of the delay element, the first output of the first to the controller is connected to the zero input m of the second trigger, the second input of the second element OR, the first input of the AND element, the second input of the synchronizer, the output of the second OR element is connected to the first input of the first IL1 element, the output of which is connected to the selector input of the ad five 0 The second output of the first comparator is connected to the second input of the first element OR, subtracting the input of the reversible counter and to the single input of the second trigger, the inverse output of which is connected to the second input of the element And whose output is connected to the summing input of the reverse counter of the counter, the outputs of which Connected to the information inputs of the group of elements And, the inputs of the second regisg, tra and the third input of the synchronizer are respectively a perry group of information inputs and a start input of the device, the output of the second element The OR is connected to the setup inputs of the data format selector and the first register, the second output of the address selector, the outputs of the AND group, the data format selector, and the first register are the information outputs of the device. 50 o FIG. g about 24 Fig.Z, Fy