SU1513437A1 - Information input device - Google Patents

Abstract

The invention relates to the field of automation and can be used in computer user dialogue systems. The aim of the invention is to improve the speed of the device due to the automatic change of symbols and functionality of the keyboard key. The device contains the first and second registers 1 and 2, the decoder 3, the adder 4, the memory block 5, the counter 6, the comparator 7, the control trigger 8, the first and second elements OR 9 and 10, groups 11,12 and 13 elements AND first to third elements are 14, 15 and 16, and first to fifth delay elements 17-21. The device eliminates the need to perform any manual procedures for searching, identifying the location and digitizing keys on the keyboard field. 2 Il.

Description

P 18 to

(L

SP

00

 with

e

3151343G

The invention relates to an automatic device, in particular to a device, the provision of hardware

functioning of the multifunctional keyboard of the control panel is adapted to the types and possibilities of a non-professional user, and can be used by computer user dialogue systems

The purpose of the invention is to increase the speed of the device.

Figure 1 presents the block diagram of the proposed device; 2 a time diagram of the operation of the device.

The device (Fig. 1) contains the first 1 and second 2 registers, the decoder 3, the adder 4, the memory block 5, the counter 6, the comparator 7, the control trigger 8, the first 9 and the second 10 elements OR, the element groups AND 11 -13 first 14, second 15 and third 16 elements And, first 17, second 18, third 19, quarter 20 and five 21 delay elements.

The device also has an information input 22 and a device synchronization input 23, as well as a synchronization output -24 and information outputs 25-27 of the device.

The device works as follows.

In the initial state, all the keys on the keyboard floor are blank, except for the ruler with the keys with the names of the subject areas located on the left side of the working field. Each key on its surface contains not a dotted raster, but a 12-segment raster, from combinations of segments of which any character can be formed on the surface of the key.

Each raster is connected to the outputs of the corresponding 12-bit register, the number of which corresponds to the number of keys and forms a matrix register memory located on the control panel and implemented as one large integrated circuit.

Depending on the type (type) of the user, who works at the automated workplace equipped with this keyboard, before starting work, the user presses a key with the name of the subject area located on the identification keys.

0

five

five

0

0

Suppose that in this case, an operator working with the ADA language is in the villages' workplace. He presses the hell key. The code from the pressed key enters the information input 22 of the device, from where the synchronization pulse from input 23 enters register 1..

The code entered in register 1 consists of two parts: the code of the base address of the first character of the ADA, the code of the number of characters of the ADA.

In the initial state, all nodes and elements are reset to the zero state (the installation circuits to the initial initial state and the initial installation controls are not shown).

From the first information output of register 1, the code of the base address of the first character of the ADA is fed to one information input of the adder 4, to another information input of which the code is fed from the data of counter 6. However, the last one is reset at the moment, so the second information input of the adder 4 will be a code, equal O.

The sync pulse from input 23 in parallel with writing the code in register 1 passes through the OR 9 element to the delay element 17, where it is delayed by the time the code is written to the register 1, and then enters both the input of the delay element 18 and the synchronizing input of the adder 4, start the operation of adding the code of the base address of the first character with the output code of the counter 4, equal to this moment 00 ... 0.

as a result, the summation operator at the output of the adder 4 sets the code of the base address of the first per character, which is fed to the address input of memory block 5.

In block 5 of memory, in each of the different areas of memory, for each of the subject areas, identification data is written about which of the position keys on the control panel corresponds to a given character from the selected subject area.

five

0

0

The structure of the code word in whose. The memory of block 5 has the following; its appearance: the code of the positional location of a key on the keyboard remote control the code of the displayed character.

51

A pulse from the output of the 18J delay element, delayed by the execution time of the address modification operation in the adder 4, reads the contents of the cell of the base address of the memory block 5 to the input of the register 2, where the read code is recorded by the synchronization pulse arriving at the clock input from the element 19 delay (figure 2, poses, 4).

The decoder 3 decodes the key position code of the key on the keyboard field to be digitized, and high potential at one of its outputs reveals that group of corresponding elements 11-13, the outputs of which are connected through the corresponding outputs 25-27 of the device to the corresponding 12-character keyboard floor (not shown), since it is not included in the set of essential features of the claimed object).

Other inputs of the same elements And 11-13 are connected to the first information output of register 2, whence the twelve-digit character code arrives at the outputs of the device.

And, finally, a pulse from the output of delay element 20 (Fig. 2, pos. 5), the code of the displayed symbol is inserted through the corresponding output 25-27 to the register of a certain position key, and, as a result, on the 12-segment field of this key is displayed (displayed) The first character of the alphabet.

From the output of the delay element 20, the synchronization pulse also arrives at the synchronous input of the comparator 7, checking whether the equality code from the output of counter 6 and the number of characters in register 1 is checked. Since this condition is not met: only the first character is read, no signals will be output at the comparator output .

The impulse from the output of the delay element 19 (Fig. 2, pos. 4) also passes through the element 15, which is opened with a high potential from the inverse output of the trigger 8, which is in the zero state, to the counting input of the counter 6, which registers the first inserted symbol.

The synchronization pulse from the input of the delay element 20 is also supported by the delay element 21 (FIG. 2, pos.5) for the duration of the operation of the comparator 7

ten

4376

and arrives at the inputs of the elements 14 and 16. Since the trigger 8 remains in the zero state, the high potential from the zero output of the trigger 8 on the element 16 opens, and the synchronization pulse, passed through the element 16, resets the O register 2, pass through the element OR 10 to the reset input of register 2, as well as through the element OR 9 and the element 17 for-. the holder re-enters the synchronization input of the adder 4, which adds the code 1 to the base address

, from the counter and forms the read address of the next character for the next position key, which is outputted in the indicated manner. The digitization process continues.

2Q until the comparator 7 fixes the equality of the codes in the counter 6 and the register 1. This moment is fixed by the trigger 8, which, according to the signal of the comparator 7, is set to

25 a single state and thus a high potential from the direct output opens the element And 14, and a low potential from the inverse output blocks the elements And 15 and 16, blocking the inputs of the counter 6 and the element OR 9.

Now delayed by the time when Comparator 7 and Trigger 8 are triggered by Delay Element 21, the pulse passes through AND 14 to Exit 24 as a keyboard digitizing end signal, and also goes directly to the reset inputs of Counter 6, Register 1, Adder 4 and through Element OR 10 to the fault input of register 2, returning the device to its initial state.

Thus, the introduction of new nodes and elements significantly improves the speed of the device, eliminating the need to perform any manual procedures for searching, locating, and digitizing keys on the keyboard field.

thirty

40

50

Claims (1)

Invention Formula A device for entering information containing the first register, information and synchronization inputs of which are information and synchronization inputs of the device, the second register, whose information input is connected to the information output of the memory unit, and the first information output connected to the first inputs of elements AND of the group, element I.ta, the first input of which is connected to the {synchronizing input of the device, and the code connected to the input of the first delay element, the output of which is connected to the input of the second element ki, the output of which is connected to the in (SODOM of the readout of the memory unit and the input of the third delay element, whose output is connected to the synchronizing input of the second register, control trigger, the direct output of which is connected to the first input of the first element The output of which is the synchronization of the output of the device, characterized in that, in order to improve speed, the second and third elements AND, the second OR element, the counter, the comparator, the adder, the decoder, the quarter and the fifth delay elements, and the fourth input are entered into it. The delay element is connected to the output of the third delay element and the first input of the BjToporo element I, the second input of which is connected to the inverse output of the control trigger and the second input of the filter element I, and the output connected to the clock input of the counter which is connected to | the set input of the first register, the reset input of the control trigger, the input of the adder, nepBbiii input the house of the second OR element and the output of the first AND element, the second input of which is connected to the second input of the third AND element and the output of the fifth delay element, the input of which is connected to the output of the fourth delay element, the second inputs of the AND group elements and the control input of the comparator, the first group of information the inputs of which are connected to the second group of information inputs of the adder and the outputs of the counter, the second. The group of information inputs is connected to the second group of information outputs of the first register, and the output is connected to the control input of the control trigger, the first group of information outputs of the first register is connected to the first group of information inputs of the adder, the control input of which is connected to the output of the first delay element, and the output with the information input of the memory block, the output of the third element AND is connected to the second inputs of the first and second element OR, the output of the second element OR is connected to the reset input of the second the register, the second group of information outputs of which are connected by t inputs of the decoder, the outputs of which are connected to the control inputs of the corresponding elements AND groups, the outputs of which are a group of information outputs of the device.