SU1735878A1 - Device for identifying recognition objects - Google Patents

Abstract

The invention relates to automation and can be used in robot control systems. The purpose of the invention is to increase the speed of the device by introducing the third, fourth, fifth and sixth elements of OR, second, third, fourth, fifth, sixth and seventh delay elements, the third and fourth elements of AND, the third and fourth groups of AND elements and the fourth register allows the use of such a device to identify the characteristic code of the object., 1 or

Description

The invention relates to automation and can be used in robot control systems.

The purpose of the invention is to increase the speed of the device,

The drawing shows the block diagram of the proposed device

The device includes the first 1 and second 2 blocks of memory, the first 3, the second C, the third 5 and the fourth 6 registers, the first 7–9, the second 10–12, the third 13 and the fourth H of the group of elements I, the decoder 15, the first 16, the second 17, third 18, fourth 19, fifth 5 and sixth 21 elements OR, first 22, second 23 and third 2k elements AND, first 25, second 26, third 27, fourth 28, fifth 29 and sixth 30 delay elements, trigger 31 blocking, the fourth element And 32 and the seventh element 33 delay.

The drawing also shows the first S1, the second 35 and the third 36 groups of information inputs of the devices, the first 37, the second 38 and the third 39 synchronization inputs, input 0 - the installation input of the Device Setup, and the first 1 and second 2 information outputs of the device, the first 3, the second kk and the third 45 synchronizing outputs of the device.,

Before the device starts to operate, the signal Set. About the registers 3 and k are reset to the initial state, the register 5 through the element OR 18, and the trigger 31 through the element OR 20,

Before the device starts operation, the information inputs of the register 6 from input 36 are supplied with the code of the base address (identifiable object image), which is

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input 39i supplied to the sync jack is written to register 6.

After that, the device is ready for operation and works as follows.

An identification code characterizing the object to be identified, from input 35, enters the input of register 5 and is written into it by a clock signal from input 37. The identification code is decoded by the decoder 15, and a high potential will be input to one of the AND 10-12 elements corresponding to the received code. which opens the corresponding element AND 10-12 through one input. To the other input of the specified element I, by this moment of time a pulse comes from the output of the delay element 28, delayed by the transient time in register 5 and desh ifratore 15

The incoming pulse passes through one of the elements AND 10-12 directly to the read input of the fixed cell of the memory block 2, in which the code word is written, the unit values of the bits of which characterize the description of the identification object in the space of signs that arrive at its inputs 3.

The content of the read fixed cell is fed to the information inputs of register 3, and the read pulse of the identification code word from memory block 2 and through the AND 2k element opened at the second input by a high potential from the zero output of trigger 31 is sent to the synchronization input of the register 3, writing it received the identification word code.

Depending on the state of the various bits of the register 3, their output potentials determine the state of the AND elements, through which signals are received indicating the presence of signs characterizing the identification object

Assume that the signal for the presence of a sign received through the element And 7, the corresponding register bit 3 is in the unit. This impulse then passes through the element AND 7 to the read input of the fixed cell of the memory unit 1, where the base address is stored, in which the parameters corresponding to the aforementioned feature are recorded.

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15

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The base address from the output of memory block 1 is fed to the information inputs of register A, to the synchronization input of which the same read pulse is transmitted through an OR 16 element and delayed by delay element 25 for reading the base address from memory 1. After entering the base address into the register C with a pulse, a delayed delay element 27 at the transient time in register k and entering through the element OR 21 at the pulse inputs of elements AND 13, the base address is output 1. The same read pulse from the output the OR-21 element, delayed by the element 29 for the time of reading the code, through the AND 32 element, opened at the second input, is output to the output number as a readiness signal for receiving parameters from the device’s memory

At the address indicated, there is an appeal from the output of th, and all the required information about the identification object is displayed on the display

To change the frame and present the next image of the object on

30, the direct input of the trigger 31 is given a signal that sets the trigger 31 to one state, in which the AND 2 element is closed and the AND 23 element is open.

35 In addition, the same pulse arriving at the inputs of the AND 1 elements, the code of the address of the next image of the object is output to the device 2, and through the delay element 30, the delaying pulse for the time of code rewriting, the output of the object image is output to the screen 5 display at the specified address.

45 To recognize this object, the identification code of the object to be recognized is again entered into register 5 and the described procedures are repeated.

A pulse from input 37, a delayed element 28 at the time of transient processes and passing through the specified element from elements 10-12, calls the fixed cell of block 2. As a result, the identification code word from the output of block 2 is set to informational. the inputs of register 3. However, the code is not re-recorded in register 3, since the read pulse through the OR element 17 and the delay element 26 does not pass to the synchronous input, register 3, because the AND 2 element is blocked by a low potential from the zero output of the blocking trigger 31.

The AND 23 element is open, therefore, from the output of the delay element 26, a pulse passes through it and then enters the input of the load element 33, and also returns the trigger 31 to the initial state through the OR element 20, removing the blocking of AND elements 13 and 32,

The same impulse delayed by element 33 at the trigger time Gera 31i through the element OR 21 passes to the input of the census of the contents of the base address of the register 2 and through the elements And 13 to the output D1, and after the code is rewritten and delayed by the element 29 at the time of code rewriting, this pulse through the element And 32 is issued on the exit,

Claims (1)

Invention Formula A device for identifying recognition volumes, containing the first group of elements AND, the first inputs of which are the first information inputs of the device, the second connected to the outputs of the first register, and the outputs connected to the control input-1 of the first memory block and to the inputs of the first OR element, the first delay element, the input of which is connected to the output of the first OR element, the second register, the information inputs of which are connected to the output of the first memory block, the synchronization input connected to the output of the first element delays, and the reset input is the device setup depth, the third register, the information outputs of which are the second information inputs of the device, the timing synchronization is the first synchronization input of the device, and the outputs are connected to the inputs of the decoders, the first output of which is connected to the first input of the elements And the second groups whose outputs are connected to the inputs of the second OR element and to the control input of the second memory block whose outputs are connected to the information inputs of the first register, n0 five 0 five the left input of which is connected to the installation input of the device, the first and second elements AND, characterized in that, in order to increase the speed of the device, a third OR element is entered into it, one input of which is connected to the installation input of the device, the other is connected to the output of the first AND element, and the output is connected to the zero input of the third register, the second delay element, whose input is connected to the output of the second OR element, and the output is connected to the third input of the third OR element and to one input of the second AND element, the third element And, one input of which is connected to the output of the second delay element, and the output is connected to the synchronization input of the first register, the third delay element, the input of which is connected to the output of the first delay element, the fourth OR element, whose inputs are connected to the second information output of the decoder, and the output is connected with the first input of the first element And, the fourth delay element, the input of which is connected to the first synchronizing input of the device, and the output is connected to the second input of the element And the second group and the second input of the first th AND member, whose output is the first output device, a fifth OR gate, whose first input is connected to a set input of the device, and the OTHER is connected to the output of the second element AND, the blocking trigger whose unit input is the second synchronizing output of the device, the zero input is connected to the output of the fifth element OR, the unit output of the blocking trigger is connected to the second input of the second element I, and the zero output is connected to the second input of the third element, AND, the sixth element OR, one input of which is connected to the output of the third element, the delay, the third group of elements AND, whose inputs are connected to the information output the second register, with the zero outputs of the blocking trigger and with the output of the sixth OR element, and the outputs are the first information output of the device, the fifth delay element whose input is connected to the output of the sixth OR element, the fourth AND element whose inputs are connected to the zero output of the trigger block 0 five five 717 and the output of the fifth delay element, and the output is the second output of the device, the fourth register, the information RESPONSES of which are the third information inputs of the device, and the synchronization input is the third synchronization input of the device, the fourth group of AND elements, the first inputs of which are connected to the information the inputs of the fourth register, the others are connected to the second sync 878 8 the device input and the outputs are the second information output of the device, the sixth delay element, the input of which is connected to the second synchronization input of the device, and the output is the third synchronization input of the device, and the seventh delay element of which input is connected to the output of the second And element and the output is connected to another input of the sixth element OR 40 O- Ir-lH - 36 39 ° 42