SU1718263A2 - Device to check the work of an operator - Google Patents

Abstract

The invention relates to automation and computing, in particular to devices for controlling operator operation. The purpose of the invention is to increase the speed of the device. This goal is achieved by eliminating the repetition of manual procedures for recruiting codograms when reissuing them, which is provided by introducing a second trigger, a sixth delay element, a third register, a comparator, a second OR element, a fifth And element, a second counter, and a second memory block. 4 il.

Description

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The invention relates to the field of automation, in particular, to devices for training operators, can be used in preparing employees of the passport office to work at an automated workplace, built on the basis of a personal computer, and is an improvement of the known device by author. No. 1619330.

A device containing a first decoder is known, the outputs of which are connected to the inputs of the first OR element, the first delay element whose output is connected to the input of the second delay element, the memory block whose synchronizing input is connected to the output of the first delay element, trigger the output of which is connected to one input of the first and second elements AND the counter, the first rncfp, the elements AND, the group of elements OR, the second decoder, the information inputs of which are connected to the outputs of the elements OR of the group, and the outputs connected to the address inputs of the memory block whose information inputs are connected to the outputs of the first register, the information input of which is the information input of the device, and the synchronization input is the synchronization input of the device and connected to the input of the first delay element, the third delay element whose input is connected to the counter overflow output, and the output is connected to one input of the third AND element, the other input of which is connected to the output of the first OR element, and to one input of the fourth AND element, the other in the stroke of which is connected to the corresponding output of the decoder, the fourth delay element, the input of which is connected to the output of the fourth element And, and the output connected to another input of the second element And, the single input of the trigger is connected to the output of the third element And, the zero input is connected to the output of the fourth

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And, and the direct output is the control output of the device, the output of the second element AND is connected to one input of elements AND of the group, the other inputs of which are connected to the outputs of the memory block, and the outputs are information outputs of the first group of device, error selector, information the input of which is connected to the output of the memory unit, the synchronization input is connected to the outputs of the second AND element, the setup input is connected to the overflow output of the counter, and the outputs are information outputs of the second group of the device and the second register, the information input of which is the second information input of the device, the synchronization input is the second synchronization input of the device, and the outputs are connected to one input of the elements of the OR group, the other inputs of which are connected to the information output of the counter, the count input of which connected to the output of the first element And, another input of which is connected to the output of the second delay element, and the fifth delay element, the input of which is connected to the output of the second of the AND gate, and an output connected to the adjusting inputs of the memory block, the first and second registers and the counter ..

A disadvantage of the known device lies in its low speed, due to the fact that if necessary, re-issuing the codogram already transmitted by the operator, he again has to repeat all the manual procedures for dialing this codogram, which drastically reduces the efficiency of its work.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that a second trigger is inserted into the known device, the setup input of which is the setup input of the device, and the single input is connected to the output of the second delay element, the fifth And element, the inputs of which are connected to the inverse output of the second trigger and the output of the first element the delay, the third register, whose information input is the third information input of the device, and the synchronization input is the third synchronization input of the device, the second element OR, one input which is connected to the output of the fifth delay element, the other is connected to the third clock input of the device, the sixth delay element, the input of which is connected to the output of the second OR element, the second counter,

the information input of which is connected to the output of the first register, the synchronization input is connected to the output of the fifth element And, the counting input is connected to the output

the second element OR, and the setup input is connected to the setup input of the device, a comparator, the information inputs of which are connected to the outputs of the third register and the second counter, the synchronization input is connected to the output of the sixth delay element, and the first output is connected to the third input of the second OR element, and the second block the memory whose address input is connected to the output of the second counter, the information input is connected to the output of the first memory block, the recording control input is connected to the transfer output of the first counter, the input y readout is connected to the second output of the comparator, and

the output of the second memory block is the information output of the device.

Figure 1 shows the functional diagram of the device; Fig. 2 shows a constructive implementation of the memory block; on fig.Z constructive execution of the error selector; 4 shows timing diagrams for the operation of the device.

The device (figure 1) contains the first block

1 memory, selector 2 errors, group of elements AND, first 4 and second 5 registers, first counter 6, group 7 elements OR, first 8 and second 9 decoders, first 10, second 11, third 12 and fourth 13 elements

And, the first trigger 14, the first element OR 15, the first 16, the second 17, the third 18, the fourth 19, the fifth 20 delay elements, the sixth delay element 21, the third register 22, the comparator 23, the second element OR 24, the second trigger 25, the fifth element is AND 26, the second counter 27 and the second memory block 28.

In addition, shows the inputs 29-34 and outputs 36-41 device (figure 1).

The first memory block 1 (fig; 2) contains groups 51-53 of elements AND and registers 54-56, as well as inputs 42-47 and outputs 48. The error selector (FIG. 3) contains inputs 49 and 50, decoders 57-59 , blocks 60-62 of memory, elements And 63-71, triggers 72-74.

The device works as follows.

The functional responsibilities of the employees of the passport office include the ability to solve the functional tasks of registration.

issuing passports, propiska, extracts and the like using the automated workplace of the passport office employee ..

For this, the employee of the passport office (operator) should be able to prepare a codogram-message for the corresponding functional task so that these data can later be used to update the database.

The entire sequence of codes that the passport operator must form is formed in a predetermined sequence, for example, the code number code is first generated, then the code of the sending object, then the identifiers of the object being identified, and so on.

For this purpose, the operator first dials on the keyboard the code number of the codogram that arrives at information input 29 of register 4, and then presses the Enter key (not shown), the signal from which arrives at the synchronization input 30 and writes the code into register 4, from the output of which is fed to the input 42 of memory block 1 (figure 2).

After a delay on the delay element 16 at the time of writing the code to the register 4, the same clock pulse arrives at the clock input 46 of the memory unit 1, the address inputs of which are connected to the corresponding outputs of the decoder 8.

Considering that the counter 6 and the register 5 have now been reset to zero, then at the input of the decoder 8 there is a zero code and a high potential at its extreme output is open at the input of a group of 53 elements AND block 1.

The synchronizing pulse from input 46 of block 1, arriving at the synchronous input of the group of 53 elements and the register 54 of block 1, rewrites the contents of register 4 to the register 54 of block 1. Thus, in the register 54, the code of the codogram number is generated.

In addition, the sync pulse arrives from the output of the delay element 16 at the input of the delay element 17, where it is delayed by the time that the codogram number code is written to the register 54, and then fed to the input of the AND 10 element opened at another input by a high potential from the inverse output of the trigger 14.

Passing through the element 10 on the counting input of the counter 6, this clock increases the address generated by the counter by one. As a result, register 55 is connected to the information outputs of register 4 through a group of 51 elements AND.

Then the operator on the control panel dials the code of the object number, which through input 29 enters register 4, and then presses the Enter button, from the contacts which the sync pulse from input 30 enters the synchronous input of register 4 and writes another code into it.

In the described manner, this code is then recorded in the register 55 of block 1, and the process of entering all the components of the codegram continues until a pulse appears at the transfer output of counter 6, indicating that all the components of the codegram are ready and are in registers 54 -56 block 1.

From the output of memory block 1, the outputs of all registers are connected to the inputs of the corresponding decoders 57-59 of the selector 2.

If the code decoded by the corresponding decoder, the operator is dialed correctly, i.e. such a code is among the set of codes that the operator dials, then it is opened at the corresponding output of the decoder 57, for example, AND 63 of block 2.

Then the transfer pulse from the output of the counter 6 passes to the input 50 of the selector and then through the element I 63 to the input to read the fixed cell of the memory block 60, made in the form of a constant memory. In the fixed cells of memory block 60, 1 is written if the dialed code exists in a set of codes, or O if there is no dialed code in the set of codes.

From the output of the fixed cells of all blocks 60-62 of memory in which 1 is stored, the read signals go to the single inputs of the flip-flops 72-74, the output potentials of which arrive at the outputs 37-39 in the form of correctly and incorrectly dialed codes.

In addition, the outputs of the flip-flops 72-74 of the selector 2 are connected to the inputs of the decoder 9, which, in the presence of high potentials at the output of all the flip-flops 72-74, gives a high potential to the input element I 13, the presence of any other codes at the input of the decoder 9 high potential at the output of the element OR 15 is fed to the input of the element And 12.

It is assumed that all components of the codogram are correctly typed, then the high potential from the output of the decoder 9 opens an element 13, to another input of which a transfer pulse of the counter 6 arrives, which is delayed by element 18 for the response time of the decoder 9 and triggers 72-74.

Passing the element 13, a pulse arrives at the zero input of the trigger 14, confirming its zero state, and then after a delay on the delay element 19 the trigger time of the trigger 14 arrives at the pulse input of the element 11 opened by a high potential from the inverse output of the trigger.

Passing through element 11, the sync pulse arrives at the pulse input of group 3 elements AND, overwriting the contents of all registers to output 36 of the device, and through input 49 of the selector 2 resets all triggers 72-74 to the initial state. The same pulse after a delay on element 20 at the time of the census of the code at output 36 goes to zero inputs of registers 4 and 5, counter 6 and through input 47 to reset registers 54-56.

If at least one of the components of the codogram is typed by the operator incorrectly, then the high potential from the output of the OR 15 element is open to the AND 12 element.

In this case, the transfer pulse from the output of the delay element 18, passed through the element 12, arrives at the single input of the trigger 14 and sets it to the single state.

A high potential from the single output of the trigger 14 is output to the device output 40, indicating that the codogram is typed incorrectly, and the output potentials at the outputs 37-39 indicate which component of the codogram is typed incorrectly.

To correct an error, the operator on the control panel must press a key with the name of the component of the code pattern that was typed in error. Pressing the key leads to the fact that the input code 31 receives the code of the position of the component in the codogram, and the input clock 32 receives the clock pulse, which this code writes to the register 5.

The code from the output of register 5 through a group of 7 elements OR is fed to the inputs of the decoder 8, which to the outputs of register 4 connects the corresponding register 54-56, to which a correction must be made.

After making a correction to the corresponding component of the codogram, the operator in the described manner sends the dialed codogram to the address of the superior object of the ACS.

Thus, the known device works.

However, after the transmission of codograms to the address of a higher object due to the low reliability of communication channels and other reasons, there is a need to reissue the codograms.

In order to avoid re-dialing the blocks that make up the codogram, during the initial recruitment of codograms after entering the codogram number into register 4 from input 29 with a sync pulse from the output of delay element 16, the codogram number code is recorded not only into memory block 1, but with a pulse that passes through the element And 26 and received on the synchronous input of the counter 27,

it is stored in the counter 27, forming the first write address for the memory block 28.

After the operator has generated the complete codogram, the code from the output 48 of block 1

is outputted not only at the output 36 of the device, but also enters the information input of the memory block 28, where it is recorded at the address formed by the counter 27 by a pulse from the transfer output of the counter 6.

In addition, the same pulse after delay by element 20 passes through the element OR 24 to the counting input of counter 27 and increases its readings by one, forming the next address for memory block 28.

Similarly, all the codograms generated by the passport operator are recorded in the memory of block 28. If necessary, reissue

any of the already transmitted codograms at the input 33 receives the code of the codogram number, and the input 34 of the sync pulse, according to which the code from the input 33 is entered into the register 22. At the same time, the same sync pulse with

input 34 passes through the element OR 24 and enters the counting input of the counter 27, increasing its contents by one.

After a delay by element 21 at the end of the transient processes in the counter 27

the pulse from the output of the delay element 21 is fed to the synchronous input of the comparator 23, which compares the codes of the register 22 and the counter 27.

If the codes are not equal, then the comparator 23 generates a signal at the output, which

again through the element OR 24 enters the counting input of the counter 27 and after a delay - the synchronous input of the comparator 23.

This process continues until the codes in register 22 and counter 27 do not

coincide and the output 35 of the coparator 23 does not appear a signal fixing the equality of the codes. This signal is fed to the read input of the memory block 28 and, at the address set in the counter 27, reads the codogram recorded there to the output 41.

Thus, the introduction of additional nodes and elements significantly improves the speed of the device, eliminating the need for the operator to re-manually set the codogram.

Claims (1)

Invention Formula Device for controlling the work of the operator auth.St. Isfe 1619330, characterized in that, in order to increase the speed of the device, a second trigger is inserted into it, the setup input of which is the installation input of the device, and the input input connected to the output of the second delay element, the fifth element I. The inputs of which are connected to the inverse output of the second trigger and the output of the first delay element, the third register, whose information input is the third information input of the device, and the synchronization input of the third synchronization input of the device, the second element OR, one input of which is connected to the output of the fifth delay element, the other one is connected to the third synchronizing input of the device; the sixth delay element, the input of which is connected to the output of the second element OR, the second counter, whose information input is connected to the output of the first register, the synchronization input connected to the output of the fifth element AND, the counting input is to the output of the second element OR, and the installation input is connected to the device installation input, a comparator, whose information inputs are connected to the outputs of the third register and the second counter, the synchronization input is connected to the output of the sixth delay element, and the first output is connected to the third input of the second element OR, and the second memory block, whose address input is connected to the output of the second counter, the information input is connected to the output of the first memory block, the record control input is connected to the transfer output of the first counter, the control input the reading is connected to the second output of the comparator, and the output of the second memory block is an additional information output of the device. 1 1 u Ј928Ш Faode 47 signal  / 7 Nav / move with per. cvemwra} T  Signal at the memory input FagL t h t H I Memory i t t TO