SU1509982A2 - Device for sampling information from memory unit - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices. The purpose of the invention is to improve the reliability of the device. This is achieved by introducing user access control to different sections of the memory. The device contains memory blocks of base addresses 1, data 2, number of data calls 3 and access codes 27, reversible counter 4, decoder 5 number of calls, elements 6 and 23, element 7, registers of base addresses 8, access 16 and password 17 , adder 9 modulo two, elements OR 10.18 and 19, delay elements 11-14 and 28, address selector 15, decoder 20, triggers 21 and 22, and a group of elements 24-26. 3 il.

Description

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The invention relates to computing, in particular, to storage properties, and is an enhancement of the device according to the basic author, No. 1387033.

The purpose of the invention is to increase the reliability of the device.

FIG. a block diagram of the device is presented; FIG. 2 shows a constructive implementation of an address selector; Fig. 3 shows a constructive execution of the memory block, the number of data calls.

The device contains (block 1 of memory of base addresses, block 2 of data memory, block 3 of memory of the number of data calls, reversible counter 4, decoder 5 of the number of calls, first element AND 6, element NOT 7, register 8 basic addresses, adder 9 through module two, first element OR 10, delay elements 11-14 (from first 11 to fourth 14), address selector 15, access register 16, password register 17, 25 second element OR 18, third element OR 19, decoder 20, first 21 and second 22 triggers, second element And 23, group of elements And 24-26, block 27 of memory of access codes, fifth element 28 of delay ki

The first memory block 1 is made in the form of a persistent storage device, in fixed cells of which the base addresses are kept, from which help is started on the relevant subject areas. The second memory block 2 is executed on the address structure.

The address selector 15 (FIG. 2) contains the first 29, 30, Second 31, 32, third 33, 34 groups of elements AND, triggers 35-37, group of elements OR 38-40, first 41, second 42 elements OR, elements 43- 45 delay, the third element 46 delay,

Memory block 3 (FIG. 3) contains the first 47-49 and the second 50-32 groups of the AND elements, registers 53-35 and the group of elements OR 36,

Figures 1-3 also show signal. O. inputs 57-39 of the address selector, data reclose input 60, first synchronization input 61, installation input 62, second synchronization. The device works as follows.

Inputs 57-59 of the selector 15 (FIGS. 1 and 2) are connected to mnemonic keys of the control panel (not shown), the number of which is determined by the number of subject areas with which the user works. Mnemonically, the names of the respective subject areas are superimposed on the corresponding keys.

Information input 64 is connected to the numeric keypad of the control panel, with which the operator on the control panel dials the password code, inputs 61 and 63 are connected to the keyboard Enter the password and Password, respectively, and input 62 is connected to the 2 key. End of work.

Help and other operational information about all subject areas is pre-recorded in block 2 (chains and records of the specified information in the memory of block 2, as well as the chain of installation of all nodes and blocks in the initial state are not shown to simplify the functional diagram of the device). mnemonic keys cause the appearance of the help signal on the corresponding input 57-59 of the selector 13. Suppose that such a signal occurs at the input 37, from where it arrives at the pulse inputs of elements AND 29, 30. However, in contrast to the known device, in which element AND 29 is open with a high potential from the inverse output, three heres are 35, and element 29 also has two inputs, for which it is locked by low potentials from a single output, trigger 21, which enters the input of the interlock of the selector 15 and from a single output of the corresponding bit of registration 16,

Each user, calling the information he needs, must first enter the password code by typing it. On the numeric keypad and press the Enter key,

Using the numeric keypad, the user dials the code of the password, the third is entered from the information input 64 into the register 17, and the control signal with. login 63 password code for

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A device's 63 input, 55 information is carried to register 17. This code is a device 64 input, information is encrypted by the decoder 20 and the device’s national output 65, output 66 No password, and output 67 One of its outputs appears high the potential that opens one of the elements And 24-26, for example And 24,

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The device works as follows.

Inputs 57-59 of the selector 15 (FIGS. 1 and 2) are connected to mnemonic keys of the control panel (not shown), the number of which is determined by the number of subject areas with which the user works. The mnemonic names of the respective subject areas are superimposed on the corresponding keys.

Information input 64 is connected to the numeric keypad of the control panel. In this case, the operator on the control panel dials the password code, inputs 61 and 63 are connected to the Enter password and Password keys, respectively, and input 62 is connected to the End of work key.

Help and other operational information about all subject areas is pre-recorded in block 2 (chains and records of the specified information in the memory of block 2, as well as the chain of installation of all nodes and blocks in the initial state are not shown to simplify the functional diagram of the device). mnemonic keys cause the help signal on the corresponding input 57-59 of the selector 13 to appear. Suppose that such a signal is at VILS at input 37, from where it arrives at the pulse inputs of elements AND 29, 30. However, unlike the known device, in which element AND 29 is open with high potential from the inverse output of trigger 35, element 29 also has two entrances on which it is locked by low potentials from a single exit tri-. Gera 21 arriving at the interlock input of the selector 15 and from the single output of the corresponding register bit 16,

Each user, calling the information he needs, must first enter the password code by typing it. On the numeric keypad and press the Enter key,

Using the numeric keypad, the user dials the code of the password that is received from information input 64 to register 17, and the control signal is c. input 63 password code for 0

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This is decoded into register 17. This code is decoded by decoder 20 and

one of its outputs appears high potential, opening one of the elements And 24-26, for example And 24,

After that, the user presses the Password key and the signal from input 61 through the OR element 18 enters the pulse inputs of elements 24-26 and passes through the open element AND 2D to the read input of the fixed memory cell of the block 27, made in the form of a persistent storage device, and reads its contents to the register entry. sixteen,

At the same time, the same read pulse, which passed through the OR element 19 and the delayed delay element 28 while reading the contents of the fixed cell of the block 27, writes the code to the register 16 by applying a pulse to its clock input.

The code of the Access Control word corresponding to the entered password is stored in each of the fixed cells of the block 27. Units in bits The words of access control mean that this user has access to the corresponding subject areas, and zeros mean no access. From the output of each of the bits in the register, the corresponding potentials are fed to the inputs of the address selector 15.

If the user presses the Password key without typing the password code on the keyboard, then in register 17 there will be one zeros and a high potential corresponding to this state of register 17, the decoder opens the potential input element AND 23, Then the pulse from input 61 through the element OR 18 After having passed the AND 23 element, it arrives at the single input of the trigger 22 and sets it to the single state, with the result that the Enter 66 signal is output to the output 66.

If the password is dialed and entered, then, along with the passage of the signal to write it to the register 16, the pulse from the output of the delay element 28 also goes to the zero input of the register 17, resetting it to its original state, and to the single input of the trigger 21, setting it to the single state and thereby removing the inhibitory potential from the single output, which is input to the blocking of the address selector 15. The same permit potential is also output to the device output 67 as an indication signal. There is a password.

Assume that the password is entered and in the register 16 the Word is displayed

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no access. Element AND 29 (FIG. 2) is open at all three inputs if the corresponding word rank has a unit, and element 30 is locked with a low potential from a single output of trigger 35,

Passing the AND 29 element, the call pulse through the SHSh 39 and 40 elements is fed to the zero inputs of the flip-flops 36 and 37, confirming their zero state, through the OR 41 element it goes to the output, and also after the delay on the delay element 43 it goes to the single trigger input 35, setting it to one. In addition, it is output to the output of the selector directly and through the OR element 42 to the output of the selector (Fig. 2). Then, the call pulse from the output goes to the synchronization inputs of the AND 47-49 elements and registers 53-55 of block 3. Since AND 47-49 elements are closed at the potential input by low potentials from the single outputs of the flip-flops 35-37, the arrival of a sync pulse at the input does not impact on the state of registers 53-55,

After a delay of the call pulse on the element 43 for the time determined by the response time of the registers 53-55, it arrives at the single input of the trigger 35, setting it to the single state at which high

5, the potential element opens at element 30, and the low potential closes element at element 29, the high potential from the single-exit trigger is output to the output, from where it enters the corresponding inputs of the elements 49 and 52 of block 3 and opens them at one input.

In addition, the same pulse from the output goes to the synchronizing input of the reversible counter 4 ina: the inputs of the corresponding elements AND 52, connecting the outputs of register 55 through the elements OR 56 to the information inputs of the reversing counter 4, Since in the initial state all registers are cleared, In the reversive counter 4, the zero information is entered via information buses; the same impulse is output from the output of the address selector

5 is fed to the input of a fixed cell of block 2, where the base address of the data array of the reference is written. This address is from the output of block 1 to infor0

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The pairing code is entered into the register 8 by the clock signal from the output of the delay element 11. The last from the output of the delay element 11, the passed element OR 10, is fed to the input of the second delay element 12, where it is delayed by the time the code is set in register 8.

From the output of the register 8 and the reversing counter 4, in which there are only zeros at a given time, their contents are fed to the input of the adder 9, where the final result is generated by the clock signal from the output of the delay element 12, which is fed to the address input of the memory 2 , to the read input of which the read signal comes from the output of the delay element 13, delaying the sync pulse for the transient time in the adder 9,

As a result, the output of the device 65 yields the contents of the corresponding cell of the memory block 2 as a reference for the corresponding subject area, and the read pulse itself goes to the summing input of the reversible counter.4 and increases its content, by one,

In addition, the same pulse, after a delay on the delay element 14, at the time of reference acquisition, arrives at the reset input of the adder 9 and sets it to the initial state.

If the user needs the following help from the same subject area, he presses the same key again. At the input 57, a help call pulse appears again, the incoming Hs inputs of the AND elements 29, 30.

However, the call pulse passes through the AND 30 element open at the second input (FIG. 2) and through the OR element 46 passes to the selector output, from immediately through the OR 10 element enters the input of the delay element 12 and further to the clock input of the adder 9, wherein the content of the reversible counter is added to the contents of the base address, thereby increasing the next read address by one.

The described process of invoking reference information on a given subject area continues in a similar manner until the user presses the same key.

If you need to return to the view you just viewed: Help, the user presses the Return key, resulting in an input 60 which generates a pulse arriving at the pulse input of element AND 6, to another input which receives a high potential from the output of element NOT. The decoder 5 outputs to its output a high potential only if the contents of the reversible counter 4 is zero.

Since the case of returning to previously viewed help is considered, the number of viewed references has already been recorded in the up / down counter 4. As a result, the output potential of the decoder will be low, and the output of the element is NOT 7 high. The impulse from input 60, having passed the AND 6 element, goes both to the subtracting input of the reversible counter, reducing its content by one, and through the delay element 12 to the synchronizing input of the adder 9, ensuring the formation of the address at the input of the memory block 2.

A pulse from the output of the delay element 13 at the address determined by the code in the adder 9 reads the contents of the corresponding cell of the memory block 2, and then the pulse from the code of the delay element 14 deduces the adder 9 to its original state.

Pressing the Return key again causes the contents of the references to be scrolled backward until the contents of the up / down counter 4 becomes zero. This moment will be fixed by the decoder 5 by issuing a high potential, which, after inverting the elements NOT 7, will block element 6 on the second input.

The need to view another subject area results in the appearance of a signal at another input of the selector 15, for example, at input 58. This pulse from input 58 passes through the open source element 31 and through the OR element 41 enters the selector code from which it arrives at the clock inputs elements And 47-49. Since the potential of the trigger 35 is open only elements And 49, the pulse from the input (fig.Z) rewrites the contents of the reversible counter in the register 35, and the pulse from the output

delay element 44 and element OR 42 the contents of register 54 through AND 51 and OR 56 elements will be rewritten. in reversible counter 4.

Thus, after reviewing the required number of references when returning to the viewing of any subject area, the need to re-search (paging) references, starting with the first, will be necessary. Pressing a key with the selected subject area immediately brings up the last previously viewed help, which is especially

The device’s data call inputs, the access register outputs are connected to the corresponding signal inputs of the address selector, the settings in the O access register and the first trigger are combined and are the device setup inputs, the password register information inputs are device password inputs, password register synchronization. is the second synchronization input of the device, the register register outputs are connected to the decoder inputs you

it is convenient in a comparative analysis of the data of 5 moves of the lower-order bits of which are connected in the same subject area.

After completing the work, the operator presses the End job key and the signal is fed to input 62, from where he is fed to the zero input of trigger 21, returning it to its original state, in which it blocks the operation of the address selector 15 on the input, and to the zero input of register 16, resetting its initial state and thus blocking the operation of the selector 15 at the inputs.

Claims (1)

Invention Formula A device for retrieving information from a memory block according to the author, No. 1387033, characterized in that, in order to increase the reliability of the device, an access register, a password register, a decoder, an access code memory block, the second and third elements OR, the first and second triggers, the second element And, the group of elements And and the fifth element of the delay, and the input of the second element OR is with the first synchronization in: the device, the inputs of the group of the second element OR are connected with the corresponding 20 25 thirty 35 40 are connected to the first input of the second element I, the output of which is connected to the installation input in G of the second trigger, the output of which is the output No device password, the outputs of the higher bits of the decoder are connected to the first inputs of the corresponding AND elements of the group, the outputs of which are connected to the corresponding inputs of the memory block these access codes, the outputs of which are connected to the information inputs of the access register, the second inputs of the second element AND and the elements AND of the group are connected to the output of the second element OR, the third inputs of the second element nA and AND elements of the group are connected to the inverse output of the first trigger, the direct output of which is connected to the blocking input of the address selector and is an output. The device has password, the inputs of the third element OR are connected to the outputs of the corresponding AND elements of the group, the output of the third element OR is connected to the input nth delay element whose output is connected to the inputs O installation in second trigger and register the password to the installation input in 1 of the first trigger and the synchronization input of the access register. 0 five 0 five 0 are connected to the first input of the second element I, the output of which is connected to the installation input in G of the second trigger, the output of which is the output No device password, the outputs of the higher bits of the decoder are connected to the first inputs of the corresponding AND elements of the group, the outputs of which are connected to the corresponding inputs of the memory block these access codes, the outputs of which are connected to the information inputs of the access register, the second inputs of the second element AND and the elements AND of the group are connected to the output of the second element OR, the third inputs of the second element nA and AND elements of the group are connected to the inverse output of the first trigger, the direct output of which is connected to the blocking input of the address selector and is an output. The device has password, the inputs of the third element OR are connected to the outputs of the corresponding AND elements of the group, the output of the third element OR is connected to the input nth delay element whose output is connected to the inputs O installation in second trigger and register the password to the installation input in 1 of the first trigger and the synchronization input of the access register. Phage.2