SU1626258A1 - Device for identification of signs of objects - Google Patents

Abstract

The invention relates to the field of automation, in particular to devices for identifying codegram messages. The purpose of the invention is to increase the reliability of the device. The goal is achieved by selecting errors and correcting them in codogram messages, which is ensured by introducing a second decoder 9, the information inputs of which are connected to the outputs of the OR elements of the group, the third 18, the fourth 19 and the fifth 20 delay elements, the second register 5, whose information input is the second information input of the device, the error selector 2, the information input of which is connected to the output of the memory block, and the synchronization input is connected to the output of the second element I. 3 Il. YOU Oh yu ate 00 Fig1

Description

The invention relates to automation, in particular to a device for identifying objects, and can be used in control systems for transmitting commands to robots.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the device; Fig 2 is a block diagram of a memory block; in fig. 3 is an error selector diagram.

The device (Fig. 1) contains a memory block 1, an error selector 2, a group of 3 elements And, the first 4 and second 5 registers, a counter b, a group of 7 elements OR, the first 8 and second 9 decoders, the first 10, the second 11, the third 12 and fourth 13 elements AND, trigger 14, element OR 15, first 16, second 17, third 18, fourth 19 and fifth fifth delay elements.

The memory block (Fig. 2) contains registers 21-23, elements AND 24-26 groups.

The error selector (Fig. 3) contains decoders 27-29, memory blocks 30-32, And group elements 33-41, triggers 42-44, In addition, in FIG. 1 shows information inputs 45, 46, synchronization inputs 47, 48, information outputs of the first group 49, the second group 50, and control output 51.

FIG. 2 shows information input 52, address inputs 53-55, synchronization input 56, setup input 57, and information output 58.

FIG. 3 shows a sync input 59 and a setup input 60.

The device works as follows.

At input 45, the codes of all features that make up the description of identifiable objects are received in succession.

Simultaneously with these codes, the corresponding synchronization pulses arrive at the input 47, which, arriving at the synchronizing input of the register 4, write these codes to the specified register one by one, alternately, from the output of which they arrive at the input 52 of block 1 (Fig. 2).

After a delay on the delay element 16 at the time of writing the code to the register 4, the same clock pulse arrives at the clock input 56 of the memory unit 1, the address inputs of which are connected to the corresponding outputs of the decoder 8.

Considering that the counter 6 and the register 5 have now been reset to zero, then the zero code at the input of the decoder 8 and the high potential at its extreme output opens at input 53 a group of elements 24 of block 1.

The synchronizing pulse from the input 56 of block 1, acting on the synchronous input of the elements And 24 and the register 21 of block 1, writes the contents of register 4 into the register 21 of the block

1. Thus, in code 21, the code number code is generated.

In addition, from the output of the delay element 16, the sync pulse arrives at the input of the delay element 17, where it is delayed by

the recording time is the code number of the codogram to the register 21, and then enters the input of the AND 10 element opened by another input with high potential from the inverse output of the trigger 14.

Passing through the element 10 on the counting input of the counter 6, this clock increases the address generated by the counter by one. As a result, to the information outputs of the register 4 through the elements

And 25 connects register 22.

Similarly, the next code enters the next code in register 4, and the sync pulse from input 47 writes to it

next code.

In the described manner, this code is then recorded in the register 22 of block 1 and the process of entering all the components of the codogram continues until

transfer of counter 6 does not show a pulse, indicating that all components of the codogram are ready and are in registers 21–23 of block 1.

From the output of memory block 1, the outputs of all

registers 21-23 are connected to the inputs of the corresponding decoders 27-29 selector 2.

If the code decoded by the corresponding decoder is present in the device (i.e., such code is among the plurality of codes that come as part of the codograms), it opens on the corresponding output of the decoder 21, for example, And block 33 of the block 2.

Then the transfer pulse from the output of the counter 6 passes to the input 59 of the selector 2 and then through the AND 33 element to the read input of the fixed cell of the memory block 30, made in the form of a constant memory and

fixed cells of memory block 30 are written G if the received code exists in the set of codes, or O if the dialed code is not in the set of codes. From the output of fixed cells of all

blocks 30-32 of the memory in which 1 is stored, the read signals are fed to the single inputs of the flip-flops 42-44, the output potentials of which are fed to the outputs 50 of the device and displayed on the display screen.

In addition, the outputs of the flip-flops 42-44 of the selector 2 are connected to the inputs of the decoder S, which, if there are high potentials at the output of all the flip-flops 42- 44, gives a high potential to the input of the element 12, but the presence of any other codes at the input of the decoder 9 that a high potential at the output of the element OR 15 will be fed to the input of the element AND 11.

Assuming that all components of the codogram are correctly typed, then the high potential from the output of the decoder 9 opens element 12, to another input of which a transfer pulse of counter 6 arrives, which is delayed by element 18 for the response time of the decoder 9 and triggers 42-44.

Passing the element 12, the pulse arrives at the zero input of the trigger 14, confirming its zero state, and then, after a delay on the delay element 19, the trigger 14 triggered to the pulse input element And the 13, which is open to high potential from the inverse output of the original.

Passing through element 13, the sync pulse, firstly, arrives at the pulse input of elements of the 3rd group, rewriting all registers 21–23 to the device output 49, secondly, enters through the input 60 of the selector 2 and resets all triggers 42-44. Thirdly, the same pulse after the delay on element 20 at the time of the census of the code at output 49, goes to the zero inputs of registers 4 and 5, counter b, and through input 57 to reset registers 21-23.

If at least one of the components of the codogram is typed incorrectly, then the high potential from the output of the OR 15 element opens the AND 11 element.

In this case, the transfer pulse from the output of the delay element 18, having passed the element 11 and 11, will go to the single input of the trigger 14 and set it to the single state.

A high potential from the unit output of the trigger 14 is outputted at the output 51 of the device, indicating that the codogram is typed incorrectly, and the output potentials at the outputs 50 specifically indicate which component of the codogram is typed incorrectly.

To correct an error, the operator on the control panel must press a key with the name of the component of the code pattern that was typed in error. Pressing the key causes the code of the position of the component in the codogram to be input to input 46, and a clock pulse arrives at the input 48, which this code writes to register 5.

The code from the output of register 5 through the elements

OR 7 enters the inputs of the decoder 8,

which connects to the outputs of register 4

the corresponding register 21-23, in which

need to make a correction.

Thus, the entered second decoder 9, third 18, fourth 19, fifth

0 20 delay elements, the error selector 2, the second register 5 allow to establish whether the codogram components are correctly or incorrectly typed — at least one of its components — and thus helps to correct the errors, which significantly increases the reliability of the device.

Claims (1)

The invention The device for identifying features of objects, containing the first decoder, the outputs of which are connected to the inputs of the OR element, the first delay element, whose input is connected to the input of the second delay element, a memory unit, the synchronization input of which is connected to the output of the first delay element, trigger The inverse output of which is connected to one input of the first and second elements AND, the counter, the first register, the elements AND, and the group of elements OR, which are distinguished by the fact that in order to increase the reliability of the device a, it contains the second decoder, the information inputs of which are connected to the outputs of the elements of the OR group, and the outputs are connected to the address5 inputs of the memory block, the information inputs of which are connected to the outputs of the first register, whose information input is the information input of the device, asynchronous input the synchronization input of the device and connected to the input of the first delay element, the third delay element whose input is connected to the counter overflow output and the output connected 5 to one input of the third element AND, the other input of which is connected to the output of the OR element, and to one input of the fourth element AND, the other input of which is connected to the corresponding output of the decoder, the fourth delay element whose input is connected to the output of the fourth element I. And the output connected to another input of the second element AND, a single input of the trigger is connected to the output of the third element AND, a zero input is connected to the output of the fourth element AND, and the direct output is the control output of the device, the output of the second element And n connected to one input of elements AND of a group, the other inputs of which are connected to the output of the memory unit, and the outputs are informational outputs of the first group of the device, an error selector, whose information input is connected to the output of the memory unit, the synchronization input connected to the output of the second And element, The setup input is connected to the overflow output of the counter, and the outputs are the information outputs of the second group of the device and are connected to the information inputs of the first decoder, the second register, the information input of which Pogo is the second information input device Va, the sync input is the second sync input of the device, and the outputs are connected to one input of the elements OR groups, the other inputs of which are connected to the output of the counter, the counting input of which is connected to the output of the first And element, the other input of which is connected to the output of the second delay element, and a fifth delay element, the input of which is connected to the output of the second element AND, and the output is connected to the installation inputs of the memory block, the counter, the first and second registers.