JPH03220981A - Synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a highly accurate synchronizing signal by a simple circuit by specifying an address of a read-only memory stored previously with waveform data on a ternary level synchronizing signal, and converting the read data into the ternary level synchronizing signal and outputting it. CONSTITUTION:A carry signal generated when a clock counter 11 is reset is counted by a line counter 15, which is reset in response to the leading or trailing edge of a frame pulse 13 to acquire synchronism with an image frame. The output 12 of the clock counter 11 is used as a low-order address signal and the output 16 of the line counter 15 is used as a high-order address signal; and they are supplied to the read-only memory 19 stored previously with the waveform data on the ternary level synchronizing signal to read the waveform data on the ternary level synchronizing signal out of the read-only memory 19. Consequently, the highly accurate synchronizing signal can be generated by the simple circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] Video equipment that outputs a luminance signal and a color difference signal superimposed on a ternary level synchronization signal, particularly a ternary MUSE decoder that restores a high-definition signal band-compressed using the MUSE method. This invention relates to a level synchronization signal generation circuit.

[Conventional technology]

Video signals corresponding to red, green, and blue output from video equipment,
and output horizontal and vertical synchronization pulses respectively,
It was transmitted using five coaxial cables.

[Problem that the invention sought to solve]

It was necessary to output video signals corresponding to red, green, and blue, as well as horizontal and vertical synchronization pulses independently, correct transmission distortion in the transmission system, and achieve accurate phase synchronization.

In particular, in high-definition video equipment, the transmission delay difference between each channel of the signal is required to be 3.5 ns or less.

In addition, the large number of transmission cables that connect each video device has many disadvantages in terms of equipment costs, ensuring reliability, and maintenance management, and improvements are needed.

[Means to solve the problem]

Adopts a three-level synchronization signal that can detect zero crosses with minimal phase distortion even if there is transmission distortion in the transmission system.
The counter output of the clock signal synchronized with the vertical and horizontal synchronization signals specifies the address of the read-only memory that stores the waveform data of the three-level level synchronization signal in advance, converts the read data from digital to analog, and converts it to the three-level level. Output as a synchronization signal.

In particular, in the case of a high-definition MUSE signal, the frame pulse extracted from the signal and the outputs of a resampling frequency clock counter and a horizontal scanning line counter synchronized with a horizontal synchronization signal were used as address signals for the read-only memory.

[Effect]

In the main block diagram of the MUSE decoder shown in Fig. 1,
A high-definition band-compressed MUSE signal 41 output from a satellite broadcast receiver or the like is sampled at a resampling frequency of 10 output by a horizontal phase synchronization circuit 34 and converted into a digital signal 42.

A resampling frequency 10 in which the frame pulse 13 is detected by autocorrelation calculation of the digital signal 42 and the phase shift is corrected by a horizontal phase synchronization circuit 34 configured with a phase locking loop circuit including an autocorrelation calculation circuit of the digital signal 42. and outputs a horizontal synchronizing signal 14.

The horizontal scanning period ll input to the synchronization signal generation circuit 33
The resampling frequency 10 outputted from the 134 is counted as a clock signal by a clock counter 11, and the clock counter 11 is reset at the rising or falling edge of the horizontal synchronizing signal 14 to synchronize with the horizontal scanning line of the image.

A carry signal generated when the clock counter 11 is reset is counted by a line counter 15, and an in-counter 5 is reset at the rising or falling edge of the frame pulse J3 to achieve synchronization with the image frame.

The output I2 of the clock counter II is used as a lower address signal, and the output 16 of the line counter 15 is used as an upper address signal, which is supplied to a read-only memory I9 that has previously stored waveform data of a three-level synchronization signal, and is then read out. The waveform data of the three-level synchronization signal is read from the dedicated memory 19.

Furthermore, as shown in Figure 6, the three-level synchronization signal is based on one horizontal scanning period as a unit, and only the waveform data of horizontal scanning line numbers 1, 6, 7, 536, and 568 shown at the top of the waveform diagram in the same figure are used. is stored in the read-only memory 19, and the output of the line counter 15 that outputs data of the same horizontal scanning line number is supplied to the decoder circuit 17, which detects the timing of outputting each of the same waveform data, and outputs the same detection output 18. It is also possible to specify the address of the read-only memory I9 that stores each waveform data and read out the corresponding waveform data.

Furthermore, the waveform data of the three-level synchronization signal is stored in the read-only memory I9 in units of A of the horizontal scanning period, and the output timing of each waveform data is detected by decoding the output of the line counter 15 in the same manner as described above. However, the corresponding waveform data can also be read from the read-only memory I9 using the detection output 18.

FIG. 3 shows a waveform diagram of the three-level synchronization signal in units of A during one horizontal scanning period. , In the same figure, the thick solid line represents the waveform of the corresponding period, and the dotted line represents a part of the waveform before and after the same waveform.

The waveform data read from the read-only memory 19 is converted into analog data, and a synchronization signal 2 of a desired three-level level is generated.
Outputs 8.

The video signal of the corresponding line is read out from the video signal time memory 36 of the video signal processing circuit 35 shown in FIG. The luminance signal of the signal is superimposed on the synchronization signal 28 and output together with the color difference signal of the analog video signal.

FIG. 4 shows an example of a D/A converter that converts waveform data read from the read-only memory 19 into analog data, and includes an operational amplifier 27 that operates with two positive and negative power supplies (not shown).
The upper bit and lower bit data when the waveform data of the three-level synchronization signal is expressed as a 2-bit binary number are supplied to the negative phase input and the positive phase input of the circuit through resistors 23 and 24, respectively; It outputs a three-level synchronization signal 28 of positive, negative, and ground potentials.

〔Example〕

Figure 5 shows the program diagram of the MUSE decoder.
Description will be made with reference to a block diagram of main parts related to the synchronization signal generation circuit of the present invention shown in the figure.

The high-definition MUSE signal 41 inputted to the MUSE decoder is inputted to the A/D converter 31 together with the resampling frequency 10 outputted from the horizontal phase synchronization circuit 34,
It is converted into a digital signal 42.

Digital signal 42 output from the A/D converter 31
A frame detection circuit 32 and a horizontal phase synchronization circuit 3 supply the digital signal 42 to a video signal separation circuit and an audio signal separation circuit, and restore the high-definition video signal and audio signal from the separated signals.
Also supplies to 4.

The resampling frequency 10 output from the horizontal phase synchronization circuit 34 is used as a clock signal, and is supplied to the clock counter 11 of the synchronization signal generation circuit 33, and the horizontal synchronization signal 14 output from the horizontal phase synchronization circuit 34 is also supplied. The signal is supplied to the clock counter 11.

The carry signal output from the clock counter 1 is input as a clock signal to the line counter 15 of the synchronization signal generation circuit 33, and the frame pulse 13 output from the frame detection circuit 32 is also input.

The output 12 of the clock counter II and the output 16 of the line counter 15 are used as address signals and are supplied to a read-only memory 19 in which waveform data of a three-level synchronization signal of Neuivision is stored in advance.

The clock counter 11 of the read-only memory 9
And the output 12 of the line counter 15 outputs the stored data at the address designated by 16 to the D/A controller 2.
0 and outputs a three-level synchronization signal 28.

FIG. 4 shows how the waveform data of the three-level synchronization signal is stored in the read-only memory 19 as 2-bit binary digital data.
This is an example of a D/A controller in which data is stored in a computer.

In the figure, the upper bits of the 2-bit data outputted from the read-only memory 19 are input to the negative phase input 21 of the operational amplifier 27, which operates with dual positive and negative sources (not shown), through the resistor 23. Positive phase human power 2 via 27 resistors 24
2 are connected to the lower bits, respectively.

A feedback resistor 26 is connected between the connection point between the negative phase input of the operational amplifier 27 and the resistor 23 and the output of the operational amplifier 27, and a feedback resistor 26 is connected between the connection point between the positive phase input of the operational amplifier 27 and the resistor 24 and ground. A resistor 25 was connected to form an amplifier with a predetermined gain.

FIG. 2 is a block diagram of another embodiment of the synchronization signal generation circuit 33.

In the figure, a decoder circuit stores only data of different waveforms of the same three-level synchronization signal in the read-only memory I9 in units of periods of one horizontal scanning line of an image, and detects timing corresponding to the stored waveform data. 17 is supplied with the output of the line counter 15, and the decoder circuit 1
The output of 7 specifies the corresponding address in the read-only memory 19, and can be used as a read-only memory with a small storage capacity.

Furthermore, by supplying the output of the line counter 15 together with the most significant bit of the clock counter II to the decoder circuit 17 using the period of A horizontal scanning line of the image as a unit, a read-only memory with a smaller storage capacity can be obtained. You can also do it.

Said clock counter! The video signal of the corresponding line is read out from the video signal time memory 36 of the video signal processing circuit 35 shown in FIG.
The luminance signal of the analog video signal is converted into an analog signal by the D/A conversion circuit 37 and outputted as the synchronization signal 28.
They are also superimposed in the signal synthesis circuit IIISB and output together with the color difference signal of the analog video signal.

FIG. 6 shows the main part waveforms of the luminance signal and the bottomed out signal of the video signal obtained by separating and restoring the three-level synchronization signal 28 output from the synchronization signal generation circuit 33 from the digital signal 42.

〔Effect of the invention〕

Generating a high-definition three-level synchronization signal required a complex logic circuit, but according to the present invention, a highly accurate synchronization signal can be generated using a simple circuit with a small number of parts, reducing costs. It can be made cheap.

In addition, by using three-level synchronization signals, it is possible to reduce the number of transmission cables for high-definition signals, and furthermore, it is possible to reduce the effects of transmission distortion of synchronization signals caused by the same transmission cables, reducing equipment costs and reliability of high-definition receiving equipment. Benefits can be obtained in terms of maintenance and management.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the synchronization detection section of the MUSE decoder and the synchronization signal generation circuit of the present invention, FIG. 2 is a block diagram of another embodiment of the synchronization signal generation circuit of the present invention, and FIG. 3 is a three-level level synchronization A waveform diagram of the A period of the signal, FIG. 4 is a circuit diagram of a D/A converter showing an embodiment of the present invention, and FIG. 5 is a MU
FIG. 6, a block diagram of the SE decoder, is a waveform diagram of the main part of the three-level synchronization signal. In the figure, 10 is the resampling frequency, 1 is the clock counter, 2 is the counter output signal, 13 is the frame pulse, 14 is the horizontal synchronization signal, 15 is the line counter, 1
6 is the counter signal output, 17 is the decoder circuit, 18 is the decoder output signal, 19 is the read-only memory, and 20 is the D
/A converter, 21 is the same /A converter negative phase input゛, 22 is the same /A converter positive phase input, 23 to 26
is a resistor, 27 is an operational amplifier, 28 is a three-level synchronization signal output, 3 is an A/D converter, 32 is a frame detection circuit, 33 is a synchronization signal generation circuit, 34 is a horizontal phase synchronization circuit,
35 is a video signal processing circuit, 36 is a video signal memory in the video signal processing circuit, and 37 is a D/D in the video signal processing circuit.
A converter, 38 is a signal control circuit, 41 is a MUSE signal input, and 42 is a digital signal of the MUSE signal.

Claims (4)

[Claims] (1) In a video device that outputs a three-level synchronization signal generated in synchronization with the vertical and horizontal synchronization signals of a television, and superimposes the video signal of the same television, synchronization with the vertical and horizontal synchronization signals is performed. The output of the clock signal counting counter is used as an address signal, the address of the read-only memory that stores the waveform data of the three-level synchronization signal is specified in advance, and the read data is converted into a three-level synchronization signal and output. A synchronization signal generation circuit for video equipment characterized by: (2) Convert the high-definition band compressed MUSE signal to a digital signal at an internally generated resampling frequency,
M according to claim (1), characterized in that the counter output of the resampling frequency synchronized with the frame pulse and the horizontal synchronization signal detected by the autocorrelation calculation of the digital signal and the phase-locked loop circuit is used as the address signal.
USE decoder synchronization signal generation circuit. (3) Storing only waveform data of different waveforms in one horizontal scanning period of the three-level synchronization signal in the read-only memory, and decoding the output of the resampling frequency counter to a predetermined position of the three-level synchronization signal. 3. The synchronizing signal generating circuit for a MUSE decoder according to claim 2, wherein the synchronizing signal generating circuit reads out waveform data corresponding to a waveform of the MUSE decoder. (4) The MUS according to claim (2), wherein only waveform data of waveforms having different half horizontal scanning periods of the three-level synchronization signal are stored in the read-only memory.
E-decoder synchronization signal generation circuit.