JPH08275022A - Video camera equipment - Google Patents

Abstract

PURPOSE: To realize the video camera equipment in which number of signal lines between a CCU and a CHU is saved. CONSTITUTION: A return video signal DVrt is sequentially being written in a buffer memory 610 of a CCU 6. Furthermore, a phase comparator 603 of the CCU 6 compares a phase of synchronizing signals VDref, HDref obtained from a reference video signal SVref with a phase of synchronizing signals VDm, HDm obtained by a main line group video signal DVm. A horizontal phase of a return video signal DVrc read and outputted from the buffer memory 610 is controlled in a direction that a phase difference represented by horizontal phase difference data HPD outputted from the phase comparator 603 is made zero. A synthesis circuit 614 inserts a command CMD converted from vertical phase difference data VPD to an auxiliary data part of the return video signal DVrc. The return video signal DVrc with the command CMD inserted thereto is fed to a CHU 5. That is, advance synchronization information is fed from the CCU 6 to the CHU 5 by using the return video signal DVrc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera device having a camera head unit and a camera control unit. For details, in order to synchronize the main line video signal supplied from the camera head unit to the camera control unit with the reference video signal, the camera control unit uses the return video signal to send advance synchronization information to the camera head unit. By doing so, the signal line can be saved.

[0002]

2. Description of the Related Art FIG. 5 shows a camera head unit (CH
U) 1 and a camera control unit (CCU) 2 arranged on the video processing system side are shown. The camera head unit 1 has a function of performing a predetermined process on an output signal of an image pickup device on which a subject is imaged to obtain a video signal, and transmitting the video signal to the camera control unit 2 side. .

The camera control unit 2 is for adjusting the video signal so that the image quality of the video signal obtained by the camera head unit 1 becomes a predetermined value. One camera control unit 2 is provided for each camera head unit 1. And is usually connected to the camera head unit 1 by a transmission cable. The camera control unit 2 is also connected to various control devices and the like and has a function of transmitting and receiving a control signal, an intercom signal, a video signal and the like to and from the camera head unit 1.

The main line system video signal SVm is led from the camera head unit 1 to the video processing system side via the camera control unit 2. In addition, the main line video signal S
A video signal in which Vm is processed by a video processing system (for example, a video signal for on-air) is supplied to the camera head unit 1 via the camera control unit 2 as a return video signal SVrt. Although not shown, the return video signal SVrt is supplied to the monitor receiver via the camera head unit 1, and the image is monitored by the return video signal SVrt.

Further, the reference video signal SVref is supplied to the camera control unit 2, and the main video signal SVm supplied from the camera head unit 1 and the reference video signal SVref are controlled to be in phase with each other. . That is, from the camera control unit 2 to the camera head unit 1, a genlock (genlo)
ck) advance synchronization signal AD.SYNC is supplied. In the camera head unit 1, a sync signal added to the main line video signal SVm is formed on the basis of the advance sync signal AD / SYNC. Then, in the camera control unit 2, the main line video signal SVm
Since the phase of the advance synchronization signal AD / SYNC is controlled so that the phase of the reference video signal SVref and the phase of the reference video signal SVref match, the mainline system video signal SVm and the reference video signal SVref are eventually synchronized.

[0006] Fig. 6 mainly shows the main configuration of the camera head unit 1 and the camera control unit 2, that is, the configuration for matching the phases of the main line system video signal SVm and the reference video signal SVref. This Figure 6
In FIG. 5, parts corresponding to those in FIG. 5 are designated by the same reference numerals.

In the figure, an analog reference video signal S
Vref is supplied to the sync separation circuit 201 of the camera control unit 2, and the composite sync signal separated by this sync separation circuit 201 is supplied to the sync detection circuit 202 to detect the horizontal sync signal and the vertical sync signal. The vertical sync signal detected by the sync detection circuit 202 is a sync generator 203.
Is supplied as a vertical reset pulse.

The horizontal sync signal detected by the sync detection circuit 202 is supplied to a phase comparator 204 which constitutes a PLL (Phase Locked Loop) circuit. Further, an oscillation signal (clock) output from the voltage controlled oscillator (VCO) 205
Is supplied to a counter 206 for counting, and a horizontal pulse is output from this counter 206 in a horizontal cycle. The horizontal pulse output from the counter 206 is supplied to a phase comparator 204 via a phase shifter 207. .

The phase error signal output from the phase comparator 204 is supplied as a control signal to the voltage controlled oscillator 205 via the low pass filter 208. As a result, the phase of the horizontal pulse output from the counter 206 is shifted from the phase of the horizontal sync signal detected by the sync detection circuit 202 by the amount of phase adjustment by the phase shifter 207.

The horizontal pulse output from the counter 206 is supplied to the synchronization generator 203 as a horizontal reset pulse. In the synchronization generator 203, the reference horizontal synchronization signal HDref synchronized with the horizontal pulse output from the counter 206
And a reference vertical sync signal VDref synchronized with the vertical sync signal detected by the sync detection circuit 202. Sync signal H output from sync generator 203
Dref and VDref are supplied to the phase comparator 209, respectively.

The main line video signal SVm supplied from the camera head unit 1 is supplied to the sync separation circuit 210 of the camera control unit 2. Here, the video signal SVm is, for example, a component signal of a red signal R, a green signal G, and a blue signal B, and the sync separation circuit 21.
One of the color signals is supplied to 0. Sync separation circuit 2
The composite sync signal separated by 10 is supplied to the sync detection circuit 211 to be supplied to the horizontal sync signal HDm and the vertical sync signal VD.
m is detected, and these synchronizing signals HDm and VDm are supplied to the phase comparator 209, respectively.

In the phase comparator 209, the horizontal synchronizing signal HD
m is phase-compared with the horizontal synchronization signal HDref to obtain phase difference data HPD, and the vertical synchronization signal VDm is phase-compared with the vertical synchronization signal VDref to obtain phase difference data VPD.
Is obtained. The phase difference data HPD and VPD output from the phase comparator 209 are supplied to the synchronization generator 212, respectively. In the sync generator 212, the advance sync signal (composite sync signal) AD / SYNC for genlock described above is used.
Is formed. In this case, the advance synchronization signal AD · S
The YNC controls the vertical phase in the direction in which the phase difference of the vertical sync signal indicated by the phase difference data VPD becomes zero, and at the same time sets the horizontal phase in the direction in which the phase difference of the horizontal sync signal indicated by the data HPD becomes zero. Controlled.

The sync signal AD / SYNC output from the phase comparator 212 of the camera control unit 2 is supplied to the sync detection circuit 101 of the camera head unit 1.
A horizontal sync signal and a vertical sync signal are detected. The vertical sync signal detected by the sync detection circuit 101 is the sync generator 1
02 as a vertical reset pulse.

The horizontal sync signal detected by the sync detection circuit 101 is supplied to a phase comparator 103 which constitutes a PLL circuit. Further, an oscillation signal (clock) output from the voltage controlled oscillator (VCO) 104 is supplied to a counter 105 and counted, and a horizontal pulse is output from this counter 105 in a horizontal cycle and is output from the counter 105. The horizontal pulse is supplied to the phase comparator 103. The phase error signal output from the phase comparator 103 is supplied as a control signal to the voltage controlled oscillator 104 via the low pass filter 106. As a result, the phase of the horizontal pulse output from the counter 105 matches the phase of the horizontal sync signal detected by the sync detection circuit 101.

The horizontal pulse output from the counter 105 is supplied to the synchronization generator 102 as a horizontal reset pulse. The sync generator 102 forms a composite sync signal that is in sync with the horizontal pulse output from the counter 105 and in sync with the vertical sync signal detected by the sync detection circuit 101. The composite sync signal output from the sync generator 102 is supplied to the synthesizing circuit 107 and added to the color signals R, G, B as the video signal SV to obtain the main line video signal SVm.

Although not shown, the color signals R, G, B as the video signal SV obtained by the camera head unit 1 are also provided.
Is formed in synchronization with the horizontal pulse output from the counter 105 and in synchronization with the vertical synchronization signal detected by the synchronization detection circuit 101.

In the above configuration, the advance sync signal AD output from the sync generator 212 as described above.
In the SYNC, the vertical phase is controlled in the direction in which the phase difference of the vertical synchronization signal indicated by the phase difference data VPD becomes zero, and the horizontal phase in the direction in which the phase difference of the horizontal synchronization signal indicated by the data HPD becomes zero. Are controlled, the result is that the main line system video signal SVm is synchronized with the reference video signal SVref. Strictly speaking, it is shifted by the amount of phase adjustment by the phase shifter 207.

[0018]

In the above-mentioned conventional video camera apparatus, in order to synchronize the main line video signal SVm and the reference video signal SVref with each other, the camera control unit 2 advances the genlock advance to the camera head unit 1. The synchronization signal AD / SYNC is supplied. Therefore, the synchronization signal AD, between the camera control unit 2 and the camera head unit 1
It was necessary to provide a signal line for sending SYNC.

Therefore, the present invention provides a video camera device capable of saving the signal line between the camera control unit and the camera head unit.

[0020]

A video camera device according to the present invention comprises a camera head unit and a camera control unit, and a return video signal is supplied to the camera head unit via the camera control unit. The camera control unit has a buffer memory and a phase comparator for phase-comparing the reference sync signal and the sync signal obtained from the main line video signal supplied from the camera head unit. This return video signal is written in synchronization with the obtained sync signal, and the read phase of the return video signal from the buffer memory is controlled so that the phase difference indicated by the phase difference information output from the phase comparator becomes zero. , The return video signal read from the buffer memory is supplied to the camera control unit. The camera head unit synthesizes a sync signal that forms a sync signal based on the sync signal obtained from the return video signal supplied from the camera control unit and the sync signal formed by the sync generator into a video signal. And a synthesizing circuit for obtaining the main line video signal.

[0021]

In the camera control unit, the return video signal is written in the buffer memory in synchronization with the synchronizing signal. The phase comparator compares the phases of the reference sync signal and the sync signal obtained from the main line video signal supplied from the camera head unit. The read phase of the buffer memory is controlled so that the phase difference indicated by the phase difference information from the phase comparator becomes zero. Then, the return video signal read from the buffer memory is supplied to the camera control unit.

In the camera head unit, the sync generator forms a sync signal based on the sync signal obtained from the return video signal supplied from the camera control unit. Then, the sync signal formed by the sync generator is combined with the video signal to obtain the main line video signal.

A direction in which the phase difference of the return video signal supplied from the camera control unit to the camera head unit becomes zero between the reference synchronization signal and the synchronization signal obtained from the main line video signal supplied from the camera head unit. As a result, the main line video signal is synchronized with the reference synchronization signal.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This example is an example applied to a digital video camera device. FIG. 1 shows an outline of the video camera device of this example.

The video camera device of this example comprises a camera head unit (CHU) 5 and a camera control unit (CCU) 6 arranged on the video processing system side. The camera head unit 5 has a function of performing a predetermined process on an output signal of an image pickup device on which a subject is imaged to obtain a digital video signal and transmitting the video signal to the camera control unit 6 side. There is.

The camera control unit 6 is for adjusting the video signal so that the image quality of the digital video signal obtained by the camera head unit 5 becomes a predetermined value. The camera head units 5 are normally provided by a transmission cable (signal line). The camera control unit 6 is also connected to various control devices and the like, and controls the camera head unit 5 to receive a control signal, an intercom signal,
It has a function of transmitting and receiving video signals and the like.

The digital main line video signal DVm is led from the camera head unit 5 to the video processing system side via the camera control unit 6. A video signal (for example, an on-air video signal) obtained by processing the main line video signal DVm in the video processing system is supplied to the camera head unit 5 via the camera control unit 6 as a digital return video signal DVrc.
Although not shown, the return video signal DVrc is supplied to the monitor receiver via the camera head unit 5, and the image is monitored by the return video signal DVrc.

An analog reference video signal SVref is supplied to the camera control unit 6, and a main line system video signal DV supplied from the camera head unit 5.
It is controlled so that the phase of m and the phase of the reference video signal SVref match. That is, the camera control unit 6 supplies the phase-controlled return video signal DVrc to the camera head unit 5. In the camera head unit 5, a TRS added to the main line video signal DVm is formed based on TRS (Timing Reference Signal) as a synchronization signal of the return video signal DVrc. In the camera control unit 6, the phase of the return video signal DVrc is controlled so that the phases of the main line video signal DVm and the reference video signal SVref match, and as a result, the main line video signal DVm and the reference video signal SVref It will be synchronized.

FIG. 2 mainly shows a main structure of the camera head unit 5 and the camera control unit 6, that is, a structure for matching the phases of the main line video signal DVm and the reference video signal SVref. This figure 2
In FIG. 1, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, an analog reference video signal S
Vref is supplied to the sync separation circuit 601 of the camera control unit 2, and the composite sync signal separated by the sync separation circuit 201 is supplied to the sync detection circuit 602 to detect the horizontal sync signal and the vertical sync signal. The vertical synchronization signal detected by the synchronization detection circuit 602 is supplied to the phase comparator 603 as the reference vertical synchronization signal VDref.

The horizontal sync signal detected by the sync detection circuit 602 is supplied to a phase comparator 604 which constitutes a PLL circuit. An oscillation signal (clock) output from the voltage controlled oscillator (VCO) 605 is supplied to the counter 606 and counted, and a horizontal pulse is output from the counter 606 in a horizontal cycle and output from the counter 606. The horizontal pulse is supplied to the phase comparator 604 via the phase shifter 607.

The comparison error signal output from the phase comparator 604 is supplied as a control signal to the voltage controlled oscillator 605 via the low pass filter 608. As a result, the phase of the horizontal pulse output from the counter 606 is shifted from the phase of the horizontal sync signal detected by the sync detection circuit 602 by the amount of phase adjustment in the phase shifter 607. The horizontal pulse output from the counter 606 is supplied to the phase comparator 603 as the reference horizontal synchronizing signal HDref.

The main line video signal DVm supplied from the camera head unit 5 is supplied to the TRS detection circuit 609 of the camera control unit 6. In the TRS detection circuit 609, the TRS of the main line system video signal DVm is
(Timing Reference Signal) EAV (end of ac
tive video line) and SAV (start of active vid)
The H, V, F data of the fourth word of the (eo line) is detected, and the horizontal synchronizing signal HDm and the vertical synchronizing signal VDm are formed based on these H, V, F data.

FIG. 3 shows the horizontal synchronization timing relationship between, for example, a 525/60 analog video signal and a digital video signal. Analog line is 63.5 μs
Is. Digital line is 1716 words (1716
W) and is composed of 276-word digital horizontal blanking and 1440-word digital active line. Video data is arranged corresponding to the digital active line, and EAV of 4 words, auxiliary data of 268 words, and SAV of 4 words are arranged corresponding to the digital horizontal blanking. The start position of the analog line and the start position of the digital line are shifted by 32 words.

FIG. 4 shows an example of the configuration of EAV and SAV. As described above in the fourth word of each, H, V, and
Bit data of F exists. P3 to P0 are error correction codes. Here, F = 0 indicates field 1, and F =
1 indicates the field 2. Further, V = 1 indicates that the field blanking is being performed, and V = 0 indicates the other cases. H = 0 indicates SAV, and H = 1 indicates EAV.

Returning to FIG. 2, the synchronization signals HDm and VDm output from the TRS detection circuit 609 are supplied to the phase comparator 603, respectively. In the phase comparator 603, the horizontal synchronizing signal HDm is phase-compared with the horizontal synchronizing signal HDref to obtain the phase difference data HPD and the vertical synchronizing signal Vd.
Dm is phase-compared with the vertical synchronizing signal VDref to obtain phase difference data VPD.

The return video signal DVrt is supplied as write data to the buffer memory 610 of the camera control unit 6 and is also supplied to the TRS detection circuit 611. In the TRS detection circuit 611, EAV and SA which are TRSs of the return video signal DVrt.
The H, V, and F data of the fourth word of V are detected, and the horizontal synchronizing signal and the vertical synchronizing signal are formed based on these H, V, and F data.

The sync signal output from the TRS detection circuit 611 is supplied to the write control signal generator 612, and the write control signal is formed in synchronization with this sync signal. Then, the return video signal D to the buffer memory 610 described above.
The writing of Vrt is performed according to the write control signal generated by the write control signal generator 612.

The phase difference data HPD of the horizontal sync signal output from the phase comparator 603 is supplied to the read control signal generator 613. Read control signal generator 61
In 3, the read control signal is formed based on the phase difference data HPD, and the data is read from the buffer memory 610 according to the read control signal. In this case, the read phase is controlled so that the phase difference of the horizontal sync signal indicated by the phase difference data HPD becomes zero. The phase-adjusted return video signal DVrc read from the buffer memory 610 is supplied to the synthesis circuit 614.

Further, the phase difference data VPD of the vertical synchronizing signal output from the phase comparator 603 is the central processing unit (hereinafter referred to as "CPU") which constitutes the system control.
After being supplied to 615 and converted into a command CMD, it is supplied to the synthesizing circuit 614 and inserted into, for example, the auxiliary data portion of the return video signal DVrc.

The return video data DVrc output from the synthesis circuit 614 of the camera control unit 6 is supplied to the TRS detection circuit 501 of the camera head unit 5. The TRS detection circuit 501 detects H, V, and F data of the fourth word of EAV and SAV that are TRS of the return video signal DVrc, and based on these H, V, and F data, a horizontal synchronization signal and a vertical synchronization signal. A signal is formed.

The horizontal synchronizing signal output from the TRS detection circuit 501 is supplied to the phase comparator 502 which constitutes the PLL circuit. Further, the oscillation signal (clock) output from the voltage controlled oscillator (VCO) 503 is supplied to the counter 504 and is counted, and the counter 504 outputs a horizontal pulse in a horizontal cycle.
The output horizontal pulse is supplied to the phase comparator 502. The phase error signal output from the phase comparator 502 is supplied as a control signal to the voltage controlled oscillator 503 via the low pass filter 505. As a result, the phase of the horizontal pulse output from the counter 504 is TR
It is in agreement with the phase of the horizontal synchronizing signal output from the S detection circuit 501. The horizontal pulse output from the counter 504 is supplied to the synchronization generator 506 as a horizontal reset pulse.

In addition, the return video signal DVrc output from the synthesis circuit 614 of the camera control unit 6
Is supplied to the command detection circuit 507, and the command CMD inserted in the auxiliary data portion as described above is detected based on the TRS detected by the TRS detection circuit 501. Command CM detected by the command detection circuit 507
D is supplied to the CPU 508 which constitutes the system controller.

In the CPU 508, based on the command CMD, the phase difference data VP of the above-mentioned vertical synchronizing signal with respect to the vertical synchronizing signal output from the TRS detection circuit 501.
A vertical pulse advanced by the phase difference indicated by D is formed. The vertical pulse output from the CPU 508 is supplied to the synchronization generator 506 as a vertical reset pulse, and
EAV and SAV data are formed.

EAV output from the synchronization generator 506,
The SAV data is supplied to the synthesis circuit 509. In the combining circuit 509, the digital video signal DV obtained in the camera head unit 5 is combined with the EAV and SAV data output from the synchronization generator 506 to form a digital main line video signal DVm. This main line system video signal DVm is sent to the camera control unit 6 side as described above.

Although not shown, the digital video signal VD obtained by the camera head unit 1 is the counter 5
04 in synchronization with the horizontal pulse output, and CPU5
It is formed in synchronization with the vertical pulse output from 08.

In the above configuration, in the camera control unit 6, the horizontal phase of the return video signal DVrc read out from the buffer memory 610 and output is controlled so that the phase difference of the horizontal synchronizing signal indicated by the phase difference data HPD becomes zero. At the same time, the command CMD corresponding to the phase difference data VPD of the vertical synchronizing signal is inserted into, for example, the auxiliary data portion of the return video signal DVrc.

The camera head unit 5 detects the TRS of the return video signal DVrc sent from the camera control unit 6 and outputs the horizontal sync pulse phase-synchronized with the horizontal sync signal obtained from the return video signal DVrc.
Based on the command CMD detected from the auxiliary data portion of rc, and thus the vertical pulse advanced with respect to the vertical synchronizing signal obtained by detecting the TRS of the return video signal DVrc by the phase difference indicated by the phase difference data VPD. EAV and SAV data as TRS are formed. And
These EAV and SAV data are combined into a digital video signal DV to generate a digital main line video signal DVm.
Is formed. As a result, as a result, the main line video signal D
Vm is synchronized with the reference video signal SVref.
Strictly speaking, it is shifted by the amount of phase adjustment by the phase shifter 607.

As described above, in this example, the main line system video signal DVm and the reference video signal SVref supplied from the camera head unit 5 to the camera control unit 6 are supplied.
The horizontal phase of the return video signal DVrc sent from the camera control unit 6 to the camera head unit 5 side is controlled on the basis of the phase difference data HPD of the horizontal sync signal in order to synchronize with the vertical sync signal. The command CMD obtained by converting the phase difference data VPD is inserted into, for example, the auxiliary data portion of the return video signal DVrc. Therefore, the return video signal DV
Since the advance synchronization information is transmitted using rc, it is not necessary to provide a dedicated signal line for transmitting the advance synchronization information, and the signal line can be saved.

Further, in the present example, the buffer memory 61
At 0, only the horizontal phase of the return video signal DVrc is adjusted based on the phase difference data HPD of the horizontal synchronizing signal, and the vertical phase is not adjusted. Therefore, the capacity of the buffer memory 610 may be one horizontal period,
The memory capacity can be saved.

If the vertical phase is also adjusted in the buffer memory 610, the return video signal DVrc will be delayed for a maximum of one frame period in the buffer memory 610. However, since only the horizontal phase is adjusted in the buffer memory 610 in this example, the delay of the return video signal DVrc in the portion of the buffer memory 610 is within one horizontal period. Therefore, the delay of the return video signal DVrc supplied from the camera control unit 6 to the camera head unit 5 can be suppressed within one horizontal period.

In the above embodiment, only the horizontal phase of the return video signal DVrc is adjusted by the buffer memory 610, but the vertical phase may of course be adjusted. In that case, the vertical phase difference data VPD output from the phase comparator 603 is also supplied to the read control signal generator 613, and the vertical phase of the return video signal DVrc read from the buffer memory 610 is adjusted based on this data VPD. Will be done.
Further, although the above-described embodiment is an example applied to a digital video camera device, the analog video camera device as shown in FIG. 6 similarly uses the return video signal SVrt to advance the synchronization information. Can be sent from the camera control unit 2 to the camera head unit 1 side, and the signal line can be saved.

[0053]

According to the present invention, the advance synchronization information is transmitted from the camera control unit to the camera head unit using the return video signal, and it is necessary to provide a dedicated signal line for transmitting the advance synchronization information. Therefore, the signal line can be saved. Also, by adjusting only the horizontal phase of the return video signal in the buffer memory, the memory capacity of the buffer memory can be saved and the delay of the return video signal supplied to the camera head unit can be suppressed within one horizontal period. .

[Brief description of drawings]

FIG. 1 is a system diagram showing an outline of a video camera device of an embodiment.

FIG. 2 is a system diagram showing a main configuration of a camera head unit and a camera control unit according to an embodiment.

FIG. 3 is a diagram showing a horizontal synchronization timing relationship between an analog video signal and a digital video signal.

FIG. 4 E as timing reference signal TRS
It is a figure which shows the structural example of AV and SAV.

FIG. 5 is a system diagram showing an outline of a conventional video camera device.

FIG. 6 is a system diagram showing a main configuration of a conventional camera head unit and camera control unit.

[Explanation of symbols]

 5 camera head unit (CHU) 6 camera control unit (CCU) 501, 609, 611 TRS detector 506 sync generator 507 command detection circuit 508, 615 central processing unit (CPU) 509, 614 synthesis circuit 602 sync detection circuit 603 phase Comparator 610 Buffer memory 612 Write control signal generator 613 Read control signal generator

Claims (2)

[Claims] 1. A video camera device comprising a camera head unit and a camera control unit, wherein a return video signal is supplied to the camera head unit via the camera control unit, wherein the camera control unit comprises a buffer memory, It has a phase comparator for comparing the phase of the reference sync signal and the sync signal obtained from the main line video signal supplied from the camera head unit, and the buffer memory is synchronized with the sync signal obtained from the return video signal. Then, the return video signal is written, and the read phase of the return video signal from the buffer memory is controlled so that the phase difference indicated by the phase difference information output from the phase comparator becomes zero. Rita read from memory A video signal to the camera control unit, and the camera head unit to generate a sync signal based on the sync signal obtained from the return video signal supplied from the camera control unit; And a synthesizing circuit for synthesizing a synchronizing signal formed by a video signal into a video signal to obtain the main line video signal. 2. The camera control unit sets the read phase of the return video signal from the buffer memory in the direction in which the phase difference indicated by the phase difference information of the horizontal synchronizing signal output from the phase comparing means becomes zero. In addition to controlling, the command corresponding to the phase difference information of the vertical synchronizing signal output from the phase comparing means is combined with the return video signal read from the buffer memory, and the sync generator of the camera head unit is In addition to a horizontal synchronizing signal obtained from the return video signal supplied from the control unit, a synchronizing signal is formed based on a vertical reset pulse generated corresponding to a command detected from the return video signal. The video camera device according to claim 1.