JPS6390964A - Discriminating circuit for television signal field - Google Patents

Abstract

PURPOSE:To shorten the time required for generating filed discriminating signal, by discriminating the time extending from a fall of a VS to a rise of a first HS that is generated after the fall of the VS by counting the number of clocks of a clock generator. CONSTITUTION:The time extending from a fall of a vertical synchronizing signal (VS) obtained by separating and shaping a television signal, to a rise of the first horizontal synchronizing signal (HS) that is generated after the fall of the VS is discriminated by counting the number of cloks of a clock generator 5. In this way, field can be discriminated, therefore, the time required for generating a field discriminating signal becomes shorter than 60mu sec of one horizontal synchronizing period. In this way, the filed can be discriminated quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to displays having an even field and an odd field by interlaced scanning (for example, television, video, etc.).
This invention relates to a television signal field discrimination circuit used in the video signal control circuit of a tL crystal television.

2. Description of the Related Art The concept of a conventional television signal field discrimination circuit is shown in FIG. Figure 3 shows the scanning method used in domestic television broadcasting. Out of 525 scanning lines, odd fields are scanned as shown by solid lines, and even fields are scanned as shown by broken lines. Interlaced scanning is performed to scan between the scanning lines. Vertical synchronization signal (hereinafter abbreviated as VS) that separates and formats the television signal
, the horizontal synchronization signal (hereinafter abbreviated as H3) is shown in Figure 3.

In the waveform shown in b, one H3 occurs after one scanning line is scanned from left to right, so one vertical interperiod period (approximately 16
m5ec), 262 H3s occur in odd fields and 263 H3s occur in even fields. Therefore, to determine whether the field is an odd field or an even field, it is determined by counting H3 in one vertical interval, and the field determination signal (E'l/EN/○DD) is an even number field as shown in C in Figure 3B. The signal is low level in the field and high level in the odd field. Problems to be Solved by the Invention However, in the conventional discrimination circuit, the number of H8 in one vertical interval is counted, so the field discrimination signal is not generated. The problem was that approximately 16 m560 of vertical synchronization period was required for one vertical synchronization period.

The present invention solves this problem and aims to shorten the time required to generate a field discrimination signal.

Means for Solving the Problem In order to solve this problem, the television signal field discrimination circuit of the present invention calculates the time from the falling edge of vS to the rising edge of H8 that occurs first after the falling edge of vS. The determination is made by counting the number of clocks from the clock generator.

Effect With this configuration, from the falling edge of vS to 1 after the falling edge of vS
The field can be determined by counting the number of clocks of the clock generator and determining the time up to the rising edge 9 of H3, which occurs the second time, so the time required to generate the field determination signal is one horizontal opening period. This requires less time than about 6Qμsec, and field discrimination is faster than in the past.

Embodiment A block diagram of a television signal field discriminating circuit according to the present invention is shown in FIG. 1, and an explanatory diagram of its operation is shown in FIG.

Figure 2 a and b are the waveforms of VS and H3, respectively.
The difference between an odd field and an even field is not only the number of H5 in the field as shown in the conventional example, but also the time from the falling edge of vS to the rising edge 9 of H3 that occurs first after the falling edge of vS. There are also differences. That is, the time from the falling edge of VS to the rising edge of I(S that occurs first after the falling edge of VS) is T4 in an odd field and T2 in an even field.
When one horizontal period is H, T,> −H, T2<,H
It becomes a relationship. Since one horizontal period H is approximately 60 μsec, T1 is 30 μsec or more and T2 is 30 μ38 C or less.

In FIG. 1, 1 is a D type flip-flop (D
-4F), 2B, 2-person OR gate 3 is a 2-person exclusive OR gate, and 2-person exclusive OR gate 3 is a 2-person exclusive OR gate.
The output A of the R gate 3 is at a high level from the fall of VS to the first rise of H8 after the fall of VS, as shown in FIG. , the signal is high level only during the period. 5 is a clock generator with a frequency of IMHz (period: 1 μsec), which starts generating a clock at the rising edge of the human waveform, and when the clock and the signal human are 2
Human Power II) This becomes the input to gate 4. The output B of the two-manual AND gate 4 has a waveform as shown in FIG. 2B, and is a signal that generates a 1MH2 clock only during T, . . . T2. Next, this signal B enters the counter 6, and the 5th bit output C of the counter 6 is 3 times the clock of the signal B, as shown in Figure 2e.
After the second one, it becomes high level.

7 is a D-type flip-flop, and 8 is a two-input NAND gate.The output of the two-input HAND gate 8 is a signal that becomes low level only at the 32nd clock of signal B, as shown in FIG. 2(f). The time from the fall of vS to the 32nd rise of the clock of signal B is 3171 seconds, so if the signal is an odd field, it will take 31 seconds from the fall of VS.
At 7I8150, it becomes low level for 1 μsec, and the signal becomes a no-repel signal. 10 is an SR flip-flop (SR-FF), and the set input of 5R-FF10 (
A signal is input to S), and a signal E as shown in Fig. 2g, which is obtained by inverting vS by an inverter 9, is input to the reset input (R).

Therefore, the output F of 5R-FF10 is v in odd fields.
It is set and becomes high level 31 μsea after the fall of S, and in an even field, it is reset by the inverted signal of vS and becomes low level, and this signal F becomes a field discrimination signal.

Effects of the Invention As described above, in the field discrimination circuit of the present invention, field discrimination is performed 31 μsec after the fall of VS, and it is possible to obtain the effect that field discrimination can be performed much faster than the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a television signal field discrimination circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, and FIG. 3 is a block diagram of a conventional television signal field discrimination circuit. It is an explanatory diagram showing a concept. 1.7...D type flip-flop, 2...
...2-man-powered OR gate, 3...2-man-powered exclusive OR gate, 4...2-man-power AND gate, 5...Clock generator, 6...・Counter, 8...2-man power NAND gate, 9...
...Inverter, 1°...SR flip-flop. Name of agent: Patent attorney Toshio Nakao and 1 other group
1 mouth ^ to ^ to to to he to
3 (2T (II) (B> 6 momme) Contains Hakomachi period injury% (S)

Claims (1)

[Claims] It consists of a clock generator, a counter, and several gate circuits, and is separated from the television signal and shaped from the fall of the vertical synchronization signal to the rise of the horizontal synchronization signal that occurs first after the fall of the vertical synchronization signal. A television signal field discriminating circuit, characterized in that the television signal field discriminating circuit determines the time until the end of the television signal by counting the number of clocks of the clock generator.