JPS63316569A - Synchronizing device - Google Patents

Abstract

PURPOSE:To suppress horizontal zitter in the digital sampling of an image signal by using a reference clock and an inverted reference clock as system clocks in accordance with a phase difference between a synchronizing signal and the reference clock in a horizontally synchronizing device for an image signal. CONSTITUTION:A horizontally synchronizing signal generator 1 outputs a horizontally synchronizing signal from an image signal inputted from the external and the signal is compared with a reference clock outputted from a reference clock generator 2 at their phases by a phase comparator 3. When the phase difference is <=1/2 the wavelength of the reference clock, a system clock forming device 4 outputs a reference clock as it is, and in case of >=1/2, outputs an inverted reference clock as a system clock in accordance with the compared result. When the system clock is supplied, the horizontally synchronizing signal outputted from the generator 1 is synchronized with a synchronizing coincidence device 5. In said constitution, horizontal zitter in the digital sampling of an image signal is suppressed within 1/2 the reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization device for a horizontal synchronization signal and a reference clock that suppresses horizontal jitter in digital chimpling of an image signal.

[Conventional technology]

An outline of a conventional synchronizing device of this type will be explained with reference to FIGS. 5 and 6.

FIG. 5 is a block diagram of a conventional synchronization device, in which 41 is an external horizontal synchronization signal, 42 is a reference clock (system clock) generator, and 43 is a D-FF for synchronizing the external horizontal synchronization signal 41 with the reference clock.

44 is an internal horizontal synchronization signal synchronized with the reference clock.

FIG. 6 is a timing chart of signals in each part of the fs5 diagram, where 46 is the rising edge of the external horizontal synchronizing signal waveform;
47 and 49 are reference clock waveforms, both of which have different phase differences from the external horizontal synchronization signal 46. 48.50 is an internal horizontal synchronization signal waveform in which the external horizontal synchronization signal 46 is synchronized with the reference clock 47.49.

Next, the operation shown in FIG. 5 will be explained using FIG. 6.

In FIG. 5, the external horizontal synchronizing signal 41 inputs a rising edge to the D input of the D-FF4M.

The output of the reference clock generator 42 is inputted to the clock input of the D-FF 43, and the internal horizontal synchronization signal 44 delayed so as to match the rising edge of the reference clock is outputted to the output of the D-FF 43.

This situation is shown in the timing diagram of FIG. If the rising edge of the reference clock has a slight phase difference with respect to the rising edge of the external horizontal synchronizing signal waveform 1746, then the internal horizontal synchronizing signal waveform 48 will have a small delay.

On the other hand, when the rising edge of the reference clock is the reference clock waveform 49, the internal horizontal synchronization signal 50 is delayed by nearly one clock.

As described above, since the phase of the external horizontal synchronizing signal is adjusted in units of one clock of the reference clock, the jitter with the internal horizontal synchronizing signal is at most one clock of the reference clock.

An example of this type of synchronizing device is the one described in the video superimposition card circuit diagram for the Hitachi personal computer MBS1, for example.

[Problem that the invention seeks to solve]

In the above conventional contact, the horizontal synchronizing signal is time-shaped in units of one clock of the reference clock, so that the internal horizontal synchronizing signal handled internally has a phase difference of one clock with respect to the externally input horizontal synchronizing signal.

That is, the horizontal fluctuation of one clock appears on one screen, causing a visual disturbance. In order to reduce this to a level that does not affect the visual sense, the frequency of the clock must be increased to reduce the lateral vibration, which poses a problem in that the circuit design becomes more difficult.

The present invention aims to provide a synchronization device that suppresses the phase difference between an externally input horizontal synchronizing signal and an internal horizontal synchronizing signal to within half a clock of the reference clock, and halves the horizontal fluctuation on the screen using the reference clock of the same frequency. purpose.

[Means for solving problems]

The above object is achieved by providing a phase comparing means for comparing the phases of an external horizontal synchronizing signal and a reference clock, and a system clock generating means for appropriately inverting the reference clock based on the result and outputting it as a system clock.

[Effect]

Immediately after the edge of the external horizontal synchronization signal is input, the phase comparison means detects whether the reference clock is rising or falling. If the reference clock has a data ratio of 50%,
Based on this detection result, the phase difference of 1/2 clock can be detected.

Next, the system clock generating means outputs the reference clock as the system clock if the detection result is a rising edge, and outputs an inverted version of the reference clock as the system clock if the detection result is a falling edge.

Due to the above operation, the edge of the system clock immediately after the rise of the external horizontal synchronization signal is always a rising edge, so the phase difference between the external horizontal synchronization signal and the internal horizontal synchronization signal can be suppressed to within 1/2 system clock. Become.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a synchronization device according to the present invention,
1 is a horizontal synchronization signal generator that outputs a horizontal synchronization signal; 2
5 is a reference clock generator that generates a clock with a duty ratio of 50%, and 5 is the rising edge of the horizontal synchronization signal output from the horizontal synchronization signal generator and the reference clock generator 2.
A phase comparator device 4 compares the phases of reference clocks output from the phase comparator 5 and outputs the comparison results, and 4 is a system that appropriately inverts the reference clock based on the comparison results output from the phase comparator 5 and outputs it as a system clock. A clock generation device 5 is a synchronization matching device that matches the edges of the horizontal synchronization signal and the phase of the system clock to achieve synchronization.

FIG. 2 is a specific circuit diagram of the phase comparison device 6 and system clock generation device 4 shown in FIG. Device 2 occurred. For example, a reference clock with a duty ratio of 50%, 1i$, 14 is an exclusive OR (hereinafter referred to as 11X-OR) on the same chip that creates a positive inverted signal of the reference clock 12 to 5 without time delay. 13 is for normal clock generation, 14 is for inverted clock generation, 15, 16, 17.18 is D-F for soft phase ratio.
MX-OR 120, which switches the system clock to normal rotation or inversion according to the phase comparison result, is an output system clock.

Figures 3 and 4 are timing diagrams showing the operation of each part in Figure 2. Figure 3 shows an example where the reference clock becomes the system clock as is, and Figure s4 shows an example where the reference clock is inverted and becomes the system clock. 24 is the rising edge of the horizontal synchronizing signal, 25 is the rising edge of the reference clock immediately after the rising edge of the horizontal synchronizing signal, 26 is also the falling edge, 27 and 52 are the output waveforms of the D-FFI 5,
28.55 is the output waveform of D-FF16, 29 and 34 are D
- The output waveform of FF17, 3C1 and 35 are the output waveforms of D-FF18, and 51.54 is the output waveform of lX-0R19.

Next, the operation will be explained.

In FIG. 1, a phase comparator 5 compares the rising edge of the horizontal synchronizing signal generated from the horizontal synchronizing signal generator 1 and the edge of the reference clock generated from the reference clock generator. Then, the system clock generation device 4 generates a system clock based on the comparison result.

The details of this operation will be explained with reference to FIG.

The horizontal synchronization signal 11 is input to the D input of D-FFI5.14, the CK large input of D-FF15 receives a normal reference clock, and the CK large input of D-FF1d receives an inverted reference clock. has been done.

D-F depends on whether the edge of the reference clock immediately after the horizontal synchronization signal rises or falls.
F15. D-FF1! It is determined which one outputs the KH (hey) level first.

And this is D-FF 17, D-FF 18! judge.

If the rising edge of the reference clock is input immediately after the rising edge of the horizontal synchronization signal and before the falling edge,
D-FF15 outputs H level to the next stage half a clock earlier than D-FF1d.

Next stage D-FF17. In D-FF18, the output of D-FF17 first becomes 1ch level, and the clear terminal KL (low) level of D-FFI8 is input, so that D-FF
18 remains at L level even if the D-FF 14 outputs Hv level.

As a result, the lll-0R19 outputs the reference clock as it is as the system clock 31.

This situation will be explained using the timing diagram shown in FIG.

When the horizontal synchronizing signal 24 rises to H level.

In FIG. 3, the rising edge 25 of the reference clock, which immediately follows the rising edge 24 of the horizontal synchronization signal, precedes the falling edge 26.

As a result, D-FF15 outputs H level before D-PFid, and in order to transmit this to the next stage, D-FF17 outputs H level before D-PFid.
- KHV pek occurs before FF18, masks the operation of D-FF1B, and D-FF18 remains at L level output. Therefore, the %EX-OR 19 outputs the system clock 31 having the same phase as the reference clock.

On the contrary, if the falling edge 26 of the reference clock comes before the rising edge 25 as shown in FIG.
-FFI, 6 reaches the #IcH level before D-FF15, and D-FF111 masks the operation of D-FF17.

Therefore, 0-0R1? Since the inverted reference clock is output as the system clock 36, the clock is set so that the rising edge 25 of the reference clock comes within half a clock, such as within IIc%Ic immediately after the rising edge 24 of the primary horizontal synchronizing signal.

This system clock and the horizontal synchronization signal are synchronized by a matching device 5.
By synchronizing the system and the horizontal synchronizing signal, the system and horizontal synchronizing signal are synchronized with jitter within 1/2 system clock.

However, what must be noted here is that when the system clock is inverted, a whisker-like pulse is generated, as shown in the system clock waveform 36#C in FIG. 4. It is generally not good for such a pulse to appear in the system clock, but in digital sampling of one image, there is usually a horizontal retrace period around the horizontal synchronization signal, so it is necessary to eliminate the problem. is easy.

According to this embodiment, since the circuit is constructed using only standard logic, it is possible to incorporate a gate array or a logic-dedicated LSIK. Further, since the time comparison is performed, a 1f block LSI in which the delay time does not differ much depending on the gate is very effective in this embodiment. In particular, in designing a digital television, the effect of being able to assemble a circuit without using analog devices such as PLL is significant.

〔Effect of the invention〕

As explained above, according to the present invention, the phase difference between the system clock and the horizontal synchronization signal can be suppressed by half a clock.

As a result, in digital sampling of image signals, the lateral fluctuation of cycling is reduced to 1/1/2 of the sampling clock.
It can be suppressed to 2 cycles.

In other words, when this is reproduced and converted into an image, the lateral wobbling on the screen is suppressed to half a dot, and it becomes invisible to the naked eye with digital sampling using a normal sampling clock. It is possible to provide a synchronization device for the functions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the synchronization device according to the present invention, and FIG. 2 is a detailed circuit diagram of the present invention shown in FIG.
sm and FIG. 4 are timing diagrams for explaining the operation of the embodiment of the present invention, FIG. 5 is a block diagram of the conventional example, and FIG. 6 is a timing diagram showing the operation of the conventional example. 5... Phase comparison device, 4... System clock generation device. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a synchronization device that matches the phase of a synchronization signal generated from a synchronization signal generation means and a reference clock generated from a reference clock generation means, the phase difference between the edge of the synchronization signal and the edge of the reference clock is the reference clock period. a phase comparison means for comparing whether the phase difference is within 1/2 or more than 1/2, and outputs the reference clock as a system clock if the phase difference is within 1/2 clock cycle;
A synchronization device comprising a system clock generating means for outputting an inverted version of the reference clock as a system clock if the clock period is longer than the clock period, and the synchronization device is configured to suppress horizontal jitter in digital sampling of an image signal.